diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
| commit | f71fa1715793c764ffa95411e87b73179a7c7b3f (patch) | |
| tree | b4095efe0bda4413326c5860754921b7d8ae78e3 /tests/long/se/30.eon | |
| parent | 42fe2df35495685e616f74ad3342953714c7dcc1 (diff) | |
| download | gem5-f71fa1715793c764ffa95411e87b73179a7c7b3f.tar.xz | |
stats: arm: updates
Diffstat (limited to 'tests/long/se/30.eon')
4 files changed, 1163 insertions, 1163 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 048a31a06..5070249ec 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216865 # Number of seconds simulated -sim_ticks 216864820000 # Number of ticks simulated -final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216744 # Number of seconds simulated +sim_ticks 216744260000 # Number of ticks simulated +final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114758 # Simulator instruction rate (inst/s) -host_op_rate 137779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91148248 # Simulator tick rate (ticks/s) -host_mem_usage 250616 # Number of bytes of host memory used -host_seconds 2379.25 # Real time elapsed on the host -sim_insts 273037856 # Number of instructions simulated -sim_ops 327812213 # Number of ops (including micro ops) simulated +host_inst_rate 123383 # Simulator instruction rate (inst/s) +host_op_rate 148134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 97944157 # Simulator tick rate (ticks/s) +host_mem_usage 314844 # Number of bytes of host memory used +host_seconds 2212.94 # Real time elapsed on the host +sim_insts 273037857 # Number of instructions simulated +sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7584 # Number of read requests accepted +system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7583 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,8 +46,8 @@ system.physmem.perBankRdBursts::1 843 # Pe system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts -system.physmem.perBankRdBursts::5 349 # Per bank write bursts -system.physmem.perBankRdBursts::6 172 # Per bank write bursts +system.physmem.perBankRdBursts::5 348 # Per bank write bursts +system.physmem.perBankRdBursts::6 173 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts system.physmem.perBankRdBursts::9 311 # Per bank write bursts @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 428 # Pe system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts -system.physmem.perBankRdBursts::15 541 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216864583500 # Total gap between requests +system.physmem.totGap 216744023500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7584 # Read request sizes (log2) +system.physmem.readPktSize::6 7583 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 318.190664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.796192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.520878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 546 35.90% 35.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 355 23.34% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 175 11.51% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 75 4.93% 75.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.67% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 3.42% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.43% 86.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 29 1.91% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 181 11.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1521 # Bytes accessed per row activation -system.physmem.totQLat 53624000 # Total ticks spent queuing -system.physmem.totMemAccLat 195824000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7070.68 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation +system.physmem.totQLat 54921500 # Total ticks spent queuing +system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25820.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6058 # Number of row buffer hits during reads +system.physmem.readRowHits 6057 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28595013.65 # Average gap between requests +system.physmem.avgGap 28582885.86 # Average gap between requests system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5663385765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125149854750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 145015352790 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.696011 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208196147750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states +system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.684406 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1425508750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5827279860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125006088000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145036838310 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.795085 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207953796500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states +system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.812768 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1667592250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33219593 # Number of BP lookups -system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits +system.cpu.branchPred.lookups 33185861 # Number of BP lookups +system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6612086 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433729640 # number of cpu cycles simulated +system.cpu.numCycles 433488520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037856 # Number of instructions committed -system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4054236 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 273037857 # Number of instructions committed +system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.588533 # CPI: cycles per instruction -system.cpu.ipc 0.629512 # IPC: instructions per cycle -system.cpu.tickCycles 430193126 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3536514 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.587650 # CPI: cycles per instruction +system.cpu.ipc 0.629862 # IPC: instructions per cycle +system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.769078 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168782221 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37415.699623 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.769078 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -404,54 +404,54 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86649433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86649433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168696891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168696891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168760431 # number of overall hits -system.cpu.dcache.overall_hits::total 168760431 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits +system.cpu.dcache.overall_hits::total 168747655 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7278 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7278 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7284 # number of overall misses -system.cpu.dcache.overall_misses::total 7284 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 136977706 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 136977706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400661500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400661500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 537639206 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 537639206 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 537639206 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 537639206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86651492 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86651492 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses +system.cpu.dcache.overall_misses::total 7285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168704169 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168704169 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73871.833746 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73810.983800 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2771 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2771 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2771 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2771 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507 system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109140792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109140792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220213500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329354292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329354292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329675042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329675042 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36897 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.852858 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73252007 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1886.285394 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36918 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852858 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146620518 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146620518 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73252007 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73252007 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73252007 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73252007 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73252007 # number of overall hits -system.cpu.icache.overall_hits::total 73252007 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses -system.cpu.icache.overall_misses::total 38835 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728387498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728387498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728387498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728387498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728387498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728387498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73290842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73290842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73290842 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73290842 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73290842 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73290842 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18755.954629 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18755.954629 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18755.954629 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18755.954629 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits +system.cpu.icache.overall_hits::total 73120141 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses +system.cpu.icache.overall_misses::total 38856 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18742.414247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18742.414247 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3421 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3421 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215060000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85447750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300507750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181443000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181443000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215060000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266890750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 481950750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215060000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266890750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 481950750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214664750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 86513250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301178000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181997750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181997750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214664750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 268511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 483175750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214664750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 268511000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 483175750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174856 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62846.288720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65327.025994 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63532.293869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63574.982481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63574.982481 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 44377 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58975998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4730 # Transaction distribution -system.membus.trans_dist::ReadResp 4730 # Transaction distribution +system.membus.trans_dist::ReadReq 4729 # Transaction distribution +system.membus.trans_dist::ReadResp 4729 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7584 # Request fanout histogram +system.membus.snoop_fanout::samples 7583 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7584 # Request fanout histogram -system.membus.reqLayer0.occupancy 8969000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7583 # Request fanout histogram +system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40262750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index bf0686636..4230ac10b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112554 # Number of seconds simulated -sim_ticks 112553814500 # Number of ticks simulated -final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112557 # Number of seconds simulated +sim_ticks 112556618500 # Number of ticks simulated +final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123079 # Simulator instruction rate (inst/s) -host_op_rate 147770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50736526 # Simulator tick rate (ticks/s) -host_mem_usage 257068 # Number of bytes of host memory used -host_seconds 2218.40 # Real time elapsed on the host -sim_insts 273037219 # Number of instructions simulated -sim_ops 327811601 # Number of ops (including micro ops) simulated +host_inst_rate 95501 # Simulator instruction rate (inst/s) +host_op_rate 114659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39369115 # Simulator tick rate (ticks/s) +host_mem_usage 319836 # Number of bytes of host memory used +host_seconds 2859.01 # Real time elapsed on the host +sim_insts 273037220 # Number of instructions simulated +sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory -system.physmem.bytes_read::total 468928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7327 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7327 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 117696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 162752 # Number of bytes read from this memory +system.physmem.bytes_read::total 467520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1839 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2543 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7305 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1662026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1045660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1445957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4153643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1662026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1662026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1662026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1045660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1445957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4153643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7305 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7305 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 467520 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 468928 # Total read bytes from the system interface side +system.physmem.bytesReadSys 467520 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,13 +51,13 @@ system.physmem.perBankRdBursts::2 601 # Pe system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts -system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 255 # Per bank write bursts +system.physmem.perBankRdBursts::6 146 # Per bank write bursts +system.physmem.perBankRdBursts::7 247 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts -system.physmem.perBankRdBursts::12 547 # Per bank write bursts +system.physmem.perBankRdBursts::12 540 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts system.physmem.perBankRdBursts::14 615 # Per bank write bursts system.physmem.perBankRdBursts::15 555 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112553656000 # Total gap between requests +system.physmem.totGap 112556460000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7327 # Read request sizes (log2) +system.physmem.readPktSize::6 7305 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,78 +190,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation -system.physmem.totQLat 96387273 # Total ticks spent queuing -system.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1395 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 333.121147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.861490 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.787983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 501 35.91% 35.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 324 23.23% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 138 9.89% 69.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 72 5.16% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 60 4.30% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 40 2.87% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 25 1.79% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.37% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 202 14.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1395 # Bytes accessed per row activation +system.physmem.totQLat 103629565 # Total ticks spent queuing +system.physmem.totMemAccLat 240598315 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36525000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14186.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32936.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5921 # Number of row buffer hits during reads +system.physmem.readRowHits 5900 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15361492.56 # Average gap between requests -system.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 15408139.63 # Average gap between requests +system.physmem.pageHitRate 80.77 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4800600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2619375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 28509000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.186805 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states +system.physmem_0.actBackEnergy 3210095790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64714428750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75311688315 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.136839 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107655127862 # Time in different power states system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1137230638 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5692680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3106125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28033200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.241613 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states +system.physmem_1.actBackEnergy 3321763065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64616466750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75326296620 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.266714 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107490739638 # Time in different power states system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1301464112 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37745757 # Number of BP lookups -system.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299874 # Number of BTB hits +system.cpu.branchPred.lookups 37745745 # Number of BP lookups +system.cpu.branchPred.condPredicted 20165036 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746193 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18664433 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299757 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.688361 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7225644 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -381,95 +381,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225107630 # number of cpu cycles simulated +system.cpu.numCycles 225113238 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12251417 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334051298 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37745745 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24525401 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210778013 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510671 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2374 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89095174 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21831 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224788353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.802613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228565 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51103569 22.73% 22.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42898008 19.08% 41.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30051948 13.37% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734828 44.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108576617 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113387886 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 224788353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167674 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483926 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27670582 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63851253 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108576447 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23069494 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620577 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880022 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363530011 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6168132 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620577 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44985380 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17900890 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 342489 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113387887 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46551130 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355747905 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2899336 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6599141 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 195125 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7751977 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21225499 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2892433 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403402217 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533894130 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350207887 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194891394 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 31172166 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 55319848 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416628 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88482470 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1658909 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1843123 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353235356 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25451552 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 346405014 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2300418 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25451778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73600174 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 224788353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.541027 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099686 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40435382 17.99% 17.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78271933 34.82% 52.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 61035531 27.15% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34789384 15.48% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9595504 4.27% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 651863 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8756 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224788353 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9471637 7.62% 7.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7328 0.01% 7.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available @@ -488,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 257062 0.21% 7.83% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126985 0.10% 7.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 92941 0.07% 8.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68002 0.05% 8.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 719490 0.58% 8.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 316341 0.25% 8.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 682827 0.55% 9.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53603507 43.13% 52.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58947270 47.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110656004 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148356 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,105 +522,105 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798499 1.96% 34.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668326 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332485 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592467 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930113 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182308 2.07% 46.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148959 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91886991 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85885220 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346404668 # Type of FU issued -system.cpu.iq.rate 1.538840 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251708205 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127016687 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346405014 # Type of FU issued +system.cpu.iq.rate 1.538803 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124293390 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358809 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756692141 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251708637 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223263072 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287500048 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127016707 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424886 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303165485 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167532919 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5066153 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684353 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13689 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10190 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6106853 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 154467 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 567717 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620577 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2121612 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 331103 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353264247 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 92416628 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88482470 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8045 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 337585 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10190 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220609 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439082 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659691 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342414524 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90667106 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3990490 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 867 # number of nop insts executed -system.cpu.iew.exec_refs 175255989 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752931 # Number of branches executed -system.cpu.iew.exec_stores 84589034 # Number of stores executed -system.cpu.iew.exec_rate 1.521114 # Inst execution rate -system.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340687891 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153731206 # num instructions producing a value -system.cpu.iew.wb_consumers 266896125 # num instructions consuming a value +system.cpu.iew.exec_refs 175256113 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752933 # Number of branches executed +system.cpu.iew.exec_stores 84589007 # Number of stores executed +system.cpu.iew.exec_rate 1.521077 # Inst execution rate +system.cpu.iew.wb_sent 340946411 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340687958 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153730891 # num instructions producing a value +system.cpu.iew.wb_consumers 266895127 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513444 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back +system.cpu.iew.wb_rate 1.513407 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575997 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23077429 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611435 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221063225 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.482889 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.052142 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87359166 39.52% 39.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70369846 31.83% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20804571 9.41% 80.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13442893 6.08% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8809424 3.99% 90.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4514904 2.04% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2991184 1.35% 94.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2424669 1.10% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10346568 4.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037831 # Number of instructions committed -system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 221063225 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037832 # Number of instructions committed +system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168107892 # Number of memory references committed system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563525 # Number of branches committed +system.cpu.commit.branches 30563526 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction @@ -653,95 +653,95 @@ system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Cl system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction -system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561599370 # The number of ROB reads -system.cpu.rob.rob_writes 705507733 # The number of ROB writes -system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273037219 # Number of Instructions Simulated -system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824458 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads -system.cpu.ipc 1.212919 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331300708 # number of integer regfile reads -system.cpu.int_regfile_writes 136940215 # number of integer regfile writes -system.cpu.fp_regfile_reads 187107289 # number of floating regfile reads -system.cpu.fp_regfile_writes 132177847 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads -system.cpu.cc_regfile_writes 80242169 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads +system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction +system.cpu.commit.bw_lim_events 10346568 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561603777 # The number of ROB reads +system.cpu.rob.rob_writes 705508335 # The number of ROB writes +system.cpu.timesIdled 50687 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324885 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037220 # Number of Instructions Simulated +system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.824478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824478 # CPI: Total CPI of All Threads +system.cpu.ipc 1.212888 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.212888 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331301011 # number of integer regfile reads +system.cpu.int_regfile_writes 136940115 # number of integer regfile writes +system.cpu.fp_regfile_reads 187107432 # number of floating regfile reads +system.cpu.fp_regfile_writes 132177980 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297030870 # number of cc regfile reads +system.cpu.cc_regfile_writes 80242369 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182848919 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes system.cpu.dcache.tags.replacements 1533856 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.842901 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163689178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 106.681825 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 84489000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.842901 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336633512 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336633512 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82631334 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82631334 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80965560 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80965560 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70478 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70478 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits -system.cpu.dcache.overall_hits::total 163667410 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163596894 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163596894 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163667372 # number of overall hits +system.cpu.dcache.overall_hits::total 163667372 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2773234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2773234 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1087139 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1087139 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses -system.cpu.dcache.overall_misses::total 3860348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3860373 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3860373 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3860391 # number of overall misses +system.cpu.dcache.overall_misses::total 3860391 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22353219965 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22353219965 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8921439031 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8921439031 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31274658996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31274658996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31274658996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31274658996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85404568 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85404568 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70496 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70496 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167457267 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167457267 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167527763 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167527763 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032472 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032472 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses @@ -752,36 +752,36 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8060.343976 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8060.343976 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8206.346227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8206.346227 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8101.460402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8101.460402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8101.422627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8101.422627 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 920181 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 117395 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.838332 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks system.cpu.dcache.writebacks::total 966341 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459520 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1459520 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866494 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 866494 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2326014 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2326014 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2326014 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2326014 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses @@ -792,16 +792,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9970454284 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9970454284 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1720952041 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1720952041 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 709000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 709000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11691406325 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11691406325 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11692115325 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11692115325 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -812,76 +812,76 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7589.516656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7589.516656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7799.642145 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7799.642145 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64454.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64454.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7619.733273 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7619.733273 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7620.140726 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7620.140726 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715719 # number of replacements -system.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 715712 # number of replacements +system.cpu.icache.tags.tagsinuse 511.827844 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88374047 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716224 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.388838 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326692250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.827844 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999664 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178906226 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits -system.cpu.icache.overall_hits::total 88373879 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses -system.cpu.icache.overall_misses::total 721118 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 178906541 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178906541 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88374047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88374047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88374047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88374047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88374047 # number of overall hits +system.cpu.icache.overall_hits::total 88374047 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721111 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721111 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721111 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721111 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721111 # number of overall misses +system.cpu.icache.overall_misses::total 721111 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5974650710 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5974650710 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5974650710 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5974650710 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5974650710 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5974650710 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89095158 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89095158 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89095158 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89095158 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89095158 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89095158 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8285.341244 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8285.341244 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8285.341244 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8285.341244 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 59670 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2032 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.365157 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -891,291 +891,291 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 4886 system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716232 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 716232 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 716232 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 716232 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 716232 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 716232 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5192936459 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5192936459 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5192936459 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5192936459 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5192936459 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5192936459 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716225 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716225 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716225 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716225 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716225 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716225 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5193352944 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5193352944 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5193352944 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5193352944 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5193352944 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5193352944 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7250.355275 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7250.355275 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7251.007636 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7251.007636 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7251.007636 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7251.007636 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 404550 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404804 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 188 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 405309 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 405577 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 209 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28140 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 27975 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5993.813794 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2806615 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7301 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 384.415149 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5974.758413 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2806551 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7279 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 385.568210 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.149913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2681.614006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 610.589138 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 126.460737 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157175 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163673 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037267 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.365833 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 517 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6784 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 2575.130596 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.592596 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 609.586326 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 109.448896 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.157173 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037206 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006680 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.364670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6782 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5743 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031555 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414062 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51684538 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51684538 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 712391 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1312672 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2025063 # number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5741 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.413940 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 51684404 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51684404 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 712384 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1312658 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2025042 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003648 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003648 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002117 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015565 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60140.537462 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64888.297872 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61381.170331 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5903.946949 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65502.176398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65502.176398 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62077.812474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60140.537462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65157.015769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5903.946949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13543.310315 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2029950 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029950 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31609 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431544 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5466625 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32706 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32515 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.009730 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3216936 99.03% 99.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 31609 0.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1075177011 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301798469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 6562 # Transaction distribution -system.membus.trans_dist::ReadResp 6562 # Transaction distribution +system.membus.trans_dist::ReadReq 6500 # Transaction distribution +system.membus.trans_dist::ReadResp 6500 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 765 # Transaction distribution -system.membus.trans_dist::ReadExResp 765 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 805 # Transaction distribution +system.membus.trans_dist::ReadExResp 805 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14612 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 467520 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7328 # Request fanout histogram +system.membus.snoop_fanout::samples 7306 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7306 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7328 # Request fanout histogram -system.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7306 # Request fanout histogram +system.membus.reqLayer0.occupancy 9226230 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38266679 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 833e406c9..08c45e0cd 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.201717 # Number of seconds simulated -sim_ticks 201717313500 # Number of ticks simulated -final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 201717314000 # Number of ticks simulated +final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235958 # Simulator instruction rate (inst/s) -host_op_rate 1483905 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 913112758 # Simulator tick rate (ticks/s) -host_mem_usage 308700 # Number of bytes of host memory used -host_seconds 220.91 # Real time elapsed on the host -sim_insts 273037594 # Number of instructions simulated -sim_ops 327811949 # Number of ops (including micro ops) simulated +host_inst_rate 854590 # Simulator instruction rate (inst/s) +host_op_rate 1026030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 631341281 # Simulator tick rate (ticks/s) +host_mem_usage 304088 # Number of bytes of host memory used +host_seconds 319.51 # Real time elapsed on the host +sim_insts 273037595 # Number of instructions simulated +sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory -system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 403434628 # number of cpu cycles simulated +system.cpu.numCycles 403434629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037594 # Number of instructions committed -system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed +system.cpu.committedInsts 273037595 # Number of instructions committed +system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured @@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 1174407516 # nu system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read +system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written system.cpu.num_mem_refs 168107829 # number of memory refs system.cpu.num_load_insts 85732235 # Number of load instructions system.cpu.num_store_insts 82375594 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 403434627.998000 # Number of busy cycles +system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 30563490 # Number of branches fetched +system.cpu.Branches 30563491 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Cl system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 327812144 # Class of executed instruction -system.membus.trans_dist::ReadReq 434895827 # Transaction distribution -system.membus.trans_dist::ReadResp 434906722 # Transaction distribution +system.cpu.op_class::total 327812145 # Class of executed instruction +system.membus.trans_dist::ReadReq 434895828 # Transaction distribution +system.membus.trans_dist::ReadResp 434906723 # Transaction distribution system.membus.trans_dist::WriteReq 82052672 # Transaction distribution system.membus.trans_dist::WriteResp 82052672 # Transaction distribution system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution @@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 54062 # Tr system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 517024351 # Request fanout histogram +system.membus.snoop_fanout::samples 517024352 # Request fanout histogram system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::3 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::3 348660274 67.44% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 517024351 # Request fanout histogram +system.membus.snoop_fanout::total 517024352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 426aa68c6..eb13035d6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235404500 # Number of ticks simulated -final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 517235405500 # Number of ticks simulated +final_tick 517235405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 693666 # Simulator instruction rate (inst/s) -host_op_rate 832772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1315500911 # Simulator tick rate (ticks/s) -host_mem_usage 318184 # Number of bytes of host memory used -host_seconds 393.19 # Real time elapsed on the host -sim_insts 272739285 # Number of instructions simulated -sim_ops 327433743 # Number of ops (including micro ops) simulated +host_inst_rate 520716 # Simulator instruction rate (inst/s) +host_op_rate 625139 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 987510163 # Simulator tick rate (ticks/s) +host_mem_usage 313820 # Number of bytes of host memory used +host_seconds 523.78 # Real time elapsed on the host +sim_insts 272739286 # Number of instructions simulated +sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470809 # number of cpu cycles simulated +system.cpu.numCycles 1034470811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739285 # Number of instructions committed -system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed +system.cpu.committedInsts 272739286 # Number of instructions committed +system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured @@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 1215888421 # nu system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read +system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written system.cpu.num_mem_refs 168107847 # number of memory refs system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034470810.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 30563502 # Number of branches fetched +system.cpu.Branches 30563503 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction @@ -206,14 +206,14 @@ system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Cl system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 327812213 # Class of executed instruction +system.cpu.op_class::total 327812214 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.445034 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445034 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235818500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235818500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235818500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235818500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.098302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52685.098302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52649.810225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52649.810225 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75951500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75951500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229066000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 229066000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229226500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 229226500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47380.848409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47380.848409 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51187.932961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51187.932961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51189.481912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51189.481912 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1766.007655 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007655 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -362,44 +362,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 26 system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits -system.cpu.icache.overall_hits::total 348644749 # number of overall hits +system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits +system.cpu.icache.overall_hits::total 348644750 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312482000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312482000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312482000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312482000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312482000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312482000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.046081 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20027.046081 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.046081 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20027.046081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.046081 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20027.046081 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,37 +414,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18527.046081 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18527.046081 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18527.046081 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18527.046081 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18527.046081 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18527.046081 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.765010 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623059 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714789 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id @@ -455,40 +455,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 12995 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 238 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 254 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137027000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 222081500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) @@ -503,27 +503,27 @@ system.cpu.l2cache.demand_accesses::total 20081 # n system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851806 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.027607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.695906 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.027607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.112689 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.027607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.112689 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -533,48 +533,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105625000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171072000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383436 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |