diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | |
parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt')
-rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | 1009 |
1 files changed, 524 insertions, 485 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index fb73a0a48..a78600dd4 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.560955 # Number of seconds simulated -sim_ticks 560955232000 # Number of ticks simulated -final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.504258 # Number of seconds simulated +sim_ticks 504258263000 # Number of ticks simulated +final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 326346 # Simulator instruction rate (inst/s) -host_op_rate 326346 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197101410 # Simulator tick rate (ticks/s) -host_mem_usage 309500 # Number of bytes of host memory used -host_seconds 2846.02 # Real time elapsed on the host +host_inst_rate 397765 # Simulator instruction rate (inst/s) +host_op_rate 397765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215954385 # Simulator tick rate (ticks/s) +host_mem_usage 262596 # Number of bytes of host memory used +host_seconds 2335.02 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 184896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18519872 # Number of bytes read from this memory -system.physmem.bytes_read::total 18704768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 184896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 184896 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory +system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185088 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289373 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292267 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 329609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33014884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33344493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 329609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 329609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7607937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7607937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7607937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 329609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33014884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40952430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292262 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 367050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36727212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37094262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 367050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 367050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8463346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8463346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8463346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 367050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36727212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 45557607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292267 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292262 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292267 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18684608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18704768 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18685248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18705088 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18033 # Per bank write bursts -system.physmem.perBankRdBursts::1 18359 # Per bank write bursts +system.physmem.perBankRdBursts::1 18363 # Per bank write bursts system.physmem.perBankRdBursts::2 18394 # Per bank write bursts -system.physmem.perBankRdBursts::3 18332 # Per bank write bursts -system.physmem.perBankRdBursts::4 18249 # Per bank write bursts -system.physmem.perBankRdBursts::5 18255 # Per bank write bursts -system.physmem.perBankRdBursts::6 18314 # Per bank write bursts -system.physmem.perBankRdBursts::7 18296 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18236 # Per bank write bursts +system.physmem.perBankRdBursts::3 18341 # Per bank write bursts +system.physmem.perBankRdBursts::4 18245 # Per bank write bursts +system.physmem.perBankRdBursts::5 18249 # Per bank write bursts +system.physmem.perBankRdBursts::6 18313 # Per bank write bursts +system.physmem.perBankRdBursts::7 18290 # Per bank write bursts +system.physmem.perBankRdBursts::8 18231 # Per bank write bursts +system.physmem.perBankRdBursts::9 18232 # Per bank write bursts system.physmem.perBankRdBursts::10 18229 # Per bank write bursts system.physmem.perBankRdBursts::11 18376 # Per bank write bursts -system.physmem.perBankRdBursts::12 18263 # Per bank write bursts -system.physmem.perBankRdBursts::13 18132 # Per bank write bursts -system.physmem.perBankRdBursts::14 18061 # Per bank write bursts -system.physmem.perBankRdBursts::15 18191 # Per bank write bursts +system.physmem.perBankRdBursts::12 18272 # Per bank write bursts +system.physmem.perBankRdBursts::13 18137 # Per bank write bursts +system.physmem.perBankRdBursts::14 18064 # Per bank write bursts +system.physmem.perBankRdBursts::15 18188 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts +system.physmem.perBankWrBursts::9 4183 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 560955150000 # Total gap between requests +system.physmem.totGap 504258181000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292262 # Read request sizes (log2) +system.physmem.readPktSize::6 292267 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4051 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,121 +193,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 220.533003 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.789866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.043159 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 38344 36.85% 36.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 44004 42.28% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8921 8.57% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 721 0.69% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1372 1.32% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1145 1.10% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 668 0.64% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 598 0.57% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8294 7.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104067 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.768889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.564435 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 763.185509 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.78% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 103155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.473443 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.311324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.647767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37345 36.20% 36.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43741 42.40% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9241 8.96% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 735 0.71% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1396 1.35% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1157 1.12% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 662 0.64% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 564 0.55% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8314 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103155 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.893801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.549322 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 747.524050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4050 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4050 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.461235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.440549 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.842853 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3116 76.94% 76.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 76.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 932 23.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4050 # Writes before turning the bus around for reads -system.physmem.totQLat 2934449500 # Total ticks spent queuing -system.physmem.totMemAccLat 8408455750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459735000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10051.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463077 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.442287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.845052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 933 23.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads +system.physmem.totQLat 3567632750 # Total ticks spent queuing +system.physmem.totMemAccLat 9041826500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12219.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28801.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30969.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 37.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 37.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.32 # Data bus utilization in percentage -system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing -system.physmem.readRowHits 202530 # Number of row buffer hits during reads -system.physmem.writeRowHits 52011 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes -system.physmem.avgGap 1562788.59 # Average gap between requests -system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140391200 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing +system.physmem.readRowHits 203404 # Number of row buffer hits during reads +system.physmem.writeRowHits 52048 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes +system.physmem.avgGap 1404814.55 # Average gap between requests +system.physmem.pageHitRate 71.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 388939320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 212218875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140243000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109486358955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240531047250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388619465820 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.784540 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 399461576500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18731440000 # Time in different power states +system.physmem_0.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 104730111945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 210683510250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 350306824590 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.703966 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 349825620000 # Time in different power states +system.physmem_0.memoryStateTime::REF 16838120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142759852250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 137589656250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 394276680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 215131125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136522400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109506441195 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240513431250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388620069450 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.785616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399429681750 # Time in different power states -system.physmem_1.memoryStateTime::REF 18731440000 # Time in different power states +system.physmem_1.actEnergy 390829320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 213250125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136538000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215511840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105447215835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 210054471750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 350393179590 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.875219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 348773258750 # Time in different power states +system.physmem_1.memoryStateTime::REF 16838120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 142792236250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125747709 # Number of BP lookups -system.cpu.branchPred.condPredicted 81143389 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12156447 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103980471 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83512685 # Number of BTB hits +system.cpu.branchPred.lookups 123840342 # Number of BP lookups +system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 102061444 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68186680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.315740 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691016 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 66.809441 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691358 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9446 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14052117 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14048642 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3475 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11780 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537764 # DTB read hits -system.cpu.dtb.read_misses 198464 # DTB read misses +system.cpu.dtb.read_hits 237538322 # DTB read hits +system.cpu.dtb.read_misses 198467 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736228 # DTB read accesses -system.cpu.dtb.write_hits 98304946 # DTB write hits -system.cpu.dtb.write_misses 7177 # DTB write misses +system.cpu.dtb.read_accesses 237736789 # DTB read accesses +system.cpu.dtb.write_hits 98305180 # DTB write hits +system.cpu.dtb.write_misses 7178 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312123 # DTB write accesses -system.cpu.dtb.data_hits 335842710 # DTB hits -system.cpu.dtb.data_misses 205641 # DTB misses +system.cpu.dtb.write_accesses 98312358 # DTB write accesses +system.cpu.dtb.data_hits 335843502 # DTB hits +system.cpu.dtb.data_misses 205645 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048351 # DTB accesses -system.cpu.itb.fetch_hits 316984906 # ITB hits -system.cpu.itb.fetch_misses 120 # ITB misses +system.cpu.dtb.data_accesses 336049147 # DTB accesses +system.cpu.itb.fetch_hits 285763790 # ITB hits +system.cpu.itb.fetch_misses 119 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316985026 # ITB accesses +system.cpu.itb.fetch_accesses 285763909 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,83 +325,118 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1121910464 # number of cpu cycles simulated +system.cpu.numCycles 1008516526 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30861351 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.207928 # CPI: cycles per instruction -system.cpu.ipc 0.827864 # IPC: instructions per cycle -system.cpu.tickCycles 1059707465 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62202999 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.085840 # CPI: cycles per instruction +system.cpu.ipc 0.920946 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction +system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction +system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction +system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 928789150 # Class of committed instruction +system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked +system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776530 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.728000 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322866540 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 898816500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.728000 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999201 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999201 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 411.972126 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 901583500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.342308 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999107 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 951 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1398 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648211872 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648211872 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224702494 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224702494 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164046 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322866540 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322866540 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322866540 # number of overall hits -system.cpu.dcache.overall_hits::total 322866540 # number of overall hits +system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 321596153 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 321596153 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 321596153 # number of overall hits +system.cpu.dcache.overall_hits::total 321596153 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137154 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849083 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849083 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849083 # number of overall misses -system.cpu.dcache.overall_misses::total 849083 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24904735500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24904735500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9954481000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9954481000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34859216500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34859216500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34859216500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34859216500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225414423 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225414423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses +system.cpu.dcache.overall_misses::total 849082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25457059500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25457059500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10110916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10110916000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35567975500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35567975500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35567975500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35567975500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 224144035 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 224144035 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323715623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323715623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323715623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323715623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 322445235 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 322445235 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 322445235 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 322445235 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003176 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41055.134186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41055.134186 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41889.918170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41889.918170 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,16 +445,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88497 # number of writebacks -system.cpu.dcache.writebacks::total 88497 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks +system.cpu.dcache.writebacks::total 88489 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68143 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68457 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68457 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68457 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68457 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -424,85 +463,85 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780626 system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24185998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24185998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4992658500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4992658500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29178656500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29178656500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29178656500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29178656500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24738054000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24738054000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5071007000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5071007000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29809061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29809061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29809061000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29809061000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003175 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003175 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002421 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002421 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10567 # number of replacements -system.cpu.icache.tags.tagsinuse 1685.376446 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316972597 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12308 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25753.379672 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12309 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23214.841173 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376446 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.822938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.822938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.158478 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823320 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823320 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633982120 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633982120 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316972597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316972597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316972597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316972597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316972597 # number of overall hits -system.cpu.icache.overall_hits::total 316972597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12309 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12309 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12309 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12309 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12309 # number of overall misses -system.cpu.icache.overall_misses::total 12309 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 349738000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 349738000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 349738000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 349738000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 349738000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 349738000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316984906 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316984906 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316984906 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316984906 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316984906 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316984906 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28413.193598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28413.193598 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285751480 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285751480 # number of overall hits +system.cpu.icache.overall_hits::total 285751480 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12310 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12310 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12310 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12310 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12310 # number of overall misses +system.cpu.icache.overall_misses::total 12310 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352350500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352350500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352350500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352350500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352350500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352350500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 285763790 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 285763790 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 285763790 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 285763790 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 285763790 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 285763790 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28623.111292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28623.111292 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,133 +552,133 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 10567 # number of writebacks system.cpu.icache.writebacks::total 10567 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12309 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12309 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12309 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12309 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12309 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12309 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 337430000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 337430000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337430000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 337430000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27413.274840 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27413.274840 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12310 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12310 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12310 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12310 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 340041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 340041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340041500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 340041500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259935 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32594.451091 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218218 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292671 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.162414 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259940 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292676 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.162330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2600.597713 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 77.726752 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29916.126627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.079364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002372 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.912968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994704 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2630.640415 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.297977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29869.711599 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.080281 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002420 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.911551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994252 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2660 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29372 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13001938 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13001938 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88497 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88497 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13001951 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20586193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20779973000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193779500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20586193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20779973000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.234788 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312989 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312989 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368584 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368584 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312992 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312992 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368590 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368590 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1580032 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2079 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2079 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 723923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881298 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12309 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12310 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35184 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35186 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2372966 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57087872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259935 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1052870 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001975 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044393 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 2372968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259940 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1052876 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001976 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044414 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050791 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2079 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050795 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2081 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052870 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889080000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052876 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889072500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18462000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18463500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225617 # Transaction distribution +system.membus.trans_dist::ReadResp 225622 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191173 # Transaction distribution +system.membus.trans_dist::CleanEvict 191176 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225617 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842380 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22972480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225622 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842393 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842393 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22972800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 550118 # Request fanout histogram +system.membus.snoop_fanout::samples 550126 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550118 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 550126 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550118 # Request fanout histogram -system.membus.reqLayer0.occupancy 918693000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 550126 # Request fanout histogram +system.membus.reqLayer0.occupancy 918516000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556459000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556053500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |