diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 1178 |
1 files changed, 597 insertions, 581 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 8443dfdcb..5cf480155 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.626365 # Number of seconds simulated -sim_ticks 626365181000 # Number of ticks simulated -final_tick 626365181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629815 # Number of seconds simulated +sim_ticks 629814900000 # Number of ticks simulated +final_tick 629814900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114572 # Simulator instruction rate (inst/s) -host_op_rate 114572 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39364843 # Simulator tick rate (ticks/s) -host_mem_usage 295992 # Number of bytes of host memory used -host_seconds 15911.79 # Real time elapsed on the host +host_inst_rate 180734 # Simulator instruction rate (inst/s) +host_op_rate 180734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62438874 # Simulator tick rate (ticks/s) +host_mem_usage 248904 # Number of bytes of host memory used +host_seconds 10086.90 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30294656 # Number of bytes read from this memory -system.physmem.bytes_read::total 30470720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295232 # Number of bytes read from this memory +system.physmem.bytes_read::total 30471488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473354 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476117 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 281088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48365805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48646893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 281088 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 281088 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6836446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6836446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6836446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 281088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48365805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55483340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476105 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 279854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48101803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48381656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 279854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 279854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6799001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6799001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6799001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 279854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48101803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55180657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476117 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30470720 # Total number of bytes read from memory +system.physmem.cpureqs 543025 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30471488 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30470720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30471488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 93 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29984 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29806 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29791 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4199 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4202 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4160 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 29663 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4110 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4171 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4205 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 626365119500 # Total gap between requests +system.physmem.totGap 629814837500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476105 # Categorize read packet sizes +system.physmem.readPktSize::6 476117 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 406602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 406568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2909 # Wh system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2248288249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 16547544249 # Sum of mem lat for all requests -system.physmem.totBusLat 1904048000 # Total cycles spent in databus access -system.physmem.totBankLat 12395208000 # Total cycles spent in bank access -system.physmem.avgQLat 4723.18 # Average queueing delay per request -system.physmem.avgBankLat 26039.70 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34762.87 # Average memory access latency -system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.totQLat 2509077325 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20518523575 # Sum of mem lat for all requests +system.physmem.totBusLat 2380165000 # Total cycles spent in databus access +system.physmem.totBankLat 15629281250 # Total cycles spent in bank access +system.physmem.avgQLat 5270.81 # Average queueing delay per request +system.physmem.avgBankLat 32832.35 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 43103.15 # Average memory access latency +system.physmem.avgRdBW 48.38 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time system.physmem.avgWrQLen 11.00 # Average write queue length over time -system.physmem.readRowHits 265467 # Number of row buffer hits during reads -system.physmem.writeRowHits 48790 # Number of row buffer hits during writes -system.physmem.readRowHitRate 55.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.92 # Row buffer hit rate for writes -system.physmem.avgGap 1153499.31 # Average gap between requests -system.cpu.branchPred.lookups 388924238 # Number of BP lookups -system.cpu.branchPred.condPredicted 255857711 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25855826 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 319270007 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258448229 # Number of BTB hits +system.physmem.readRowHits 143855 # Number of row buffer hits during reads +system.physmem.writeRowHits 46184 # Number of row buffer hits during writes +system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes +system.physmem.avgGap 1159826.60 # Average gap between requests +system.cpu.branchPred.lookups 389306486 # Number of BP lookups +system.cpu.branchPred.condPredicted 255918117 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25837227 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 318716729 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258426851 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.949736 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57345473 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6929 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.083554 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57314223 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6830 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522560373 # DTB read hits -system.cpu.dtb.read_misses 588728 # DTB read misses +system.cpu.dtb.read_hits 523161150 # DTB read hits +system.cpu.dtb.read_misses 589917 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 523149101 # DTB read accesses -system.cpu.dtb.write_hits 283071161 # DTB write hits -system.cpu.dtb.write_misses 50270 # DTB write misses +system.cpu.dtb.read_accesses 523751067 # DTB read accesses +system.cpu.dtb.write_hits 283054328 # DTB write hits +system.cpu.dtb.write_misses 50219 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283121431 # DTB write accesses -system.cpu.dtb.data_hits 805631534 # DTB hits -system.cpu.dtb.data_misses 638998 # DTB misses +system.cpu.dtb.write_accesses 283104547 # DTB write accesses +system.cpu.dtb.data_hits 806215478 # DTB hits +system.cpu.dtb.data_misses 640136 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 806270532 # DTB accesses -system.cpu.itb.fetch_hits 395323042 # ITB hits -system.cpu.itb.fetch_misses 713 # ITB misses +system.cpu.dtb.data_accesses 806855614 # DTB accesses +system.cpu.itb.fetch_hits 394785394 # ITB hits +system.cpu.itb.fetch_misses 699 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 395323755 # ITB accesses +system.cpu.itb.fetch_accesses 394786093 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,98 +234,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1252730363 # number of cpu cycles simulated +system.cpu.numCycles 1259629801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410516643 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3276851782 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388924238 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315793702 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630639053 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158095234 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 69542401 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6974 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 395323042 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11287657 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1242455631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.637399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410360591 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3276218906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 389306486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315741074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630494032 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158021665 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72839727 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7225 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394785394 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10887979 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1245397368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.630661 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141486 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 611816578 49.24% 49.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57562553 4.63% 53.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43380535 3.49% 57.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71885087 5.79% 63.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129158557 10.40% 73.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46353903 3.73% 77.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41221359 3.32% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7475471 0.60% 81.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233601588 18.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614903336 49.37% 49.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57906135 4.65% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43369742 3.48% 57.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71861713 5.77% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128784934 10.34% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45918421 3.69% 77.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41219044 3.31% 80.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7530301 0.60% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233903742 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1242455631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310461 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.615768 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438637304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56111569 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606899212 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9069214 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131738332 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31728331 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12429 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3195294876 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46495 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131738332 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467849375 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21501203 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 26667 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586406570 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34933484 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3096787172 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15151 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28695106 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2055570524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3581032022 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3460282692 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120749330 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1245397368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309064 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.600938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438252598 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 59249665 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 607151892 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9059684 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131683529 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32106155 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12464 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3195982000 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46456 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131683529 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467489876 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24458626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586624719 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35112981 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3097789893 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15390 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28842141 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2055592035 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3582007579 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3461235411 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120772168 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 670601454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4229 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 95 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109203185 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 744330520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351486216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69160897 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8862018 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2624452005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 84 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160789811 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17925786 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 801345385 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726874664 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1242455631 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.739128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803652 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670622965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109569448 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 744863024 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351426191 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68774306 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8838853 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2625568629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 106 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2161657606 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17941272 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 802459111 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 727402983 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 67 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1245397368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.735717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803838 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 445618907 35.87% 35.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197093468 15.86% 51.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251212495 20.22% 71.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120765174 9.72% 81.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104645405 8.42% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79514591 6.40% 96.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24185782 1.95% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17651908 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767901 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 448194916 35.99% 35.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197399515 15.85% 51.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251498314 20.19% 72.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120129049 9.65% 81.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104781180 8.41% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79785428 6.41% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24208472 1.94% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17632328 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768166 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1242455631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1245397368 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146234 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146254 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available @@ -354,118 +354,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25650345 69.73% 72.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9987945 27.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25630359 69.68% 72.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10007683 27.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234634682 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851271 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589669482 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293155183 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235285403 57.15% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851426 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589902835 27.29% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293138748 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160789811 # Type of FU issued -system.cpu.iq.rate 1.724864 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36784524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017024 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5467643878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3337715121 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990557348 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101685 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88155822 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73610149 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2120121697 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449886 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62086371 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2161657606 # Type of FU issued +system.cpu.iq.rate 1.716105 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36784296 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017017 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5472336078 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3339899399 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1991115322 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151102070 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88201964 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73610146 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2120988960 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77450190 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62844771 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233260494 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21308 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76027 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140691320 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 233792998 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 726346 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76067 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140631295 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2184 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2432 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131738332 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7963688 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 401158 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987881141 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 737486 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 744330520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351486216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191221 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1459 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76027 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25850018 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 29386 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25879404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066687986 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 523149239 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94101825 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131683529 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10419712 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 524131 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2988971416 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 730880 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 744863024 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351426191 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 106 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195253 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76067 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25831488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 28075 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25859563 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2067932709 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 523751206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93724897 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363429052 # number of nop insts executed -system.cpu.iew.exec_refs 806271170 # number of memory reference insts executed -system.cpu.iew.exec_branches 277685226 # Number of branches executed -system.cpu.iew.exec_stores 283121931 # Number of stores executed -system.cpu.iew.exec_rate 1.649747 # Inst execution rate -system.cpu.iew.wb_sent 2066566988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2064167497 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1181646251 # num instructions producing a value -system.cpu.iew.wb_consumers 1754266128 # num instructions consuming a value +system.cpu.iew.exec_nop 363402681 # number of nop insts executed +system.cpu.iew.exec_refs 806856273 # number of memory reference insts executed +system.cpu.iew.exec_branches 278042301 # Number of branches executed +system.cpu.iew.exec_stores 283105067 # Number of stores executed +system.cpu.iew.exec_rate 1.641699 # Inst execution rate +system.cpu.iew.wb_sent 2067106315 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2064725468 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181149065 # num instructions producing a value +system.cpu.iew.wb_consumers 1753530061 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.647735 # insts written-back per cycle +system.cpu.iew.wb_rate 1.639153 # insts written-back per cycle system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961921272 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 963038308 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25843781 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1110717299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.808730 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509348 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25825176 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1113713839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.803863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507965 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 491335332 44.24% 44.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228930715 20.61% 64.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119800633 10.79% 75.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58838434 5.30% 80.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50772069 4.57% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24138536 2.17% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19157540 1.72% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16738195 1.51% 90.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101005845 9.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 494406511 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228855545 20.55% 64.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119827890 10.76% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58850017 5.28% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50714183 4.55% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24146625 2.17% 87.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19124586 1.72% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16719001 1.50% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101069481 9.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1110717299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1113713839 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101005845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101069481 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3974983920 # The number of ROB reads -system.cpu.rob.rob_writes 6073558017 # The number of ROB writes -system.cpu.timesIdled 212495 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10274732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3979033860 # The number of ROB reads +system.cpu.rob.rob_writes 6075737407 # The number of ROB writes +system.cpu.timesIdled 331555 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14232433 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.687164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.687164 # CPI: Total CPI of All Threads -system.cpu.ipc 1.455256 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.455256 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2628560765 # number of integer regfile reads -system.cpu.int_regfile_writes 1497106363 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811457 # number of floating regfile reads -system.cpu.fp_regfile_writes 52660996 # number of floating regfile writes +system.cpu.cpi 0.690949 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690949 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447285 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447285 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2629419671 # number of integer regfile reads +system.cpu.int_regfile_writes 1497304474 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811610 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661263 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 8336 # number of replacements -system.cpu.icache.tagsinuse 1656.236510 # Cycle average of tags in use -system.cpu.icache.total_refs 395310182 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1655.843165 # Cycle average of tags in use +system.cpu.icache.total_refs 394772509 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39342.175756 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 39288.665307 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1656.236510 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808709 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 395310182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 395310182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 395310182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 395310182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 395310182 # number of overall hits -system.cpu.icache.overall_hits::total 395310182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12860 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12860 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12860 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12860 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12860 # number of overall misses -system.cpu.icache.overall_misses::total 12860 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 302484999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 302484999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 302484999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 302484999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 302484999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 302484999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 395323042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 395323042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 395323042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 395323042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 395323042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 395323042 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1655.843165 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808517 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808517 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394772509 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394772509 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394772509 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394772509 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394772509 # number of overall hits +system.cpu.icache.overall_hits::total 394772509 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12885 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12885 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12885 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12885 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12885 # number of overall misses +system.cpu.icache.overall_misses::total 12885 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310466999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310466999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310466999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310466999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310466999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310466999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394785394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394785394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394785394 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394785394 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394785394 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394785394 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23521.384059 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23521.384059 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23521.384059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23521.384059 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 562 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24095.226931 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24095.226931 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24095.226931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24095.226931 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.466667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.375000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2811 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2811 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2811 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2811 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2811 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2811 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2836 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2836 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2836 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2836 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2836 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2836 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10049 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10049 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10049 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10049 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10049 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10049 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 227447999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 227447999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 227447999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 227447999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 227447999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 227447999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233497999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 233497999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233497999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 233497999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233497999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 233497999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22633.893820 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22633.893820 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22633.893820 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22633.893820 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22633.893820 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22633.893820 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23235.943776 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23235.943776 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23235.943776 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23235.943776 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23235.943776 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308777 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308777 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42205.507441 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55420.098032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55331.142744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44466.346127 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44466.346127 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527785 # number of replacements -system.cpu.dcache.tagsinuse 4094.883301 # Cycle average of tags in use -system.cpu.dcache.total_refs 668274960 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531881 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 436.244695 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 304908000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.883301 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999727 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999727 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 458541726 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458541726 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733214 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 668274940 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 668274940 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 668274940 # number of overall hits -system.cpu.dcache.overall_hits::total 668274940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925848 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925848 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061682 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061682 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2987530 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987530 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987530 # number of overall misses -system.cpu.dcache.overall_misses::total 2987530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59762661000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59762661000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33641566357 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33641566357 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93404227357 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93404227357 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93404227357 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93404227357 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460467574 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460467574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1527805 # number of replacements +system.cpu.dcache.tagsinuse 4094.859699 # Cycle average of tags in use +system.cpu.dcache.total_refs 668117069 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531901 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 436.135931 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314208000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.859699 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999722 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999722 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458383895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458383895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733146 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733146 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 668117041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 668117041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 668117041 # number of overall hits +system.cpu.dcache.overall_hits::total 668117041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925777 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925777 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061750 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061750 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2987527 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987527 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987527 # number of overall misses +system.cpu.dcache.overall_misses::total 2987527 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64904546500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64904546500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35420882879 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35420882879 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 100325429379 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 100325429379 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 100325429379 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 100325429379 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460309672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460309672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 671262470 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 671262470 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 671262470 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 671262470 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004182 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004182 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 671104568 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 671104568 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 671104568 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 671104568 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004451 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004451 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004451 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004451 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31031.868039 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31031.868039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31687.045986 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31687.045986 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31264.699386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31264.699386 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11600 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 365 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33703.043758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33703.043758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33360.850369 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33360.850369 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33581.430186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33581.430186 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14466 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 388 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.780822 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 137 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.283505 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95985 # number of writebacks -system.cpu.dcache.writebacks::total 95985 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465605 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465605 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990044 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455649 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455649 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455649 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455649 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460243 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460243 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531881 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531881 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531881 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531881 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35985859000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35985859000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676864000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676864000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39662723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39662723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39662723000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39662723000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks +system.cpu.dcache.writebacks::total 95989 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990108 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455627 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455627 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455627 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455627 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460258 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460258 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531900 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531900 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531900 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531900 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39601531500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39601531500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899018500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899018500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43500550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43500550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43500550000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43500550000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003172 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002282 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002282 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24643.746965 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24643.746965 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51325.609313 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51325.609313 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27119.544286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27119.544286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54423.641160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54423.641160 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |