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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt | 45 |
1 files changed, 40 insertions, 5 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 75c422cba..6bfc9d3ce 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1945820 # Simulator instruction rate (inst/s) -host_op_rate 1945820 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 973120006 # Simulator tick rate (ticks/s) -host_mem_usage 280320 # Number of bytes of host memory used -host_seconds 1032.46 # Real time elapsed on the host +host_inst_rate 2670371 # Simulator instruction rate (inst/s) +host_op_rate 2670371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1335473702 # Simulator tick rate (ticks/s) +host_mem_usage 265688 # Number of bytes of host memory used +host_seconds 752.33 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 2009421175 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 266706457 # Number of branches fetched +system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction +system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction +system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction +system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction +system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction +system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction +system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction +system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2009421070 # Class of executed instruction ---------- End Simulation Statistics ---------- |