diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | |
parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | 186 |
1 files changed, 93 insertions, 93 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index ed560b063..a8bcfc08a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.813572 # Number of seconds simulated -sim_ticks 2813572242000 # Number of ticks simulated -final_tick 2813572242000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.811836 # Number of seconds simulated +sim_ticks 2811836424000 # Number of ticks simulated +final_tick 2811836424000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1893151 # Simulator instruction rate (inst/s) -host_op_rate 1893151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2651343461 # Simulator tick rate (ticks/s) -host_mem_usage 227888 # Number of bytes of host memory used -host_seconds 1061.19 # Real time elapsed on the host +host_inst_rate 1325085 # Simulator instruction rate (inst/s) +host_op_rate 1325085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1854626286 # Simulator tick rate (ticks/s) +host_mem_usage 228472 # Number of bytes of host memory used +host_seconds 1516.12 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475279 # Nu system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33558000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33612069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1521721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1521721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1521721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33558000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35133790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33578716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33632818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54103 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54103 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1522660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1522660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1522660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33578716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35155479 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5627144484 # number of cpu cycles simulated +system.cpu.numCycles 5623672848 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5627144484 # Number of busy cycles +system.cpu.num_busy_cycles 5623672848 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.417406 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.427768 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.417406 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721883 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721883 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1478.427768 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.721889 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.721889 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 248319000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 248319000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 248319000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 248319000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 248319000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 248319000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 237582000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 237582000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 237582000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 237582000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 237582000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 237582000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23435.164213 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23435.164213 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22421.857305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216531000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216531000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216531000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216531000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216531000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216531000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.192384 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.209846 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1063975000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.192384 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999803 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999803 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.209846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999807 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999807 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567803000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79567803000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3816006000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3816006000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83383809000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83383809000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83383809000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83383809000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81853590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81853590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81853590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81853590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54494.092713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54494.092713 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53566.024227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53566.024227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53494.043698 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793377000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78793377000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793377000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78793377000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1479705 # number of replacements -system.cpu.l2cache.tagsinuse 32703.875584 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32704.499819 # Cycle average of tags in use system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3255.326122 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.503711 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29415.045751 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.099345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3254.482584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.474832 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29416.542403 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.099319 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.897676 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.897722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998062 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits |