diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | 430 |
1 files changed, 215 insertions, 215 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 8acd26381..eff48cf7e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.286250 # Number of seconds simulated -sim_ticks 1286249820000 # Number of ticks simulated -final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1286249817500 # Number of ticks simulated +final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1681245 # Simulator instruction rate (inst/s) -host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2328806930 # Simulator tick rate (ticks/s) -host_mem_usage 298588 # Number of bytes of host memory used -host_seconds 552.32 # Real time elapsed on the host +host_inst_rate 1412500 # Simulator instruction rate (inst/s) +host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1956550284 # Simulator tick rate (ticks/s) +host_mem_usage 303116 # Number of bytes of host memory used +host_seconds 657.41 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,30 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 224031 # Transaction distribution -system.membus.trans_dist::ReadResp 224031 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 357362 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 357362 # Request fanout histogram -system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572499640 # number of cpu cycles simulated +system.cpu.numCycles 2572499635 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572499640 # Number of busy cycles +system.cpu.num_busy_cycles 2572499635 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.dcache.tags.replacements 776432 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits +system.cpu.dcache.overall_hits::total 335031269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses +system.cpu.dcache.overall_misses::total 780528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks +system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id @@ -181,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -199,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -219,34 +304,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257900 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy @@ -284,17 +369,17 @@ system.cpu.l2cache.demand_misses::total 290679 # nu system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses system.cpu.l2cache.overall_misses::total 290679 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11537659000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11649615000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15003355000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15115311000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15003355000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15115311000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11648595000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11761628000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 113033000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15147615000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15260648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 113033000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses) @@ -319,17 +404,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.369493 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,17 +436,17 @@ system.cpu.l2cache.demand_mshr_misses::total 290679 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8875123000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8961243000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11541043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11627163000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11541043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11627163000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses @@ -373,127 +458,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks -system.cpu.dcache.writebacks::total 91660 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution @@ -523,5 +499,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 9252000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 357362 # Request fanout histogram +system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |