stats: update stats for insts/ops and master id changes

1 files changed, 235 insertions, 149 deletions

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 668a6f1dd..19236d338 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds                                  2.813468                       # Nu
 sim_ticks                                2813467842000                       # Number of ticks simulated
 final_tick                               2813467842000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1954286                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2736861040                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213480                       # Number of bytes of host memory used
-host_seconds                                  1027.99                       # Real time elapsed on the host
+host_inst_rate                                2306294                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2306294                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3229827855                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215660                       # Number of bytes of host memory used
+host_seconds                                   871.09                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
+sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94708160                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 152128                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  4281472                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   39                       # Nu
 system.cpu.numCycles                       5626935684                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       2008987605                       # Number of instructions executed
+system.cpu.committedInsts                  2008987605                       # Number of instructions committed
+system.cpu.committedOps                    2008987605                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
 system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
@@ -79,26 +82,39 @@ system.cpu.icache.total_refs               2009410475                       # To
 system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               189638.587675                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1478.423269                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.721886                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             2009410475                       # number of ReadReq hits
-system.cpu.icache.demand_hits              2009410475                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             2009410475                       # number of overall hits
-system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                10596                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      248178000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       248178000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      248178000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         2009421071                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          2009421071                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         2009421071                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23421.857305                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23421.857305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23421.857305                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1478.423269                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.721886                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.721886                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       2009410475                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   2009410475                       # number of overall hits
+system.cpu.icache.overall_hits::total      2009410475                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        10596                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         10596                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        10596                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          10596                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        10596                       # number of overall misses
+system.cpu.icache.overall_misses::total         10596                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    248178000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    248178000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    248178000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    248178000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    248178000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    248178000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   2009421071                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   2009421071                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   2009421071                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   2009421071                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   2009421071                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   2009421071                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    216390000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    216390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    216390000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10596                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        10596                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        10596                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        10596                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        10596                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        10596                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216390000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    216390000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    216390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216390000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    216390000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1526048                       # number of replacements
 system.cpu.dcache.tagsinuse               4095.204626                       # Cycle average of tags in use
@@ -134,32 +148,49 @@ system.cpu.dcache.total_refs                720334778                       # To
 system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             1049839000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.204626                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999806                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              720334778                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1530144                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    79658418000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    3815994000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     83474412000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    83474412000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54553.304787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54553.304787                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4095.204626                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999806                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999806                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      210722944                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     720334778                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        720334778                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    720334778                       # number of overall hits
+system.cpu.dcache.overall_hits::total       720334778                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1458192                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1458192                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        71952                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        71952                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1530144                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1530144                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1530144                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1530144                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  79658418000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  79658418000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3815994000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3815994000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83474412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83474412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83474412000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83474412000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    511070026                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    511070026                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    721864922                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    721864922                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    721864922                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    721864922                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002853                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000341                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002120                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002120                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54628.209454                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54553.304787                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54553.304787                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   107612                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  75283842000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3600138000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  78883980000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  78883980000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       107612                       # number of writebacks
+system.cpu.dcache.writebacks::total            107612                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1458192                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1458192                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1530144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1530144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1530144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1530144                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75283842000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75283842000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3600138000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3600138000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78883980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  78883980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78883980000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  78883980000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002853                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000341                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51628.209454                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51553.304787                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51553.304787                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1479797                       # number of replacements
 system.cpu.l2cache.tagsinuse             31929.841726                       # Cycle average of tags in use
@@ -199,36 +232,75 @@ system.cpu.l2cache.total_refs                   63431                       # To
 system.cpu.l2cache.sampled_refs               1512480                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.041938                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         28848.012979                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          3081.828747                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.880371                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.094050                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 55846                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              107612                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                5079                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  60925                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 60925                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1412942                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             66873                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              1479815                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             1479815                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   73472984000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3477396000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    76950380000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   76950380000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1468788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          107612                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           71952                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.961978                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.929411                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.960457                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.960457                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  3081.828747                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     33.409968                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  28814.603011                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.094050                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001020                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.879352                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.974421                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8219                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        47627                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          55846                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       107612                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       107612                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         5079                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         8219                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        52706                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           60925                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8219                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        52706                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          60925                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2377                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1410565                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1412942                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66873                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66873                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2377                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1477438                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1479815                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2377                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1477438                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1479815                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    123604000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73349380000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  73472984000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3477396000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3477396000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    123604000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  76826776000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  76950380000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    123604000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  76826776000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  76950380000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10596                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1458192                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1468788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       107612                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       107612                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        71952                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        71952                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        10596                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1530144                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1540740                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10596                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1530144                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1540740                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.224330                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.967338                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.929411                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.224330                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.965555                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.224330                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.965555                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -237,30 +309,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   66898                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1412942                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        66873                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         1479815                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        1479815                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  56517680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2674920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  59192600000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  59192600000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.961978                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.929411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.960457                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.960457                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66898                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2377                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1410565                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1412942                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66873                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66873                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2377                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1477438                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1479815                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2377                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1477438                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1479815                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     95080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56422600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56517680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2674920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2674920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     95080000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59097520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  59192600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     95080000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59097520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  59192600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.967338                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.929411                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.965555                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.965555                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------