stats: Update stats for unified cache configuration

This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.

1 files changed, 184 insertions, 184 deletions

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index a8bcfc08a..c58eb2bea 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.811836                       # Number of seconds simulated
-sim_ticks                                2811836424000                       # Number of ticks simulated
-final_tick                               2811836424000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.769740                       # Number of seconds simulated
+sim_ticks                                2769739533000                       # Number of ticks simulated
+final_tick                               2769739533000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1325085                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1325085                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1854626286                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228472                       # Number of bytes of host memory used
-host_seconds                                  1516.12                       # Real time elapsed on the host
+host_inst_rate                                1761560                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1761559                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2428616742                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226024                       # Number of bytes of host memory used
+host_seconds                                  1140.46                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            152128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          94417856                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             94569984                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       152128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          152128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4281472                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4281472                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2377                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1475279                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1477656                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66898                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66898                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                54103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             33578716                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33632818                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           54103                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              54103                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1522660                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1522660                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1522660                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               54103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            33578716                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               35155479                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            137792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          30284544                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30422336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       137792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          137792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2153                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             473196                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                475349                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                49749                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             10934077                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                10983826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           49749                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              49749                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1546034                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1546034                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1546034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               49749                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            10934077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               12529860                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -67,7 +67,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       5623672848                       # number of cpu cycles simulated
+system.cpu.numCycles                       5539479066                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  2008987605                       # Number of instructions committed
@@ -86,18 +86,18 @@ system.cpu.num_mem_refs                     722298387                       # nu
 system.cpu.num_load_insts                   511488910                       # Number of load instructions
 system.cpu.num_store_insts                  210809477                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5623672848                       # Number of busy cycles
+system.cpu.num_busy_cycles                 5539479066                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   9046                       # number of replacements
-system.cpu.icache.tagsinuse               1478.427768                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1478.418050                       # Cycle average of tags in use
 system.cpu.icache.total_refs               2009410475                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               189638.587675                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1478.427768                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.721889                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.721889                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1478.418050                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.721884                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.721884                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
@@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst        10596                       # n
 system.cpu.icache.demand_misses::total          10596                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        10596                       # number of overall misses
 system.cpu.icache.overall_misses::total         10596                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    237582000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    237582000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    237582000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    237582000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    237582000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    237582000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    228174000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    228174000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    228174000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    228174000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    228174000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    228174000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   2009421071                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   2009421071                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   2009421071                       # number of demand (read+write) accesses
@@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000005
 system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22421.857305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22421.857305                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21533.975085                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21533.975085                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        10596
 system.cpu.icache.demand_mshr_misses::total        10596                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        10596                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        10596                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216390000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    216390000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    216390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216390000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    216390000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    206982000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    206982000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    206982000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    206982000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    206982000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    206982000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1526048                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.209846                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.197836                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             1041395000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4095.209846                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999807                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999807                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    4095.197836                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999804                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits
@@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data      1530144                       # n
 system.cpu.dcache.demand_misses::total        1530144                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1530144                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1530144                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  78109548000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  78109548000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  36022065000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36022065000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data   3744042000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total   3744042000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  81853590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  81853590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  81853590000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  81853590000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39766107000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39766107000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39766107000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39766107000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    511070026                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    511070026                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
@@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002120
 system.cpu.dcache.demand_miss_rate::total     0.002120                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002120                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002120                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53566.024227                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53566.024227                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53494.043698                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53494.043698                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53494.043698                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53494.043698                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25988.473634                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25988.473634                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       109771                       # number of writebacks
-system.cpu.dcache.writebacks::total            109771                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        96129                       # number of writebacks
+system.cpu.dcache.writebacks::total             96129                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1458192                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1458192                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71952                       # number of WriteReq MSHR misses
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1530144
 system.cpu.dcache.demand_mshr_misses::total      1530144                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1530144                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1530144                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75193164000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75193164000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33105681000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33105681000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3600138000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total   3600138000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78793302000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  78793302000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78793302000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  78793302000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36705819000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  36705819000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36705819000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36705819000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000341                       # mshr miss rate for WriteReq accesses
@@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002120
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002120                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               1479705                       # number of replacements
-system.cpu.l2cache.tagsinuse             32704.499819                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   65761                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               1512436                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.043480                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                442570                       # number of replacements
+system.cpu.l2cache.tagsinuse             32706.854192                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1089464                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                475302                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.292151                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  3254.482584                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     33.474832                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  29416.542403                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.099319                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001022                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.897722                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.998062                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8219                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        49786                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          58005                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       109771                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       109771                       # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks  1300.510334                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     26.518402                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  31379.825456                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.039688                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000809                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.957636                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.998134                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8443                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1051869                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1060312                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        96129                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        96129                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         5079                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8219                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        54865                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           63084                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8219                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        54865                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          63084                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2377                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1408406                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1410783                       # number of ReadReq misses
+system.cpu.l2cache.demand_hits::cpu.inst         8443                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1056948                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1065391                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8443                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1056948                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1065391                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2153                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       406323                       # number of ReadReq misses
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 system.cpu.l2cache.ReadExReq_misses::cpu.data        66873                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66873                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2377                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1475279                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1477656                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2377                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1475279                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1477656                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    123604000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73237112000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  73360716000                       # number of ReadReq miss cycles
+system.cpu.l2cache.demand_misses::cpu.inst         2153                       # number of demand (read+write) misses
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+system.cpu.l2cache.overall_misses::cpu.data       473196                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       475349                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    111956000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  21128799000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  21240755000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3477396000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total   3477396000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    123604000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  76714508000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  76838112000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    123604000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  76714508000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  76838112000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    111956000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  24606195000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  24718151000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    111956000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  24606195000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  24718151000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        10596                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data      1458192                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total      1468788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       109771                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       109771                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        96129                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        96129                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        71952                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        71952                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        10596                       # number of demand (read+write) accesses
@@ -328,28 +328,28 @@ system.cpu.l2cache.demand_accesses::total      1540740                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst        10596                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1530144                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      1540740                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.224330                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.965858                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.960508                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.203190                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278648                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.278104                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.929411                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.929411                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.224330                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.964144                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.959056                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.224330                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.964144                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.959056                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.203190                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.309249                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.308520                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.203190                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.309249                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.308520                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.007383                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.007344                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.006340                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000.006311                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.006340                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000.006311                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66898                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2377                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1408406                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1410783                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2153                       # number of ReadReq MSHR misses
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 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66873                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66873                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2377                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1475279                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1477656                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2377                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1475279                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1477656                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     95080000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56336240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56431320000                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     86120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  16252923000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  16339043000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2674920000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2674920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     95080000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59011160000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  59106240000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     95080000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59011160000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  59106240000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.965858                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.960508                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     86120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  18927843000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  18927843000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  19013963000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.203190                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278648                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.278104                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.929411                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.929411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964144                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.959056                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964144                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.959056                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.203190                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.309249                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.308520                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.203190                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.309249                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.308520                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------