diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing | |
parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing')
-rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 217f3cee7..3b39f56f2 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 5539479066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use -system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9046 # number of replacements +system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442570 # number of replacements -system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 442570 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use -system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1526048 # number of replacements +system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits |