diff options
author | Steve Reinhardt <stever@gmail.com> | 2013-09-28 15:25:17 -0400 |
---|---|---|
committer | Steve Reinhardt <stever@gmail.com> | 2013-09-28 15:25:17 -0400 |
commit | fbc1feb39ac19379983ca714f4c7fadcd9fdabf6 (patch) | |
tree | 59e49142d5930eb044e9fc09d94c5060a810d545 /tests/long/se/40.perlbmk/ref/alpha/tru64 | |
parent | e5c319db43751f45b2bcca1d018fc39d4561ef9c (diff) | |
download | gem5-fbc1feb39ac19379983ca714f4c7fadcd9fdabf6.tar.xz |
tests: update reference outputs
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64')
6 files changed, 160 insertions, 65 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 11091dc51..cb1d4f78d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,6 +30,11 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=DerivO3CPU children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload @@ -43,7 +49,7 @@ backComSize=5 branchPred=system.cpu.branchPred cachePorts=200 checker=Null -clock=500 +clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -92,6 +98,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -121,11 +128,9 @@ RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 globalCtrBits=2 -globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 localCtrBits=2 -localHistoryBits=11 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 @@ -133,10 +138,10 @@ predType=tournament [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -147,12 +152,21 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 @@ -422,10 +436,10 @@ opLat=3 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -436,12 +450,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -454,10 +477,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -468,16 +491,24 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 system=system use_default_range=false @@ -496,7 +527,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -507,10 +538,14 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 system=system use_default_range=false @@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM activation_limit=4 -addr_mapping=openmap +addr_mapping=RaBaChCo banks_per_rank=8 +burst_length=8 channels=1 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 in_addr_map=true -lines_per_rowbuffer=32 mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 tBURST=5000 tCL=13750 tRCD=13750 @@ -544,6 +584,9 @@ tWTR=7500 tXAW=40000 write_buffer_size=32 write_thresh_perc=70 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 40a764ff6..6fa75b847 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 26 2013 14:38:52 -gem5 started Mar 26 2013 22:56:38 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 09:53:14 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1387,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 626014950000 because target called exit() +Exiting @ tick 631883288500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 98e511e60..d4071b647 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=AtomicSimpleCPU children=dtb interrupts isa itb tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -53,6 +58,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -88,7 +97,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -99,11 +108,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 76e77727d..0011f9cf8 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:44:11 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 09:53:14 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index be88a9856..d6223b426 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000 [system] type=System -children=cpu membus physmem +children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a -clock=1000 +cache_line_size=64 +clk_domain=system.clk_domain init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,12 +30,16 @@ work_end_exit_count=0 work_item_id=-1 system_port=system.membus.slave[0] +[system.clk_domain] +type=SrcClockDomain +clock=1000 +voltage_domain=system.voltage_domain + [system.cpu] type=TimingSimpleCPU children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null checker=Null -clock=500 +clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true @@ -52,6 +57,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.tracer @@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -75,22 +81,31 @@ prefetcher=Null response_latency=2 size=262144 system=system +tags=system.cpu.dcache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=262144 + [system.cpu.dtb] type=AlphaTLB size=64 [system.cpu.icache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=2 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=2 is_top_level=true @@ -101,12 +116,21 @@ prefetcher=Null response_latency=2 size=131072 system=system +tags=system.cpu.icache.tags tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=2 +size=131072 + [system.cpu.interrupts] type=AlphaInterrupts @@ -119,10 +143,10 @@ size=48 [system.cpu.l2cache] type=BaseCache +children=tags addr_ranges=0:18446744073709551615 assoc=8 -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain forward_snoops=true hit_latency=20 is_top_level=false @@ -133,17 +157,26 @@ prefetcher=Null response_latency=20 size=2097152 system=system +tags=system.cpu.l2cache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +hit_latency=20 +size=2097152 + [system.cpu.toL2Bus] type=CoherentBus -block_size=64 -clock=500 +clk_domain=system.cpu_clk_domain header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -160,7 +193,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -171,11 +204,16 @@ simpoint=0 system=system uid=100 +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +voltage_domain=system.voltage_domain + [system.membus] type=CoherentBus -block_size=64 -clock=1000 +clk_domain=system.clk_domain header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1000 -conf_table_reported=false +clk_domain=system.clk_domain +conf_table_reported=true in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 -zero=false port=system.membus.master[0] +[system.voltage_domain] +type=VoltageDomain +voltage=1.000000 + diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index c7b42c8e2..a19734d3d 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:29:25 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Sep 24 2013 03:08:53 +gem5 started Sep 28 2013 09:53:14 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... |