diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/40.perlbmk/ref/alpha/tru64 | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64')
4 files changed, 1767 insertions, 1765 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index ef1860117..cf6f894cc 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.190861 # Number of seconds simulated -sim_ticks 1190860634000 # Number of ticks simulated -final_tick 1190860634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.555548 # Number of seconds simulated +sim_ticks 555548307000 # Number of ticks simulated +final_tick 555548307000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304682 # Simulator instruction rate (inst/s) -host_op_rate 304682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180566626 # Simulator tick rate (ticks/s) -host_mem_usage 250024 # Number of bytes of host memory used -host_seconds 6595.13 # Real time elapsed on the host -sim_insts 2009421070 # Number of instructions simulated -sim_ops 2009421070 # Number of ops (including micro ops) simulated +host_inst_rate 201077 # Simulator instruction rate (inst/s) +host_op_rate 201077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120272803 # Simulator tick rate (ticks/s) +host_mem_usage 246132 # Number of bytes of host memory used +host_seconds 4619.07 # Real time elapsed on the host +sim_insts 928789150 # Number of instructions simulated +sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 30476096 # Number of bytes read from this memory -system.physmem.bytes_read::total 30476096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 476189 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25591656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25591656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 156875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3595813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3595813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3595813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25591656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29187469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476189 # Number of read requests accepted -system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476189 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30458432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30476096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 18657152 # Number of bytes read from this memory +system.physmem.bytes_read::total 18657152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 291518 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 33583312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33583312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 336043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 336043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7681982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7681982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7681982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33583312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41265294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291518 # Number of read requests accepted +system.physmem.writeReqs 66683 # Number of write requests accepted +system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18639168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17984 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 281 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29463 # Per bank write bursts -system.physmem.perBankRdBursts::1 29817 # Per bank write bursts -system.physmem.perBankRdBursts::2 29839 # Per bank write bursts -system.physmem.perBankRdBursts::3 29779 # Per bank write bursts -system.physmem.perBankRdBursts::4 29691 # Per bank write bursts -system.physmem.perBankRdBursts::5 29776 # Per bank write bursts -system.physmem.perBankRdBursts::6 29845 # Per bank write bursts -system.physmem.perBankRdBursts::7 29824 # Per bank write bursts -system.physmem.perBankRdBursts::8 29755 # Per bank write bursts -system.physmem.perBankRdBursts::9 29877 # Per bank write bursts -system.physmem.perBankRdBursts::10 29842 # Per bank write bursts -system.physmem.perBankRdBursts::11 29915 # Per bank write bursts -system.physmem.perBankRdBursts::12 29785 # Per bank write bursts -system.physmem.perBankRdBursts::13 29577 # Per bank write bursts -system.physmem.perBankRdBursts::14 29501 # Per bank write bursts -system.physmem.perBankRdBursts::15 29627 # Per bank write bursts +system.physmem.perBankRdBursts::0 17934 # Per bank write bursts +system.physmem.perBankRdBursts::1 18286 # Per bank write bursts +system.physmem.perBankRdBursts::2 18304 # Per bank write bursts +system.physmem.perBankRdBursts::3 18252 # Per bank write bursts +system.physmem.perBankRdBursts::4 18169 # Per bank write bursts +system.physmem.perBankRdBursts::5 18242 # Per bank write bursts +system.physmem.perBankRdBursts::6 18316 # Per bank write bursts +system.physmem.perBankRdBursts::7 18295 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18210 # Per bank write bursts +system.physmem.perBankRdBursts::11 18385 # Per bank write bursts +system.physmem.perBankRdBursts::12 18260 # Per bank write bursts +system.physmem.perBankRdBursts::13 18048 # Per bank write bursts +system.physmem.perBankRdBursts::14 17980 # Per bank write bursts +system.physmem.perBankRdBursts::15 18103 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -69,8 +69,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4222 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -78,23 +78,23 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1190860558500 # Total gap between requests +system.physmem.totGap 555548231500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476189 # Read request sizes (log2) +system.physmem.readPktSize::6 291518 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 475413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 290743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 468 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,110 +189,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 196024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 177.216831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 127.562877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.494740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 75216 38.37% 38.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 90843 46.34% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17447 8.90% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 798 0.41% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 682 0.35% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 656 0.33% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1172 0.60% 95.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1008 0.51% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8202 4.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 196024 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4056 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 115.321252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.815163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1129.679023 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.53% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 7 0.17% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 9 0.22% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-18431 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 104858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.415915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.780585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.040689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39691 37.85% 37.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43831 41.80% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8352 7.97% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1265 1.21% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 732 0.70% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 905 0.86% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1060 1.01% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 884 0.84% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8138 7.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104858 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.322621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.136998 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 770.555291 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4056 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4056 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3063 75.52% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 993 24.48% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4056 # Writes before turning the bus around for reads -system.physmem.totQLat 4642842500 # Total ticks spent queuing -system.physmem.totMemAccLat 13566211250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2379565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9755.65 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458537 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855483 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3076 76.04% 76.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 966 23.88% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads +system.physmem.totQLat 2434432250 # Total ticks spent queuing +system.physmem.totMemAccLat 7895126000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456185000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8358.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28505.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.59 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27108.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.32 # Data bus utilization in percentage +system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 296141 # Number of row buffer hits during reads -system.physmem.writeRowHits 50629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 2192721.67 # Average gap between requests -system.physmem.pageHitRate 63.88 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 589509971750 # Time in different power states -system.physmem.memoryStateTime::REF 39765440000 # Time in different power states +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 202612 # Number of row buffer hits during reads +system.physmem.writeRowHits 50417 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes +system.physmem.avgGap 1550939.92 # Average gap between requests +system.physmem.pageHitRate 70.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275426566250 # Time in different power states +system.physmem.memoryStateTime::REF 18550740000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 561585082000 # Time in different power states +system.physmem.memoryStateTime::ACT 261564123750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 29187469 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409320 # Transaction distribution -system.membus.trans_dist::ReadResp 409320 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66869 # Transaction distribution -system.membus.trans_dist::ReadExResp 66869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019286 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34758208 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34758208 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34758208 # Total data (bytes) +system.membus.throughput 41265294 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224874 # Transaction distribution +system.membus.trans_dist::ReadResp 224874 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66644 # Transaction distribution +system.membus.trans_dist::ReadExResp 66644 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22924864 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1283694000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4536921750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.reqLayer0.occupancy 954576500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2724054750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 271010035 # Number of BP lookups -system.cpu.branchPred.condPredicted 174815111 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26224729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 223743631 # Number of BTB lookups -system.cpu.branchPred.BTBHits 179636452 # Number of BTB hits +system.cpu.branchPred.lookups 125108663 # Number of BP lookups +system.cpu.branchPred.condPredicted 80505378 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103330872 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82874855 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.286733 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40316732 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 27614 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18690214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511123125 # DTB read hits -system.cpu.dtb.read_misses 428196 # DTB read misses +system.cpu.dtb.read_hits 237537573 # DTB read hits +system.cpu.dtb.read_misses 198412 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511551321 # DTB read accesses -system.cpu.dtb.write_hits 210802220 # DTB write hits -system.cpu.dtb.write_misses 15121 # DTB write misses +system.cpu.dtb.read_accesses 237735985 # DTB read accesses +system.cpu.dtb.write_hits 98305055 # DTB write hits +system.cpu.dtb.write_misses 7206 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210817341 # DTB write accesses -system.cpu.dtb.data_hits 721925345 # DTB hits -system.cpu.dtb.data_misses 443317 # DTB misses +system.cpu.dtb.write_accesses 98312261 # DTB write accesses +system.cpu.dtb.data_hits 335842628 # DTB hits +system.cpu.dtb.data_misses 205618 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722368662 # DTB accesses -system.cpu.itb.fetch_hits 682230205 # ITB hits +system.cpu.dtb.data_accesses 336048246 # DTB accesses +system.cpu.itb.fetch_hits 315070348 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 682230325 # ITB accesses +system.cpu.itb.fetch_accesses 315070468 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -305,71 +306,72 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 2381721268 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 1111096614 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2009421070 # Number of instructions committed -system.cpu.committedOps 2009421070 # Number of ops (including micro ops) committed -system.cpu.discardedOps 51480727 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 928789150 # Number of instructions committed +system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed +system.cpu.discardedOps 23870770 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.185277 # CPI: cycles per instruction -system.cpu.ipc 0.843684 # IPC: instructions per cycle -system.cpu.tickCycles 2275163827 # Number of cycles that the object actually ticked -system.cpu.idleCycles 106557441 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 20821 # number of replacements -system.cpu.icache.tags.tagsinuse 1689.662119 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 682207641 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 22563 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30235.679697 # Average number of references to valid blocks. +system.cpu.cpi 1.196285 # CPI: cycles per instruction +system.cpu.ipc 0.835921 # IPC: instructions per cycle +system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58548412 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 10608 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.445112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 315057997 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25510.768988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1689.662119 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825030 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825030 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.445112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1364482973 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1364482973 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 682207641 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 682207641 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 682207641 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 682207641 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 682207641 # number of overall hits -system.cpu.icache.overall_hits::total 682207641 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 22564 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 22564 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 22564 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 22564 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 22564 # number of overall misses -system.cpu.icache.overall_misses::total 22564 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 467220750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 467220750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 467220750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 467220750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 467220750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 467220750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 682230205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 682230205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 682230205 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 682230205 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 682230205 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 682230205 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20706.468268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20706.468268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20706.468268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20706.468268 # average overall miss latency +system.cpu.icache.tags.tag_accesses 630153046 # Number of tag accesses +system.cpu.icache.tags.data_accesses 630153046 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 315057997 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 315057997 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 315057997 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 315057997 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 315057997 # number of overall hits +system.cpu.icache.overall_hits::total 315057997 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses +system.cpu.icache.overall_misses::total 12351 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 334622500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 334622500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 334622500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 334622500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 334622500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 334622500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 315070348 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 315070348 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 315070348 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 315070348 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 315070348 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 315070348 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27092.745527 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27092.745527 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27092.745527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27092.745527 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,123 +380,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 22564 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 22564 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 22564 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 22564 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 22564 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 22564 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 420842250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 420842250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 420842250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 420842250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 420842250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 420842250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18651.048130 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18651.048130 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308669500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 308669500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308669500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 308669500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308669500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 308669500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24991.458182 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24991.458182 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 88620923 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1481078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1481077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71948 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45127 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156886 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3202013 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1444032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104091136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 105535168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 105535168 # Total data (bytes) +system.cpu.toL2Bus.throughput 101892158 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69010 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56606016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 920456000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 34470750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19151500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371437000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222065750 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72034.407592 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65906.488806 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65906.488806 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71173.894349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71173.894349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71173.894349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71173.894349 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 2866.071604 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1526366 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.558807 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694159033 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1530462 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 453.561757 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 828677250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.558807 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999648 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999648 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 776534 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.879870 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322859768 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 413.588727 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879870 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 948 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1393051346 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1393051346 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 483506411 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 483506411 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 210652622 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210652622 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 694159033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694159033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 694159033 # number of overall hits -system.cpu.dcache.overall_hits::total 694159033 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1459135 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1459135 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 142274 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 142274 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53504926250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 484965546 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 484965546 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 695760442 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 695760442 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 695760442 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 695760442 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000675 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000675 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002302 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002302 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002302 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002302 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30367.623626 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30367.623626 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64625.045686 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64625.045686 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33411.156207 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33411.156207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33411.156207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33411.156207 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 648198338 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648198338 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 224695721 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224695721 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 322859768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322859768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 322859768 # number of overall hits +system.cpu.dcache.overall_hits::total 322859768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 849086 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses +system.cpu.dcache.overall_misses::total 849086 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22864552750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22864552750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8987445000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8987445000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 31851997750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31851997750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 31851997750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31851997750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 225407654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225407654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 323708854 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323708854 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 323708854 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323708854 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32116.158051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.158051 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65528.606738 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65528.606738 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37513.276335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37513.276335 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,48 +614,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95962 # number of writebacks -system.cpu.dcache.writebacks::total 95962 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 621 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 621 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 70326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 70947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 70947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 70947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 70947 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1458514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 71948 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71948 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1530462 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1530462 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1530462 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1530462 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41263033500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41263033500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529893000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529893000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 45792926500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45792926500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 45792926500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45792926500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28291.146674 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28291.146674 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62960.652138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62960.652138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks +system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 313 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68143 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 68456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711620 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711620 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69010 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69010 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21363533750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21363533750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4424989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4424989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25788522750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25788522750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30020.985568 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.985568 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64120.982466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64120.982466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c36f62fc3..9bdd841ee 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.635929 # Number of seconds simulated -sim_ticks 635929494500 # Number of ticks simulated -final_tick 635929494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278171 # Number of seconds simulated +sim_ticks 278170874500 # Number of ticks simulated +final_tick 278170874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181383 # Simulator instruction rate (inst/s) -host_op_rate 181383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63271586 # Simulator tick rate (ticks/s) -host_mem_usage 229300 # Number of bytes of host memory used -host_seconds 10050.79 # Real time elapsed on the host -sim_insts 1823043370 # Number of instructions simulated -sim_ops 1823043370 # Number of ops (including micro ops) simulated +host_inst_rate 125961 # Simulator instruction rate (inst/s) +host_op_rate 125961 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41594749 # Simulator tick rate (ticks/s) +host_mem_usage 247184 # Number of bytes of host memory used +host_seconds 6687.64 # Real time elapsed on the host +sim_insts 842382029 # Number of instructions simulated +sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295616 # Number of bytes read from this memory -system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2761 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473369 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 277867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47639898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47917765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 277867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 277867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6733627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6733627 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6733627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 277867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47639898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54651392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476130 # Number of read requests accepted -system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476130 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30454144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30472320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 176000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18476352 # Number of bytes read from this memory +system.physmem.bytes_read::total 18652352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288693 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291443 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 632705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66420872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67053576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 632705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 632705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15342052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15342052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15342052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 632705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66420872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82395628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291443 # Number of read requests accepted +system.physmem.writeReqs 66683 # Number of write requests accepted +system.physmem.readBursts 291443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18634688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29443 # Per bank write bursts -system.physmem.perBankRdBursts::1 29787 # Per bank write bursts -system.physmem.perBankRdBursts::2 29841 # Per bank write bursts -system.physmem.perBankRdBursts::3 29778 # Per bank write bursts -system.physmem.perBankRdBursts::4 29678 # Per bank write bursts -system.physmem.perBankRdBursts::5 29749 # Per bank write bursts -system.physmem.perBankRdBursts::6 29855 # Per bank write bursts -system.physmem.perBankRdBursts::7 29842 # Per bank write bursts -system.physmem.perBankRdBursts::8 29764 # Per bank write bursts -system.physmem.perBankRdBursts::9 29879 # Per bank write bursts -system.physmem.perBankRdBursts::10 29841 # Per bank write bursts -system.physmem.perBankRdBursts::11 29912 # Per bank write bursts -system.physmem.perBankRdBursts::12 29773 # Per bank write bursts -system.physmem.perBankRdBursts::13 29578 # Per bank write bursts -system.physmem.perBankRdBursts::14 29495 # Per bank write bursts -system.physmem.perBankRdBursts::15 29631 # Per bank write bursts +system.physmem.perBankRdBursts::0 17914 # Per bank write bursts +system.physmem.perBankRdBursts::1 18261 # Per bank write bursts +system.physmem.perBankRdBursts::2 18310 # Per bank write bursts +system.physmem.perBankRdBursts::3 18245 # Per bank write bursts +system.physmem.perBankRdBursts::4 18158 # Per bank write bursts +system.physmem.perBankRdBursts::5 18234 # Per bank write bursts +system.physmem.perBankRdBursts::6 18318 # Per bank write bursts +system.physmem.perBankRdBursts::7 18307 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::10 18215 # Per bank write bursts +system.physmem.perBankRdBursts::11 18386 # Per bank write bursts +system.physmem.perBankRdBursts::12 18247 # Per bank write bursts +system.physmem.perBankRdBursts::13 18053 # Per bank write bursts +system.physmem.perBankRdBursts::14 17967 # Per bank write bursts +system.physmem.perBankRdBursts::15 18100 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4230 # Per bank write bursts +system.physmem.perBankWrBursts::9 4179 # Per bank write bursts +system.physmem.perBankWrBursts::10 4147 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 635929412000 # Total gap between requests +system.physmem.totGap 278170791500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476130 # Read request sizes (log2) +system.physmem.readPktSize::6 291443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 214189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,112 +193,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 185909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 186.826200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.409449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 215.527814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 65070 35.00% 35.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 87777 47.22% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 21119 11.36% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 448 0.24% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 430 0.23% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 462 0.25% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 533 0.29% 94.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 575 0.31% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9495 5.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 185909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 100147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 228.644373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.919705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.922323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35701 35.65% 35.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41944 41.88% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10332 10.32% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 643 0.64% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 550 0.55% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 478 0.48% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 606 0.61% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1154 1.15% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8739 8.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100147 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 117.004698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.982691 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1132.774880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4024 99.51% 99.51% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 3 0.07% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 15 0.37% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.435955 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.134261 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 746.811219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.540554 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.517518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.888872 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2948 72.90% 72.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.27% 73.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1080 26.71% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.481701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.460271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.857904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3073 75.99% 75.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 23.86% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 4824243250 # Total ticks spent queuing -system.physmem.totMemAccLat 13746355750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2379230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10138.24 # Average queueing delay per DRAM burst +system.physmem.totQLat 3337058000 # Total ticks spent queuing +system.physmem.totMemAccLat 8796439250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11460.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28888.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30210.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.33 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 306274 # Number of row buffer hits during reads -system.physmem.writeRowHits 50544 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes -system.physmem.avgGap 1171058.77 # Average gap between requests -system.physmem.pageHitRate 65.74 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 176454220250 # Time in different power states -system.physmem.memoryStateTime::REF 21234980000 # Time in different power states +system.physmem.busUtil 0.64 # Data bus utilization in percentage +system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 207319 # Number of row buffer hits during reads +system.physmem.writeRowHits 50340 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.49 # Row buffer hit rate for writes +system.physmem.avgGap 776740.01 # Average gap between requests +system.physmem.pageHitRate 72.00 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 73797472500 # Time in different power states +system.physmem.memoryStateTime::REF 9288500000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 438237480500 # Time in different power states +system.physmem.memoryStateTime::ACT 195078106500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54651392 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409276 # Transaction distribution -system.membus.trans_dist::ReadResp 409276 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66854 # Transaction distribution -system.membus.trans_dist::ReadExResp 66854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019168 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34754432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34754432 # Total data (bytes) +system.membus.throughput 82395628 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224814 # Transaction distribution +system.membus.trans_dist::ReadResp 224814 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66629 # Transaction distribution +system.membus.trans_dist::ReadExResp 66629 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649569 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22920064 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22920064 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1134499000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4452935500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 964230000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2710224500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 402497188 # Number of BP lookups -system.cpu.branchPred.condPredicted 262794086 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25809520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 329924346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 269779526 # Number of BTB hits +system.cpu.branchPred.lookups 192451615 # Number of BP lookups +system.cpu.branchPred.condPredicted 125635967 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11884604 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155866017 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126935891 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.770118 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 58338435 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6772 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.439106 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28844958 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522325129 # DTB read hits -system.cpu.dtb.read_misses 599769 # DTB read misses +system.cpu.dtb.read_hits 244501349 # DTB read hits +system.cpu.dtb.read_misses 309633 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522924898 # DTB read accesses -system.cpu.dtb.write_hits 290323928 # DTB write hits -system.cpu.dtb.write_misses 50170 # DTB write misses +system.cpu.dtb.read_accesses 244810982 # DTB read accesses +system.cpu.dtb.write_hits 135678395 # DTB write hits +system.cpu.dtb.write_misses 31433 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 290374098 # DTB write accesses -system.cpu.dtb.data_hits 812649057 # DTB hits -system.cpu.dtb.data_misses 649939 # DTB misses +system.cpu.dtb.write_accesses 135709828 # DTB write accesses +system.cpu.dtb.data_hits 380179744 # DTB hits +system.cpu.dtb.data_misses 341066 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 813298996 # DTB accesses -system.cpu.itb.fetch_hits 408884134 # ITB hits -system.cpu.itb.fetch_misses 679 # ITB misses +system.cpu.dtb.data_accesses 380520810 # DTB accesses +system.cpu.itb.fetch_hits 196843274 # ITB hits +system.cpu.itb.fetch_misses 340 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 408884813 # ITB accesses +system.cpu.itb.fetch_accesses 196843614 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,507 +310,508 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1271858990 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 556341750 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 427176335 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3374139678 # Number of instructions fetch has processed -system.cpu.fetch.Branches 402497188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 328117961 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 650903682 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 174116050 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 24391105 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7638 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 408884134 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8158289 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1250296288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.698672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.147490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202596472 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648022555 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192451615 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155780849 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341400338 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24237220 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 65 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6944 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 196843274 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6474022 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556122593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176362 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 599392606 47.94% 47.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 59914511 4.79% 52.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43339464 3.47% 56.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 76172685 6.09% 62.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 135820925 10.86% 73.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46245373 3.70% 76.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41570756 3.32% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7626661 0.61% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 240213307 19.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 237070993 42.63% 42.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30141188 5.42% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22117288 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36437929 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67906358 12.21% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21586506 3.88% 74.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299171 3.47% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3525264 0.63% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118037896 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1250296288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.652920 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437590524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 25041136 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 638845250 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1014076 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 147805302 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33122555 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12366 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3318032791 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46593 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 147805302 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 458553010 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7909851 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 618894367 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 17106362 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3208538957 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6484 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17594215 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 887362 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2130246681 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3706452753 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3620701555 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85751197 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 745277611 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4240 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12056800 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 776684532 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 361655801 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 80427234 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13113632 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2720222433 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 90 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2182396478 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17917271 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 897142134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 813907304 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 51 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1250296288 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.745503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.834496 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 556122593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345923 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962249 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168349447 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89068138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273848076 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12745104 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12111828 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15365676 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7037 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1585434415 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25396 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12111828 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176490492 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 62059786 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14189 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278431125 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27015173 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538086365 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7791 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2366498 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17905765 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6836076 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1026692475 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1767991158 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728209753 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39781404 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 387725317 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1423 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9582425 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372570647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175396988 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40822996 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11172222 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1305164678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1015585029 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462756562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 428157425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 86 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 556122593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.898849 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 456063276 36.48% 36.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196937863 15.75% 52.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 246215948 19.69% 71.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118632312 9.49% 81.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96039549 7.68% 89.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 85322198 6.82% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 31637786 2.53% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19044967 1.52% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 402389 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 196378723 35.31% 35.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93218493 16.76% 52.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 92101634 16.56% 68.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 60001110 10.79% 79.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56881652 10.23% 89.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29459866 5.30% 94.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17057995 3.07% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7198930 1.29% 99.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3824190 0.69% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1250296288 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556122593 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1147020 2.84% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25333961 62.75% 65.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 13891524 34.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464498 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15571985 66.15% 76.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5503822 23.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1250439249 57.30% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17094 0.00% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851471 1.28% 58.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 592678275 27.16% 86.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 295948284 13.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579410115 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7864 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181855 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276884212 27.26% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138933358 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2182396478 # Type of FU issued -system.cpu.iq.rate 1.715911 # Inst issue rate -system.cpu.iq.fu_busy_cnt 40372505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018499 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5521594502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3528574475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2004997019 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151784518 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88865161 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73949462 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2144972289 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77793942 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63261686 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015585029 # Type of FU issued +system.cpu.iq.rate 1.825470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23540305 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023179 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548815722 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1726656461 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 939949010 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808195 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41310105 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425215 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002762123 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36361935 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50443717 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 265614506 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19945 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 77572 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 150860905 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 135060050 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1143240 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45700 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77095788 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4433 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3083 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2279 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4366 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 147805302 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7602167 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 279549 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3087695808 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 56386 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 776684532 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 361655801 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 90 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 141634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 84137 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 77572 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25803318 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 28659 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25831977 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2081430874 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522925034 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100965604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12111828 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 61105954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191244 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479623370 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16690 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372570647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175396988 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 26783 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 176241 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45700 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11878414 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16350 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11894764 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976099064 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244811165 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39485965 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 367473285 # number of nop insts executed -system.cpu.iew.exec_refs 813299641 # number of memory reference insts executed -system.cpu.iew.exec_branches 277669733 # Number of branches executed -system.cpu.iew.exec_stores 290374607 # Number of stores executed -system.cpu.iew.exec_rate 1.636526 # Inst execution rate -system.cpu.iew.wb_sent 2081298559 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2078946481 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1190563677 # num instructions producing a value -system.cpu.iew.wb_consumers 1779120207 # num instructions consuming a value +system.cpu.iew.exec_nop 174458569 # number of nop insts executed +system.cpu.iew.exec_refs 380521398 # number of memory reference insts executed +system.cpu.iew.exec_branches 129090215 # Number of branches executed +system.cpu.iew.exec_stores 135710233 # Number of stores executed +system.cpu.iew.exec_rate 1.754495 # Inst execution rate +system.cpu.iew.wb_sent 974894086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974374225 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556362190 # num instructions producing a value +system.cpu.iew.wb_consumers 832682807 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.634573 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.669187 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751395 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668156 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1061256381 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25797472 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1102490986 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.822226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.529076 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 543793882 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 11877823 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483108609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.922109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.601347 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 487378417 44.21% 44.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227745323 20.66% 64.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 117618714 10.67% 75.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58023945 5.26% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49786654 4.52% 85.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22711490 2.06% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18023785 1.63% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18535022 1.68% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102667636 9.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205236337 42.48% 42.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102049514 21.12% 63.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51661331 10.69% 74.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25803847 5.34% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21528421 4.46% 84.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9152086 1.89% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10413942 2.16% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6658903 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50604228 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1102490986 # Number of insts commited each cycle -system.cpu.commit.committedInsts 2008987604 # Number of instructions committed -system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 483108609 # Number of insts commited each cycle +system.cpu.commit.committedInsts 928587628 # Number of instructions committed +system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 721864922 # Number of memory references committed -system.cpu.commit.loads 511070026 # Number of loads committed +system.cpu.commit.refs 335811797 # Number of memory references committed +system.cpu.commit.loads 237510597 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 266706457 # Number of branches committed -system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. -system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 185946986 9.26% 9.26% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1058512436 52.69% 61.94% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 15158 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 27517120 1.37% 63.32% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 8254514 0.41% 63.73% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 6876464 0.34% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 4 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.07% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 511070026 25.44% 89.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 210794896 10.49% 100.00% # Class of committed instruction +system.cpu.commit.branches 123111018 # Number of branches committed +system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. +system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. +system.cpu.commit.function_calls 18524163 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 2008987604 # Class of committed instruction -system.cpu.commit.bw_lim_events 102667636 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction +system.cpu.commit.bw_lim_events 50604228 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4064430925 # The number of ROB reads -system.cpu.rob.rob_writes 6288295371 # The number of ROB writes -system.cpu.timesIdled 345316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21562702 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1823043370 # Number of Instructions Simulated -system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.697657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.697657 # CPI: Total CPI of All Threads -system.cpu.ipc 1.433369 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.433369 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2650222630 # number of integer regfile reads -system.cpu.int_regfile_writes 1504597172 # number of integer regfile writes -system.cpu.fp_regfile_reads 79149378 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661639 # number of floating regfile writes +system.cpu.rob.rob_reads 1902264753 # The number of ROB reads +system.cpu.rob.rob_writes 3017778261 # The number of ROB writes +system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 219157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 842382029 # Number of Instructions Simulated +system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.660439 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660439 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237156032 # number of integer regfile reads +system.cpu.int_regfile_writes 705771856 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691388 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411317 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 164848262 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470375 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470374 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71643 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159913 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3180016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104188608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104831872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104831872 # Total data (bytes) +system.cpu.toL2Bus.throughput 202299828 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 718925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68836 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12807 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1667041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55864128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56273920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56273920 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914980500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15576999 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 531160500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10099250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2360120750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1208088500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8337 # number of replacements -system.cpu.icache.tags.tagsinuse 1659.365799 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 408871331 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 40679.666799 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4693 # number of replacements +system.cpu.icache.tags.tagsinuse 1650.457565 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 196834917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6403 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30741.045916 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1659.365799 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.810237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.810237 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1714 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1650.457565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.805887 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.805887 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1710 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836914 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 817778319 # Number of tag accesses -system.cpu.icache.tags.data_accesses 817778319 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 408871331 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 408871331 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 408871331 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 408871331 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 408871331 # number of overall hits -system.cpu.icache.overall_hits::total 408871331 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12803 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12803 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12803 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12803 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12803 # number of overall misses -system.cpu.icache.overall_misses::total 12803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 381292998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 381292998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 381292998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 381292998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 381292998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 381292998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 408884134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 408884134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 408884134 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 408884134 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 408884134 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 408884134 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000031 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000031 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29781.535421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29781.535421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29781.535421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29781.535421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29781.535421 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834961 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 393692951 # Number of tag accesses +system.cpu.icache.tags.data_accesses 393692951 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 196834917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 196834917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 196834917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 196834917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 196834917 # number of overall hits +system.cpu.icache.overall_hits::total 196834917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8357 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8357 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8357 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8357 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8357 # number of overall misses +system.cpu.icache.overall_misses::total 8357 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329567249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329567249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329567249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329567249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329567249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329567249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 196843274 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 196843274 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 196843274 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 196843274 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 196843274 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 196843274 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39436.071437 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39436.071437 # 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number of overall hits +system.cpu.dcache.overall_hits::total 289853230 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1579063 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1579063 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 920263 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 920263 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2499326 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2499326 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2499326 # number of overall misses +system.cpu.dcache.overall_misses::total 2499326 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79789190750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79789190750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377622714 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57377622714 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137166813464 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137166813464 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137166813464 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137166813464 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194051356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194051356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 19 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292352556 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292352556 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292352556 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292352556 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008137 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008137 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009362 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009362 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008549 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008549 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008549 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008549 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50529.453701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50529.453701 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62349.157484 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62349.157484 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54881.521444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54881.521444 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 55443 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 471 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.690021 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107.447674 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95981 # number of writebacks -system.cpu.dcache.writebacks::total 95981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467493 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467493 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 989127 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 989127 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1456620 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1456620 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1456620 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1456620 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460323 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460323 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531966 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531966 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531966 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531966 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40901282750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40901282750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5350796500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5350796500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46252079250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46252079250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46252079250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46252079250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002287 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002287 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002287 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28008.380851 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28008.380851 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74686.940804 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74686.940804 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30191.322294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30191.322294 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91520 # number of writebacks +system.cpu.dcache.writebacks::total 91520 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 866542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851427 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 851427 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1717969 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1717969 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1717969 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1717969 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712521 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712521 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68836 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68836 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781357 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781357 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781357 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781357 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21863154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21863154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5224164248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5224164248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27087318248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27087318248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27087318248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27087318248 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002673 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30684.224044 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30684.224044 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75892.908478 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75892.908478 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 6bfc9d3ce..2d72b8ec8 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.004711 # Number of seconds simulated -sim_ticks 1004710587000 # Number of ticks simulated -final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.464395 # Number of seconds simulated +sim_ticks 464394627000 # Number of ticks simulated +final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2670371 # Simulator instruction rate (inst/s) -host_op_rate 2670371 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1335473702 # Simulator tick rate (ticks/s) -host_mem_usage 265688 # Number of bytes of host memory used -host_seconds 752.33 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -sim_ops 2008987605 # Number of ops (including micro ops) simulated +host_inst_rate 1843860 # Simulator instruction rate (inst/s) +host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 922130037 # Simulator tick rate (ticks/s) +host_mem_usage 234352 # Number of bytes of host memory used +host_seconds 503.61 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory -system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8037684280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1586125963 # Number of bytes written to this memory -system.physmem.bytes_written::total 1586125963 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2009421070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 511070026 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2520491096 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 210794896 # Number of write requests responded to by this memory -system.physmem.num_writes::total 210794896 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3552681501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11552681087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1578689409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13131370496 # Throughput (bytes/s) -system.membus.data_through_bus 13193226959 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory +system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory +system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13156831461 # Throughput (bytes/s) +system.membus.data_through_bus 6109961839 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.data_hits 721864922 # DTB hits -system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722298387 # DTB accesses -system.cpu.itb.fetch_hits 2009421070 # ITB hits +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789150 # ITB hits system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2009421175 # ITB accesses +system.cpu.itb.fetch_accesses 928789255 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -71,64 +71,64 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 2009421175 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 928789255 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2008987605 # Number of instructions committed -system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses -system.cpu.num_func_calls 79910682 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls -system.cpu.num_int_insts 1779374816 # number of integer instructions -system.cpu.num_fp_insts 71831671 # number of float instructions -system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read -system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written -system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read -system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written -system.cpu.num_mem_refs 722298387 # number of memory refs -system.cpu.num_load_insts 511488910 # Number of load instructions -system.cpu.num_store_insts 210809477 # Number of store instructions +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2009421175 # Number of busy cycles +system.cpu.num_busy_cycles 928789255 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 266706457 # Number of branches fetched -system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction -system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction -system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction -system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction -system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2009421070 # Class of executed instruction +system.cpu.op_class::total 928789150 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index ef8e8a3ca..9f0d0f3c5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.769740 # Number of seconds simulated -sim_ticks 2769739533000 # Number of ticks simulated -final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.286250 # Number of seconds simulated +sim_ticks 1286249820000 # Number of ticks simulated +final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1094265 # Simulator instruction rate (inst/s) -host_op_rate 1094265 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1508635104 # Simulator tick rate (ticks/s) -host_mem_usage 274392 # Number of bytes of host memory used -host_seconds 1835.92 # Real time elapsed on the host -sim_insts 2008987605 # Number of instructions simulated -sim_ops 2008987605 # Number of ops (including micro ops) simulated +host_inst_rate 839019 # Simulator instruction rate (inst/s) +host_op_rate 839019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162182391 # Simulator tick rate (ticks/s) +host_mem_usage 244120 # Number of bytes of host memory used +host_seconds 1106.75 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory -system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory +system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory -system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12529860 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408476 # Transaction distribution -system.membus.trans_dist::ReadResp 408476 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66873 # Transaction distribution -system.membus.trans_dist::ReadExResp 66873 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1017606 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1017606 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34704448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34704448 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34704448 # Total data (bytes) +system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 17781280 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22871168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 511070026 # DTB read hits -system.cpu.dtb.read_misses 418884 # DTB read misses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 511488910 # DTB read accesses -system.cpu.dtb.write_hits 210794896 # DTB write hits -system.cpu.dtb.write_misses 14581 # DTB write misses +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 210809477 # DTB write accesses -system.cpu.dtb.data_hits 721864922 # DTB hits -system.cpu.dtb.data_misses 433465 # DTB misses +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 722298387 # DTB accesses -system.cpu.itb.fetch_hits 2009421071 # ITB hits +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789151 # ITB hits system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2009421176 # ITB accesses +system.cpu.itb.fetch_accesses 928789256 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -85,118 +85,118 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5539479066 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 2572499640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2008987605 # Number of instructions committed -system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses -system.cpu.num_func_calls 79910682 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls -system.cpu.num_int_insts 1779374816 # number of integer instructions -system.cpu.num_fp_insts 71831671 # number of float instructions -system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read -system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written -system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read -system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written -system.cpu.num_mem_refs 722298387 # number of memory refs -system.cpu.num_load_insts 511488910 # Number of load instructions -system.cpu.num_store_insts 210809477 # Number of store instructions +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5539479066 # Number of busy cycles +system.cpu.num_busy_cycles 2572499640 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 266706457 # Number of branches fetched -system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction -system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction -system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction -system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction -system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction -system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction -system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction -system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2009421070 # Class of executed instruction -system.cpu.icache.tags.replacements 9046 # number of replacements -system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks. +system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.icache.tags.replacements 4618 # number of replacements +system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4018852738 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4018852738 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits -system.cpu.icache.overall_hits::total 2009410475 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10596 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses -system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2009421071 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits +system.cpu.icache.overall_hits::total 928782983 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses +system.cpu.icache.overall_misses::total 6168 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,123 +205,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10596 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # 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average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442570 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257900 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32732 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31199 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998901 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13642206 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13642206 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96129 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96129 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 5079 # 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miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits +system.cpu.dcache.overall_hits::total 335031269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses +system.cpu.dcache.overall_misses::total 780528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,60 +451,60 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks -system.cpu.dcache.writebacks::total 96129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks +system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 678144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104081472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104759616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes) +system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |