diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long/se/40.perlbmk/ref/alpha/tru64 | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 1548 |
1 files changed, 747 insertions, 801 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 130b22828..55140cd28 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631518 # Number of seconds simulated -sim_ticks 631518097500 # Number of ticks simulated -final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629599 # Number of seconds simulated +sim_ticks 629599373500 # Number of ticks simulated +final_tick 629599373500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171044 # Simulator instruction rate (inst/s) -host_op_rate 171044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59250964 # Simulator tick rate (ticks/s) -host_mem_usage 240608 # Number of bytes of host memory used -host_seconds 10658.36 # Real time elapsed on the host +host_inst_rate 142688 # Simulator instruction rate (inst/s) +host_op_rate 142688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49278187 # Simulator tick rate (ticks/s) +host_mem_usage 277460 # Number of bytes of host memory used +host_seconds 12776.43 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295488 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176128 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory +system.physmem.bytes_read::total 30472704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176768 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473367 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476136 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 278896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47972478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48251374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 278896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 278896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6780664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6780664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6780664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 278896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47972478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55032038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476119 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 280763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48119387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48400150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280763 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280763 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6801328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6801328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6801328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48119387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55201478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476136 # Number of read requests accepted system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476119 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 476136 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30465984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue -system.physmem.bytesWritten 4281664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30471616 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30452800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4280256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30472704 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29449 # Per bank write bursts -system.physmem.perBankRdBursts::1 29798 # Per bank write bursts -system.physmem.perBankRdBursts::2 29850 # Per bank write bursts -system.physmem.perBankRdBursts::3 29793 # Per bank write bursts -system.physmem.perBankRdBursts::4 29695 # Per bank write bursts -system.physmem.perBankRdBursts::5 29771 # Per bank write bursts -system.physmem.perBankRdBursts::6 29867 # Per bank write bursts -system.physmem.perBankRdBursts::7 29856 # Per bank write bursts -system.physmem.perBankRdBursts::8 29771 # Per bank write bursts -system.physmem.perBankRdBursts::9 29894 # Per bank write bursts -system.physmem.perBankRdBursts::10 29844 # Per bank write bursts -system.physmem.perBankRdBursts::11 29915 # Per bank write bursts -system.physmem.perBankRdBursts::12 29793 # Per bank write bursts -system.physmem.perBankRdBursts::13 29587 # Per bank write bursts -system.physmem.perBankRdBursts::14 29511 # Per bank write bursts -system.physmem.perBankRdBursts::15 29637 # Per bank write bursts +system.physmem.perBankRdBursts::0 29443 # Per bank write bursts +system.physmem.perBankRdBursts::1 29785 # Per bank write bursts +system.physmem.perBankRdBursts::2 29834 # Per bank write bursts +system.physmem.perBankRdBursts::3 29781 # Per bank write bursts +system.physmem.perBankRdBursts::4 29679 # Per bank write bursts +system.physmem.perBankRdBursts::5 29744 # Per bank write bursts +system.physmem.perBankRdBursts::6 29853 # Per bank write bursts +system.physmem.perBankRdBursts::7 29847 # Per bank write bursts +system.physmem.perBankRdBursts::8 29759 # Per bank write bursts +system.physmem.perBankRdBursts::9 29871 # Per bank write bursts +system.physmem.perBankRdBursts::10 29836 # Per bank write bursts +system.physmem.perBankRdBursts::11 29910 # Per bank write bursts +system.physmem.perBankRdBursts::12 29783 # Per bank write bursts +system.physmem.perBankRdBursts::13 29571 # Per bank write bursts +system.physmem.perBankRdBursts::14 29499 # Per bank write bursts +system.physmem.perBankRdBursts::15 29630 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6 4262 # Pe system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4241 # Per bank write bursts +system.physmem.perBankWrBursts::10 4219 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 631518039500 # Total gap between requests +system.physmem.totGap 629599315500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476119 # Read request sizes (log2) +system.physmem.readPktSize::6 476136 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,223 +129,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 182335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 190.554573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 126.681752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 408.631079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 68422 37.53% 37.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 48844 26.79% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 37964 20.82% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20159 11.06% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 264 0.14% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 246 0.13% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 141 0.08% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 184 0.10% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 113 0.06% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 137 0.08% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 96 0.05% 96.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 186 0.10% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 81 0.04% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 159 0.09% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 151 0.08% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 133 0.07% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 108 0.06% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 148 0.08% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 143 0.08% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 80 0.04% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 131 0.07% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 1760 0.97% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 1531 0.84% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 10 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 19 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 18 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 8 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 14 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 14 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 13 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 14 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 6 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 10 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 10 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 20 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 12 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 11 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 18 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 13 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 17 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 12 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 11 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 14 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 18 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 12 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 10 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 14 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 17 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 14 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 13 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 12 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 9 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 8 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 11 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 18 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 9 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 16 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 12 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 17 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 14 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 15 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 5 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 16 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 14 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 17 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 13 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 15 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 11 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 18 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 12 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 8 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 9 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 12 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 6 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 11 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 15 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 12 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 12 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 11 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 16 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 12 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 11 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 13 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 16 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 12 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 12 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 17 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 11 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 22 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 11 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 8 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 12 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 26 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 26 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336 39 0.02% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400 37 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464 7 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528 7 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592 6 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656 3 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720 7 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation -system.physmem.totQLat 2888040000 # Total ticks spent queuing -system.physmem.totMemAccLat 14116017500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks -system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18586.65 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 530.927244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.070424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 451.227629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7470 34.53% 34.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2793 12.91% 47.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 292 1.35% 48.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 662 3.06% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 618 2.86% 54.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 184 0.85% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 105 0.49% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 0.31% 56.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9443 43.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21634 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 114.953218 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.941709 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1121.982719 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4021 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.55% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 11 0.27% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4040 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554208 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.524474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.020237 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3080 76.24% 76.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 645 15.97% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 312 7.72% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4040 # Writes before turning the bus around for reads +system.physmem.totQLat 3865744500 # Total ticks spent queuing +system.physmem.totMemAccLat 15098494500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2379125000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8853625000 # Total ticks spent accessing banks +system.physmem.avgQLat 8124.30 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18606.89 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29653.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31731.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.28 # Average write queue length when enqueuing -system.physmem.readRowHits 310714 # Number of row buffer hits during reads -system.physmem.writeRowHits 49883 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes -system.physmem.avgGap 1162958.82 # Average gap between requests -system.physmem.pageHitRate 66.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 25.73 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 55031937 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409266 # Transaction distribution -system.membus.trans_dist::ReadResp 409265 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 304858 # Number of row buffer hits during reads +system.physmem.writeRowHits 50638 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes +system.physmem.avgGap 1159389.14 # Average gap between requests +system.physmem.pageHitRate 65.50 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 25.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55201376 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409283 # Transaction distribution +system.membus.trans_dist::ReadResp 409282 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution system.membus.trans_dist::ReadExReq 66853 # Transaction distribution system.membus.trans_dist::ReadExResp 66853 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019145 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019145 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34753664 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019179 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754752 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34754752 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34754752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1230652000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1216217500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4488013500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4476344750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 388926557 # Number of BP lookups -system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25808786 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 317451636 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258383726 # Number of BTB hits +system.cpu.branchPred.lookups 388794194 # Number of BP lookups +system.cpu.branchPred.condPredicted 256437181 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25515612 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 316966671 # Number of BTB lookups +system.cpu.branchPred.BTBHits 257889505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.393100 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57269217 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6785 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.361710 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 56977055 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6765 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522276153 # DTB read hits -system.cpu.dtb.read_misses 591029 # DTB read misses +system.cpu.dtb.read_hits 520530320 # DTB read hits +system.cpu.dtb.read_misses 596868 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522867182 # DTB read accesses -system.cpu.dtb.write_hits 283024283 # DTB write hits -system.cpu.dtb.write_misses 50282 # DTB write misses +system.cpu.dtb.read_accesses 521127188 # DTB read accesses +system.cpu.dtb.write_hits 282735636 # DTB write hits +system.cpu.dtb.write_misses 50248 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283074565 # DTB write accesses -system.cpu.dtb.data_hits 805300436 # DTB hits -system.cpu.dtb.data_misses 641311 # DTB misses +system.cpu.dtb.write_accesses 282785884 # DTB write accesses +system.cpu.dtb.data_hits 803265956 # DTB hits +system.cpu.dtb.data_misses 647116 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805941747 # DTB accesses -system.cpu.itb.fetch_hits 394923336 # ITB hits -system.cpu.itb.fetch_misses 673 # ITB misses +system.cpu.dtb.data_accesses 803913072 # DTB accesses +system.cpu.itb.fetch_hits 392575649 # ITB hits +system.cpu.itb.fetch_misses 637 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394924009 # ITB accesses +system.cpu.itb.fetch_accesses 392576286 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -359,238 +311,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1263036196 # number of cpu cycles simulated +system.cpu.numCycles 1259198748 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410109214 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3275361918 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157942220 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394923336 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11250823 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1248398019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 407695740 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3264617465 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388794194 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 314866560 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 628012855 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 156754099 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 76226521 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6801 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 392575649 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11023705 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1242691149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.627055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.139887 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 618119324 49.51% 49.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41223036 3.30% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233409831 18.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614678294 49.46% 49.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57194010 4.60% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43037577 3.46% 57.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71548664 5.76% 63.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128942698 10.38% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45555972 3.67% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41222741 3.32% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8274333 0.67% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232236860 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1248398019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438388192 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62722156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131631453 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131631453 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467678494 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27888696 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3095577926 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2054701913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3579840200 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3494452830 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1242691149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308763 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.592615 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 436055809 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62292865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 604244409 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9361042 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 130737024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31725769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12419 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3186787270 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46304 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 130737024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 465340122 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27154826 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 583972819 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35459361 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3088232608 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15483 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 29158265 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2049406757 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3572462908 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3487065334 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85397573 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669732843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 743928173 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2623617019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160251371 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 800506398 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1248398019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 664437687 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 110031896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 740965992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 350476523 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68460641 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8808840 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2617422170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2156741664 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17943359 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 794308745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 722892982 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1242691149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.735541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803084 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 451794387 36.19% 36.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196881068 15.77% 51.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120660419 9.67% 81.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104720933 8.39% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79314003 6.35% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 447799861 36.03% 36.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 195733301 15.75% 51.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 250780419 20.18% 71.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120973704 9.73% 81.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 105324665 8.48% 90.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 78133504 6.29% 96.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24822476 2.00% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17360375 1.40% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1762844 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1248398019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1242691149 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25664248 69.68% 72.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146236 3.14% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25360136 69.42% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10022546 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234386709 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1232941102 57.17% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17091 0.00% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851332 1.29% 58.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204650 0.33% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587650943 27.25% 86.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 292819094 13.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160251371 # Type of FU issued -system.cpu.iq.rate 1.710364 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5472576321 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3336085108 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990052081 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2119632115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2156741664 # Type of FU issued +system.cpu.iq.rate 1.712789 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36528918 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5459545573 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3323652243 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1987168817 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88152162 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609871 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2115818130 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449700 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62140575 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 232858147 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12904 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76517 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140575675 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229895966 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17367 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75928 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 139681627 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2851 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131631453 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987064964 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 734565 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 134613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 130737024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13158740 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 531547 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2980853453 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 734148 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 740965992 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 350476523 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 133073 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1496 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76517 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25801220 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 30372 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94121183 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 75928 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25509079 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 28871 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25537950 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2062960594 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 521127327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93781070 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363447857 # number of nop insts executed -system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed -system.cpu.iew.exec_branches 277625839 # Number of branches executed -system.cpu.iew.exec_stores 283075035 # Number of stores executed -system.cpu.iew.exec_rate 1.635844 # Inst execution rate -system.cpu.iew.wb_sent 2066015513 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063661877 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180966911 # num instructions producing a value -system.cpu.iew.wb_consumers 1753315239 # num instructions consuming a value +system.cpu.iew.exec_nop 363431191 # number of nop insts executed +system.cpu.iew.exec_refs 803913709 # number of memory reference insts executed +system.cpu.iew.exec_branches 277349504 # Number of branches executed +system.cpu.iew.exec_stores 282786382 # Number of stores executed +system.cpu.iew.exec_rate 1.638312 # Inst execution rate +system.cpu.iew.wb_sent 2062843616 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2060778688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180081311 # num instructions producing a value +system.cpu.iew.wb_consumers 1751769057 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back +system.cpu.iew.wb_rate 1.636579 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673651 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961121274 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 954910834 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1116766566 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25503576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1111954125 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.806718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513025 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 497624741 44.56% 44.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228755331 20.48% 65.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119853188 10.73% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19140455 1.71% 89.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16628477 1.49% 90.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 493953799 44.42% 44.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227598258 20.47% 64.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120157352 10.81% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 59117436 5.32% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49692095 4.47% 85.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24169379 2.17% 87.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18838880 1.69% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16341629 1.47% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102085297 9.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1116766566 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1111954125 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,229 +553,229 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102085297 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3980018812 # The number of ROB reads -system.cpu.rob.rob_writes 6071851301 # The number of ROB writes -system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14638177 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3968130856 # The number of ROB reads +system.cpu.rob.rob_writes 6058536012 # The number of ROB writes +system.cpu.timesIdled 350219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16507599 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.692817 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692817 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads -system.cpu.int_regfile_writes 1496658985 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes +system.cpu.cpi 0.690712 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690712 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447780 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447780 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2624503768 # number of integer regfile reads +system.cpu.int_regfile_writes 1494046892 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811207 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661075 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 165988542 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470277 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution +system.cpu.toL2Bus.throughput 166495312 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95977 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 71640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 71640 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3179804 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 641536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104183232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104824768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104824768 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159707 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3179816 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104181888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104825344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104825344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914915000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 914925500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15531000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 15572000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2358250250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8311 # number of replacements -system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394910393 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39396.487729 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 8345 # number of replacements +system.cpu.icache.tags.tagsinuse 1652.999012 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 392562699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10054 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39045.424607 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1652.999012 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.807128 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.807128 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1567 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 789856696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 789856696 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 394910393 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394910393 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394910393 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394910393 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394910393 # number of overall hits -system.cpu.icache.overall_hits::total 394910393 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses -system.cpu.icache.overall_misses::total 12943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 383664999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 383664999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 383664999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 383664999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 383664999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 383664999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394923336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394923336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394923336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394923336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394923336 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 394923336 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 785161352 # Number of tag accesses +system.cpu.icache.tags.data_accesses 785161352 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 392562699 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 392562699 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 392562699 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 392562699 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 392562699 # number of overall hits +system.cpu.icache.overall_hits::total 392562699 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12950 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12950 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12950 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12950 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12950 # number of overall misses +system.cpu.icache.overall_misses::total 12950 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 384762999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 384762999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 384762999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 384762999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 384762999 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72984.082761 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309018 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308794 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309018 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308794 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72695.510500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73430.274820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73425.316346 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84901.806950 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84901.806950 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72695.510500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75050.360286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75036.700123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72695.510500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75050.360286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75036.700123 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -834,187 +786,181 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2752 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406514 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409266 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2762 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406521 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409283 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66853 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66853 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2752 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28606297250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28770493500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164196250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28606297250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28770493500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278386 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278360 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473374 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29761980750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165956500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29596024250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29761980750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278396 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278371 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933180 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308784 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308784 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59664.335029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.025358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60085.626358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.048910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60822.045504 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72824.727387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72824.727387 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527796 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 667945835 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531892 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 436.026714 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 408904250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.588575 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1527769 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.584887 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 666211737 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531865 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 434.902382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 409920250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.584887 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999655 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999655 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2365 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 390 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1343398986 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1343398986 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 458212871 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458212871 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209732941 # 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Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 456456827 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 456456827 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209754882 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209754882 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 666211709 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666211709 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666211709 # number of overall hits +system.cpu.dcache.overall_hits::total 666211709 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925791 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925791 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1040014 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 123583034352 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 123583034352 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 123583034352 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460138627 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460138627 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2965805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2965805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2965805 # number of overall misses +system.cpu.dcache.overall_misses::total 2965805 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458382618 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 670933523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 670933523 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 670933523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 670933523 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004185 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004185 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004453 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.416137 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.416137 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.018802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.018802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41363.784634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41363.784634 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17901 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 132 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 338 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669177514 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669177514 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669177514 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669177514 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004934 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40442.978625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40442.978625 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51488.524316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51488.524316 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44316.302110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44316.302110 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18203 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 134 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 374 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.961538 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.671123 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 134 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks -system.cpu.dcache.writebacks::total 95971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465505 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465505 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990315 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990315 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455820 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455820 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455820 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455820 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460251 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460251 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 95977 # number of writebacks +system.cpu.dcache.writebacks::total 95977 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465566 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465566 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 968374 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 968374 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1433940 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1433940 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1433940 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1433940 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460225 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460225 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71640 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 71640 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531891 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531891 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531891 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531891 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41321289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41321289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5347166250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5347166250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 76000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 76000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46668455250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46668455250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46668455250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46668455250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531865 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531865 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41848820250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41848820250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5798224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5798224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47647044250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47647044250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47647044250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47647044250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003186 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003186 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28297.387915 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28297.387915 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74639.394891 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74639.394891 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 76000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 76000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28659.158863 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28659.158863 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80935.566723 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80935.566723 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |