diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/se/40.perlbmk/ref/alpha | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | 847 |
1 files changed, 423 insertions, 424 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index f83552a37..efccfaef5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.561963 # Number of seconds simulated -sim_ticks 561962991000 # Number of ticks simulated -final_tick 561962991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.561049 # Number of seconds simulated +sim_ticks 561048999000 # Number of ticks simulated +final_tick 561048999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333136 # Simulator instruction rate (inst/s) -host_op_rate 333136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 201563357 # Simulator tick rate (ticks/s) -host_mem_usage 305440 # Number of bytes of host memory used -host_seconds 2788.02 # Real time elapsed on the host +host_inst_rate 327042 # Simulator instruction rate (inst/s) +host_op_rate 327042 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197554566 # Simulator tick rate (ticks/s) +host_mem_usage 305844 # Number of bytes of host memory used +host_seconds 2839.97 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 186944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory -system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18657344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2921 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291521 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 332435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32867645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33200080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 332435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 332435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7594294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7594294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7594294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 332435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32867645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40794373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291519 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 333204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 32921189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33254393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7606665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7606665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7606665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 32921189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40861059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291521 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291521 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18640576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18639104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18657344 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17933 # Per bank write bursts -system.physmem.perBankRdBursts::1 18288 # Per bank write bursts -system.physmem.perBankRdBursts::2 18309 # Per bank write bursts -system.physmem.perBankRdBursts::3 18250 # Per bank write bursts -system.physmem.perBankRdBursts::4 18165 # Per bank write bursts -system.physmem.perBankRdBursts::5 18241 # Per bank write bursts -system.physmem.perBankRdBursts::6 18322 # Per bank write bursts -system.physmem.perBankRdBursts::7 18300 # Per bank write bursts -system.physmem.perBankRdBursts::8 18229 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts -system.physmem.perBankRdBursts::10 18214 # Per bank write bursts -system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::0 17937 # Per bank write bursts +system.physmem.perBankRdBursts::1 18285 # Per bank write bursts +system.physmem.perBankRdBursts::2 18301 # Per bank write bursts +system.physmem.perBankRdBursts::3 18253 # Per bank write bursts +system.physmem.perBankRdBursts::4 18160 # Per bank write bursts +system.physmem.perBankRdBursts::5 18247 # Per bank write bursts +system.physmem.perBankRdBursts::6 18325 # Per bank write bursts +system.physmem.perBankRdBursts::7 18297 # Per bank write bursts +system.physmem.perBankRdBursts::8 18227 # Per bank write bursts +system.physmem.perBankRdBursts::9 18224 # Per bank write bursts +system.physmem.perBankRdBursts::10 18215 # Per bank write bursts +system.physmem.perBankRdBursts::11 18384 # Per bank write bursts system.physmem.perBankRdBursts::12 18260 # Per bank write bursts -system.physmem.perBankRdBursts::13 18047 # Per bank write bursts +system.physmem.perBankRdBursts::13 18042 # Per bank write bursts system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18105 # Per bank write bursts +system.physmem.perBankRdBursts::15 18099 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4189 # Per bank write bursts +system.physmem.perBankWrBursts::9 4188 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 561962908000 # Total gap between requests +system.physmem.totGap 561048916000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291519 # Read request sizes (log2) +system.physmem.readPktSize::6 291521 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290732 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1004 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4041 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4041 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,118 +193,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 106018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216.046030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 139.156746 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 265.673827 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41726 39.36% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42732 40.31% 79.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8674 8.18% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 811 0.76% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1515 1.43% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1173 1.11% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 577 0.54% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 518 0.49% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8292 7.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 106018 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.199159 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.197763 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.963064 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 105209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 217.703657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.847395 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 266.018983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39852 37.88% 37.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43676 41.51% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8737 8.30% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 846 0.80% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1608 1.53% 90.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1088 1.03% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 546 0.52% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 586 0.56% 92.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8270 7.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105209 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.193764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.202156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.629260 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4034 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471396 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.862526 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3046 75.36% 75.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 995 24.62% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2975536250 # Total ticks spent queuing -system.physmem.totMemAccLat 8436642500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10216.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4041 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.496907 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.475096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.865198 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3038 75.18% 75.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1001 24.77% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4041 # Writes before turning the bus around for reads +system.physmem.totQLat 2859634000 # Total ticks spent queuing +system.physmem.totMemAccLat 8320309000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9818.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28966.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28568.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing -system.physmem.readRowHits 201381 # Number of row buffer hits during reads -system.physmem.writeRowHits 50515 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes -system.physmem.avgGap 1568843.58 # Average gap between requests -system.physmem.pageHitRate 70.37 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 399311640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 217878375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136904600 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing +system.physmem.readRowHits 202235 # Number of row buffer hits during reads +system.physmem.writeRowHits 50448 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.65 # Row buffer hit rate for writes +system.physmem.avgGap 1566283.22 # Average gap between requests +system.physmem.pageHitRate 70.60 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 396718560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 216463500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1137021600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 110801606310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 239979977250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 389456417535 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.035628 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 398531952000 # Time in different power states -system.physmem_0.memoryStateTime::REF 18764980000 # Time in different power states +system.physmem_0.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 109036341675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240981860250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388629643425 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.687306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 400213963500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18734560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 144660363000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142097780250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 402093720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 219396375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134346200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 111289898520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 239551650750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 389517237165 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.143857 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 397813996000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18764980000 # Time in different power states +system.physmem_1.actEnergy 398601000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 217490625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134307200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 109322809425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240730572750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388664124600 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.748765 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399791677000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18734560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 145378777500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 142520871000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749002 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144241 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157248 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103981751 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513628 # Number of BTB hits +system.cpu.branchPred.lookups 125749073 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144364 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157127 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103970968 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513050 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.315658 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.323432 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691036 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537715 # DTB read hits -system.cpu.dtb.read_misses 198475 # DTB read misses +system.cpu.dtb.read_hits 237538495 # DTB read hits +system.cpu.dtb.read_misses 198467 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736190 # DTB read accesses -system.cpu.dtb.write_hits 98305031 # DTB write hits -system.cpu.dtb.write_misses 7188 # DTB write misses +system.cpu.dtb.read_accesses 237736962 # DTB read accesses +system.cpu.dtb.write_hits 98305062 # DTB write hits +system.cpu.dtb.write_misses 7206 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312219 # DTB write accesses -system.cpu.dtb.data_hits 335842746 # DTB hits -system.cpu.dtb.data_misses 205663 # DTB misses +system.cpu.dtb.write_accesses 98312268 # DTB write accesses +system.cpu.dtb.data_hits 335843557 # DTB hits +system.cpu.dtb.data_misses 205673 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048409 # DTB accesses -system.cpu.itb.fetch_hits 317139351 # ITB hits +system.cpu.dtb.data_accesses 336049230 # DTB accesses +system.cpu.itb.fetch_hits 316986664 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 317139471 # ITB accesses +system.cpu.itb.fetch_accesses 316986784 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,83 +317,83 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1123925982 # number of cpu cycles simulated +system.cpu.numCycles 1122097998 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 27043469 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30863568 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.210098 # CPI: cycles per instruction -system.cpu.ipc 0.826379 # IPC: instructions per cycle -system.cpu.tickCycles 1060172068 # Number of cycles that the object actually ticked -system.cpu.idleCycles 63753914 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.208130 # CPI: cycles per instruction +system.cpu.ipc 0.827726 # IPC: instructions per cycle +system.cpu.tickCycles 1059712720 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62385278 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.699416 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 323503203 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.688853 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322867255 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 414.414040 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 905250250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.699416 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999194 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999194 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 413.599378 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 907886250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.688853 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999192 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999192 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1647 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 649485188 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 649485188 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 225339151 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 225339151 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164052 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164052 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 323503203 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 323503203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 323503203 # number of overall hits -system.cpu.dcache.overall_hits::total 323503203 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648213290 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648213290 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224703202 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224703202 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164053 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164053 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322867255 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322867255 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322867255 # number of overall hits +system.cpu.dcache.overall_hits::total 322867255 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137148 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137148 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849077 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849077 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849077 # number of overall misses -system.cpu.dcache.overall_misses::total 849077 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24941013500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24941013500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10047073750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10047073750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34988087250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34988087250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34988087250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34988087250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 226051080 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 226051080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137147 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849076 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849076 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849076 # number of overall misses +system.cpu.dcache.overall_misses::total 849076 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24858122500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24858122500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10112031250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10112031250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34970153750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34970153750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34970153750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34970153750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225415131 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225415131 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 324352280 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 324352280 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 324352280 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 324352280 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 323716331 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323716331 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323716331 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323716331 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35033.006803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35033.006803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73257.165617 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73257.165617 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41207.201761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41207.201761 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34916.575248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34916.575248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73731.333897 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73731.333897 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41186.129098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41186.129098 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,12 +406,12 @@ system.cpu.dcache.writebacks::writebacks 91489 # nu system.cpu.dcache.writebacks::total 91489 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68137 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68137 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68449 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68136 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68136 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68448 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68448 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68448 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68448 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -421,85 +420,85 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23795842750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23795842750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4974141500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4974141500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28769984250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28769984250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28769984250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28769984250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23712269000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23712269000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5006644750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5006644750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28718913750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28718913750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28718913750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28718913750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33439.115072 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33439.115072 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72077.516628 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72077.516628 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36854.922255 # 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average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10603 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.326033 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 317127004 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25686.619472 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10608 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.311703 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316974313 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25665.936275 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.326033 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823890 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823890 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.311703 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1575 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 634291048 # Number of tag accesses -system.cpu.icache.tags.data_accesses 634291048 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 317127004 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 317127004 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 317127004 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 317127004 # 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Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 633985678 # Number of tag accesses +system.cpu.icache.tags.data_accesses 633985678 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 316974313 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 316974313 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 316974313 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 316974313 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 316974313 # number of overall hits +system.cpu.icache.overall_hits::total 316974313 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12351 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28743.196728 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28743.196728 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28778.277063 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28778.277063 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28778.277063 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28778.277063 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258740 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32592.816287 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 523846 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.797218 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258742 # 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number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 223766250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22823021750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23046788000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 223766250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22823021750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23046788000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12347 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 291522 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 224288000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17859188000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18083476000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4912763250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4912763250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 224288000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22771951250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22996239250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 224288000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22771951250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22996239250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 723964 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 723968 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 12351 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 780628 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792975 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12347 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792979 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12351 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792975 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236495 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 792979 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236580 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310616 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.310617 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236495 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236580 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.367628 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236495 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.367629 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236580 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.367628 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76632.277397 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80839.635286 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80785.002779 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73227.706505 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73227.706505 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79057.313392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79057.313392 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.367629 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76758.384668 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80463.102881 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80414.964625 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73715.406257 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73715.406257 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76758.384668 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78904.889986 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78883.375011 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76758.384668 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78904.889986 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78883.375011 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,103 +634,103 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2920 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2922 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221955 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224877 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2920 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2922 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 288600 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2922 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187160250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15168425250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15355585500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4046889000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4046889000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187160250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19215314250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19402474500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187160250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19215314250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19402474500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 291522 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15084314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15271976000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4079380750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4079380750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187662000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19163694750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19351356750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187662000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19163694750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19351356750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310616 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310617 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367628 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367629 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367628 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64095.976027 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68340.092586 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68284.982768 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60723.069998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60723.069998 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64223.819302 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67961.136266 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67912.574430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61210.604697 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61210.604697 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 723968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723967 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24693 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56605888 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884464 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 884468 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884464 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884468 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884464 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533721000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 884468 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 533723000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19157750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19161500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1221759250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222147750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224874 # Transaction distribution -system.membus.trans_dist::ReadResp 224874 # Transaction distribution +system.membus.trans_dist::ReadReq 224876 # Transaction distribution +system.membus.trans_dist::ReadResp 224876 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649721 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649721 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22924928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649725 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649725 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22925056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22925056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358202 # Request fanout histogram +system.membus.snoop_fanout::samples 358204 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 358204 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 667013500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 358204 # Request fanout histogram +system.membus.reqLayer0.occupancy 732288500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1552224500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1552393250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |