stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

1 files changed, 20 insertions, 5 deletions

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 3ea3d5388..eb3e6af6a 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.489946                       # Nu
 sim_ticks                                489945697500                       # Number of ticks simulated
 final_tick                               489945697500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152136                       # Simulator instruction rate (inst/s)
-host_op_rate                                   187299                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              116346895                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275904                       # Number of bytes of host memory used
-host_seconds                                  4211.08                       # Real time elapsed on the host
+host_inst_rate                                 287135                       # Simulator instruction rate (inst/s)
+host_op_rate                                   353501                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              219588415                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 322476                       # Number of bytes of host memory used
+host_seconds                                  2231.20                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            163712                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          18473856                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             18637568                       # Number of bytes read from this memory
@@ -272,6 +273,7 @@ system.physmem_1.memoryStateTime::REF     16360240000                       # Ti
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT    137017032000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.branchPred.lookups               144591747                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          96197702                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect             97552                       # Number of conditional branches incorrect
@@ -286,6 +288,7 @@ system.cpu.branchPred.indirectHits           15989167                       # Nu
 system.cpu.branchPred.indirectMisses             5518                       # Number of indirect misses.
 system.cpu.branchPredindirectMispredicted         8032                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -315,6 +318,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -344,6 +348,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -373,6 +378,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -403,6 +409,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        979891395                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -449,6 +456,7 @@ system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Cl
 system.cpu.op_class_0::total                788730744                       # Class of committed instruction
 system.cpu.tickCycles                       924243701                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                        55647694                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            778302                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          4092.104499                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378448234                       # Total number of references to valid blocks.
@@ -467,6 +475,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4         1413
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         759382252                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        759382252                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data    249619506                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       249619506                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    128813766                       # number of WriteReq hits
@@ -587,6 +596,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             24859                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1712.892625                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           252585994                       # Total number of references to valid blocks.
@@ -603,6 +613,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1599
 system.cpu.icache.tags.occ_task_id_percent::1024     0.855957                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         505251826                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        505251826                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst    252585994                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       252585994                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     252585994                       # number of demand (read+write) hits
@@ -671,6 +682,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395
 system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           258808                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32560.749490                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1247790                       # Total number of references to valid blocks.
@@ -693,6 +705,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        28951
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         13231738                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        13231738                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks        88712                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total        88712                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        23528                       # number of WritebackClean hits
@@ -845,6 +858,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3314
 system.cpu.toL2Bus.snoop_filter.tot_snoops         2027                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2012                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        739688                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       154810                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        24859                       # Transaction distribution
@@ -877,6 +891,7 @@ system.cpu.toL2Bus.respLayer0.occupancy      39920495                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1173610473                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp             225121                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           190682                       # Transaction distribution