diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1355 |
1 files changed, 678 insertions, 677 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 9a207ffb1..9b1e23041 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.452586 # Number of seconds simulated -sim_ticks 452585997000 # Number of ticks simulated -final_tick 452585997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.452564 # Number of seconds simulated +sim_ticks 452563515000 # Number of ticks simulated +final_tick 452563515000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89374 # Simulator instruction rate (inst/s) -host_op_rate 110031 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63138171 # Simulator tick rate (ticks/s) -host_mem_usage 323296 # Number of bytes of host memory used -host_seconds 7168.18 # Real time elapsed on the host +host_inst_rate 88595 # Simulator instruction rate (inst/s) +host_op_rate 109072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62584453 # Simulator tick rate (ticks/s) +host_mem_usage 324544 # Number of bytes of host memory used +host_seconds 7231.25 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 234368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47997568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12828032 # Number of bytes read from this memory -system.physmem.bytes_read::total 61059968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 234368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 234368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243520 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 749962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 954062 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66305 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66305 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 106051818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 28343855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134913516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9376163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9376163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9376163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 106051818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 28343855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 144289678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 954063 # Number of read requests accepted -system.physmem.writeReqs 66305 # Number of write requests accepted -system.physmem.readBursts 954063 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66305 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61041664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18368 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 234304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48000768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12823616 # Number of bytes read from this memory +system.physmem.bytes_read::total 61058688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 234304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 234304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4243456 # Number of bytes written to this memory +system.physmem.bytes_written::total 4243456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200369 # Number of read requests responded to by this memory +system.physmem.num_reads::total 954042 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 106064158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 28335506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134917389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517726 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517726 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9376487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9376487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9376487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 106064158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 28335506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 144293877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 954043 # Number of read requests accepted +system.physmem.writeReqs 66304 # Number of write requests accepted +system.physmem.readBursts 954043 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61040512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61060032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 287 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 227627 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19636 # Per bank write bursts -system.physmem.perBankRdBursts::1 19225 # Per bank write bursts -system.physmem.perBankRdBursts::2 656809 # Per bank write bursts -system.physmem.perBankRdBursts::3 20104 # Per bank write bursts -system.physmem.perBankRdBursts::4 19566 # Per bank write bursts -system.physmem.perBankRdBursts::5 20746 # Per bank write bursts -system.physmem.perBankRdBursts::6 19449 # Per bank write bursts -system.physmem.perBankRdBursts::7 19830 # Per bank write bursts -system.physmem.perBankRdBursts::8 19282 # Per bank write bursts -system.physmem.perBankRdBursts::9 19792 # Per bank write bursts -system.physmem.perBankRdBursts::10 19287 # Per bank write bursts -system.physmem.perBankRdBursts::11 19476 # Per bank write bursts -system.physmem.perBankRdBursts::12 19427 # Per bank write bursts -system.physmem.perBankRdBursts::13 20933 # Per bank write bursts -system.physmem.perBankRdBursts::14 19357 # Per bank write bursts -system.physmem.perBankRdBursts::15 20857 # Per bank write bursts +system.physmem.bytesReadSys 61058752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4243456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 53 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19632 # Per bank write bursts +system.physmem.perBankRdBursts::1 19241 # Per bank write bursts +system.physmem.perBankRdBursts::2 656774 # Per bank write bursts +system.physmem.perBankRdBursts::3 20103 # Per bank write bursts +system.physmem.perBankRdBursts::4 19565 # Per bank write bursts +system.physmem.perBankRdBursts::5 20788 # Per bank write bursts +system.physmem.perBankRdBursts::6 19429 # Per bank write bursts +system.physmem.perBankRdBursts::7 19781 # Per bank write bursts +system.physmem.perBankRdBursts::8 19292 # Per bank write bursts +system.physmem.perBankRdBursts::9 19805 # Per bank write bursts +system.physmem.perBankRdBursts::10 19337 # Per bank write bursts +system.physmem.perBankRdBursts::11 19452 # Per bank write bursts +system.physmem.perBankRdBursts::12 19407 # Per bank write bursts +system.physmem.perBankRdBursts::13 20952 # Per bank write bursts +system.physmem.perBankRdBursts::14 19359 # Per bank write bursts +system.physmem.perBankRdBursts::15 20841 # Per bank write bursts system.physmem.perBankWrBursts::0 4254 # Per bank write bursts -system.physmem.perBankWrBursts::1 4108 # Per bank write bursts +system.physmem.perBankWrBursts::1 4107 # Per bank write bursts system.physmem.perBankWrBursts::2 4140 # Per bank write bursts system.physmem.perBankWrBursts::3 4154 # Per bank write bursts system.physmem.perBankWrBursts::4 4243 # Per bank write bursts system.physmem.perBankWrBursts::5 4230 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::7 4093 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts @@ -83,27 +83,27 @@ system.physmem.perBankWrBursts::11 4097 # Pe system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4153 # Per bank write bursts +system.physmem.perBankWrBursts::15 4155 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 452585986500 # Total gap between requests +system.physmem.totGap 452563504500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 954063 # Read request sizes (log2) +system.physmem.readPktSize::6 954043 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66305 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 760072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14330 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 760089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14329 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see @@ -150,15 +150,15 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4997 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see @@ -197,30 +197,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 205647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.429381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.568290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 286.974442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59802 29.08% 29.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 62661 30.47% 59.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15924 7.74% 67.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3207 1.56% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3374 1.64% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48035 23.36% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7705 3.75% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 205577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.529062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.622998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.021434 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59787 29.08% 29.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62582 30.44% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15931 7.75% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3214 1.56% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3392 1.65% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 47997 23.35% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7735 3.76% 97.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 205647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 205577 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 234.045421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.559432 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3989.674296 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4017 99.70% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-16383 7 0.17% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-32767 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::90112-98303 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::212992-221183 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 209.250931 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.553257 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2756.803776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 4005 99.40% 99.40% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::61440-65535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::94208-98303 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::114688-118783 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads @@ -242,65 +244,65 @@ system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Wr system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads -system.physmem.totQLat 15106541272 # Total ticks spent queuing -system.physmem.totMemAccLat 32989841272 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4768880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15838.67 # Average queueing delay per DRAM burst +system.physmem.totQLat 15078460254 # Total ticks spent queuing +system.physmem.totMemAccLat 32961422754 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4768790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15809.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34588.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 9.36 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.91 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34559.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 9.37 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.13 # Data bus utilization in percentage system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 788463 # Number of row buffer hits during reads -system.physmem.writeRowHits 25883 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 788510 # Number of row buffer hits during reads +system.physmem.writeRowHits 25885 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes -system.physmem.avgGap 443551.72 # Average gap between requests +system.physmem.avgGap 443538.82 # Average gap between requests system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1032091200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 563145000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6203792400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216412560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 305512170480 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3557164500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 346645334700 # Total energy per rank (pJ) -system.physmem_0.averagePower 765.925147 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4194914578 # Time in different power states -system.physmem_0.memoryStateTime::REF 15112760000 # Time in different power states +system.physmem_0.actEnergy 1031660280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 562909875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6203308800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216399600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305467849845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3582027000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 346623188280 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.915744 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4235605578 # Time in different power states +system.physmem_0.memoryStateTime::REF 15111980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 433276166672 # Time in different power states +system.physmem_0.memoryStateTime::ACT 433212896922 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 522539640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 285115875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1235348400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96876011835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 186571355250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 315263655000 # Total energy per rank (pJ) -system.physmem_1.averagePower 696.586172 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 309737229647 # Time in different power states -system.physmem_1.memoryStateTime::REF 15112760000 # Time in different power states +system.physmem_1.actEnergy 522411120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 285045750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1235535600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212738400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96975747585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 186469836000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 315260347335 # Total energy per rank (pJ) +system.physmem_1.averagePower 696.614859 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 309568131397 # Time in different power states +system.physmem_1.memoryStateTime::REF 15111980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127733879103 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127880371103 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234612390 # Number of BP lookups -system.cpu.branchPred.condPredicted 162472835 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514556 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121579993 # Number of BTB lookups -system.cpu.branchPred.BTBHits 107625887 # Number of BTB hits +system.cpu.branchPred.lookups 234612924 # Number of BP lookups +system.cpu.branchPred.condPredicted 162473080 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121580360 # Number of BTB lookups +system.cpu.branchPred.BTBHits 107626063 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.522696 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035644 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300133 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.522573 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300027 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -419,84 +421,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 905171995 # number of cpu cycles simulated +system.cpu.numCycles 905127031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 86003110 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1202048869 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234612390 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132661531 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 803279049 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064713 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1868 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85998683 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1202051079 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234612924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 132661709 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 803240111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064493 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1917 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3204 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370083974 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652982 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 904819618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.657214 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3269 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370084311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652880 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 904776257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.657297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222849160 24.63% 24.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 224059075 24.76% 49.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98313082 10.87% 60.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359598301 39.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222804793 24.63% 24.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 224059137 24.76% 49.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98313262 10.87% 60.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 359599065 39.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 904819618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259191 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.327978 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121904104 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 244100755 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484657410 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38638668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518681 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24546049 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13811 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248144086 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968857 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518681 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178914873 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 163328471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207028 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319861 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82530704 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190654266 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 24276153 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24946873 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2269725 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41528835 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1707155 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1226040359 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5813734095 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358184137 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876447 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 904776257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259204 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.328047 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121900634 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 244061321 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484657119 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38638613 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518570 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24546046 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13813 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248144936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39968729 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518570 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178911503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 163289745 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 206869 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319515 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82530055 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190655236 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 24276259 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24947259 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2269584 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41529012 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1706231 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1226042317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5813738555 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358185798 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876436 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 351262129 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 351264087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7264 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108789591 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 367388897 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236094901 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1672944 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5307285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1169836169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12331 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017123135 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19093941 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 381123542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1038508983 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 177 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 904819618 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.124117 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093910 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108789745 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 367388846 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095095 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1811043 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5312656 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1169837126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12332 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017086167 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18990404 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 381124500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1038523748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 904776257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.124130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 347160042 38.37% 38.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227103662 25.10% 63.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217769500 24.07% 87.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96665190 10.68% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16121217 1.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347117204 38.36% 38.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227104713 25.10% 63.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217802755 24.07% 87.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96630403 10.68% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16121175 1.78% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -504,9 +506,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 904819618 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 904776257 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63881232 18.86% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63882217 18.87% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available @@ -535,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 158064095 46.67% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116064822 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 158029640 46.67% 65.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116058922 34.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456367780 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456367665 44.87% 44.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued @@ -565,86 +567,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478995 1.13% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322109040 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215596292 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322074351 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215594127 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017123135 # Type of FU issued -system.cpu.iq.rate 1.123679 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338665181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3234948583 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1507425320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934275773 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61876427 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565693 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1017086167 # Type of FU issued +system.cpu.iq.rate 1.123694 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338625811 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3234688378 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1507427240 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934273902 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876428 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565689 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321978571 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1321902233 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9959468 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 9959480 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 115147959 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 115147908 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114405 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 107114599 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065764 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19863 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19869 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518681 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35329232 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1169854056 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518570 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35329075 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27772 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1169855013 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 367388897 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236094901 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6591 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29598 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 367388846 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095095 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6592 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 88 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30218 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437212 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784515 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221727 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974753111 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303296723 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42370024 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 15437101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784620 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221721 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974751329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303296690 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42334838 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497769972 # number of memory reference insts executed -system.cpu.iew.exec_branches 150611064 # Number of branches executed -system.cpu.iew.exec_stores 194473249 # Number of stores executed -system.cpu.iew.exec_rate 1.076871 # Inst execution rate -system.cpu.iew.wb_sent 963726707 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960428223 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536045857 # num instructions producing a value -system.cpu.iew.wb_consumers 893287669 # num instructions consuming a value -system.cpu.iew.wb_rate 1.061045 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600082 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 357425551 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 5555 # number of nop insts executed +system.cpu.iew.exec_refs 497768330 # number of memory reference insts executed +system.cpu.iew.exec_branches 150610966 # Number of branches executed +system.cpu.iew.exec_stores 194471640 # Number of stores executed +system.cpu.iew.exec_rate 1.076922 # Inst execution rate +system.cpu.iew.wb_sent 963724922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960426352 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536046741 # num instructions producing a value +system.cpu.iew.wb_consumers 893290325 # num instructions consuming a value +system.cpu.iew.wb_rate 1.061096 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600081 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 357426439 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 853996264 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.923576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.715161 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500772 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 853952830 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.923623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.715196 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 515355287 60.35% 60.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174404345 20.42% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72937486 8.54% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32899801 3.85% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8539084 1.00% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14259189 1.67% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7267219 0.85% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5975069 0.70% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22358784 2.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 515313788 60.34% 60.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174402011 20.42% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72937800 8.54% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32899590 3.85% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538808 1.00% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14259214 1.67% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7267758 0.85% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5975049 0.70% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22358812 2.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 853996264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 853952830 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -690,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22358784 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1977784350 # The number of ROB reads -system.cpu.rob.rob_writes 2343138350 # The number of ROB writes -system.cpu.timesIdled 648611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 352377 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22358812 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1977741776 # The number of ROB reads +system.cpu.rob.rob_writes 2343140199 # The number of ROB writes +system.cpu.timesIdled 648615 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 350774 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.412898 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.412898 # CPI: Total CPI of All Threads -system.cpu.ipc 0.707765 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.707765 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995811618 # number of integer regfile reads -system.cpu.int_regfile_writes 567906414 # number of integer regfile writes +system.cpu.cpi 1.412828 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.412828 # CPI: Total CPI of All Threads +system.cpu.ipc 0.707800 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.707800 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995808117 # number of integer regfile reads +system.cpu.int_regfile_writes 567906123 # number of integer regfile writes system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794441379 # number of cc regfile reads -system.cpu.cc_regfile_writes 384896518 # number of cc regfile writes -system.cpu.misc_regfile_reads 715823215 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794435958 # number of cc regfile reads +system.cpu.cc_regfile_writes 384896498 # number of cc regfile writes +system.cpu.misc_regfile_reads 715821566 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756185 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.937157 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216587 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258294 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2756183 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.937153 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216547 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756695 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258388 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.937157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.937153 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347973 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347973 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906811 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906811 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839347867 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347867 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906808 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906808 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414200611 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414200611 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414203768 # number of overall hits -system.cpu.dcache.overall_hits::total 414203768 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3035079 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3035079 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044666 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414200564 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414200564 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414203721 # number of overall hits +system.cpu.dcache.overall_hits::total 414203721 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3035071 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3035071 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044669 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4079745 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4079745 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4080391 # number of overall misses -system.cpu.dcache.overall_misses::total 4080391 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76869214000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76869214000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10006334850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10006334850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4079740 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4079740 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4080386 # number of overall misses +system.cpu.dcache.overall_misses::total 4080386 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76845731000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76845731000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10002174850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10002174850 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86875548850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86875548850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86875548850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86875548850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 86847905850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86847905850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86847905850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86847905850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328827 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -772,10 +774,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284159 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284159 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418280304 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280304 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284107 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284107 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses @@ -788,56 +790,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25326.923615 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25326.923615 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9578.501502 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9578.501502 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.491873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.491873 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21294.357576 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21294.357576 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21290.986293 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21290.986293 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21287.607997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21284.237778 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 352038 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 351058 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4878 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4882 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.168512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.908644 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2756185 # number of writebacks -system.cpu.dcache.writebacks::total 2756185 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323643 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323643 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2756183 # number of writebacks +system.cpu.dcache.writebacks::total 2756183 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999866 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999866 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323646 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323646 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1323515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1323515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1323515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1323515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035207 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035207 # 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number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756871 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756871 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65569114500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 65569114500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5957184350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5957184350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71526298850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 71526298850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71531875350 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 71531875350 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756228 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756228 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756869 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756869 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65547149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 65547149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5956550350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5956550350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5499000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5499000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71503699350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 71503699350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71509198350 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 71509198350 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses @@ -848,229 +850,229 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32217.417933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32217.417933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8262.128046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8262.128046 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8699.687988 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8699.687988 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25950.772922 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25950.772922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25946.761872 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25946.761872 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8261.248740 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8261.248740 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8578.783151 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8578.783151 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322 # 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Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.588578 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.872217 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997797 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.720775 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997502 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997502 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745337941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745337941 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364909744 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364909744 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364909744 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364909744 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364909744 # number of overall hits -system.cpu.icache.overall_hits::total 364909744 # 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miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013980 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013980 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013980 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013980 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.446295 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8111.446295 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8111.446295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8111.446295 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 79493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3667 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3635 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.858195 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.868776 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 5169363 # number of writebacks -system.cpu.icache.writebacks::total 5169363 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4154 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4154 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4154 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4154 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4154 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4154 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170049 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170049 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170049 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170049 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170049 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170049 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39346514434 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39346514434 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39346514434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39346514434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39346514434 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39346514434 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.472248 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.472248 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 5169029 # number of writebacks +system.cpu.icache.writebacks::total 5169029 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169715 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5169715 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169715 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169715 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5169715 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5169715 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39342077434 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39342077434 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39342077434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39342077434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39342077434 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39342077434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013969 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013969 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013969 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.105670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.105670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350388 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355069 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350427 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355108 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 4095 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790235 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 301561 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16356.089687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13502376 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 317924 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 42.470452 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4790132 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 301513 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16356.090183 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13598662 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 317875 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 42.779904 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 60356537500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9847.960617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6508.129070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.601072 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397225 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998296 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6319 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 10044 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4867 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7658 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.385681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.613037 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 244381666 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 244381666 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 9848.276079 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6507.814104 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.601091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6290 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 10072 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4827 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1956 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7712 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.383911 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.614746 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 244370866 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 244370866 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 735261 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 735261 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6546111 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6546111 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718464 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718464 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5166212 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5166212 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286380 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1286380 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5166212 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2004844 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7171056 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5166212 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2004844 # number of overall hits -system.cpu.l2cache.overall_hits::total 7171056 # number of overall hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6545775 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6545775 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718468 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718468 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5165879 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5165879 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286323 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1286323 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5165879 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2004791 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7170670 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5165879 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2004791 # number of overall hits +system.cpu.l2cache.overall_hits::total 7170670 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 174 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 174 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2385 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2385 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3664 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3664 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749468 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 749468 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3664 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 751853 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 755517 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3664 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 751853 # number of overall misses -system.cpu.l2cache.overall_misses::total 755517 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195908500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 195908500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 270114500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 270114500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 54154115500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 54154115500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 270114500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 54350024000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 54620138500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 270114500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 54350024000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 54620138500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 2381 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2381 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3663 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3663 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749523 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 749523 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3663 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 751904 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 755567 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3663 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 751904 # number of overall misses +system.cpu.l2cache.overall_misses::total 755567 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195784000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 195784000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 268224500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 268224500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 54132437000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 54132437000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 268224500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 54328221000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 54596445500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 268224500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 54328221000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 54596445500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 735261 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 735261 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6546111 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6546111 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6545775 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6545775 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 174 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 174 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5169876 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5169876 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2035848 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2035848 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5169876 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756697 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7926573 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5169876 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756697 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7926573 # number of overall (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5169542 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5169542 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2035846 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2035846 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5169542 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756695 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7926237 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5169542 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756695 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7926237 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003309 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003309 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003303 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003303 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.000709 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.000709 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368136 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368136 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368163 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000709 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.272737 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.095314 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.272756 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.095325 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000709 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.272737 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.095314 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82141.928721 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82141.928721 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73721.206332 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73721.206332 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72256.741449 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72256.741449 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73721.206332 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72288.098870 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72295.048953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73721.206332 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72288.098870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72295.048953 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.272756 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.095325 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82227.635447 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82227.635447 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73225.361725 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73225.361725 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72222.516187 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72222.516187 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73225.361725 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72254.198674 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72258.906887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73225.361725 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72254.198674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72258.906887 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1079,156 +1081,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66305 # number of writebacks -system.cpu.l2cache.writebacks::total 66305 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 66304 # number of writebacks +system.cpu.l2cache.writebacks::total 66304 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1019 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::total 1019 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 872 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 872 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 873 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 873 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1891 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1892 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1892 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1893 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1891 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1892 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200528 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 200528 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 1892 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1893 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200459 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 200459 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1366 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1366 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3663 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3663 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748596 # 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number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2993500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133767000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133767000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248088000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248088000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49620654000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49620654000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248088000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49754421000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 50002509000 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 246204000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 246204000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49598643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49598643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246204000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49732310000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 49978514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246204000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49732310000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16513318471 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66491832471 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367707 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367707 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.095076 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367734 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367734 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.095086 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.120374 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82372.666141 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17204.022989 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17204.022989 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97926.061493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97926.061493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67728.091728 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67728.091728 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66284.957440 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66284.957440 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66349.323603 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69716.843102 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120377 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 15852468 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 15851796 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925416 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 760150 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116849 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7205895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6546111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 987513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243924 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 760180 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116881 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 7189951 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 987519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243847 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170049 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035848 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23135037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661654912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311653440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 973308352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1297915 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9224662 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.222014 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.558747 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8269921 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23778205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661668416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352824192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1014492608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1297843 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9224254 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.222027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.558758 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7819958 84.77% 84.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 761403 8.25% 93.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 643301 6.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7819520 84.77% 84.77% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 761435 8.25% 93.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 643299 6.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9224662 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15851782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9224254 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15851110000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755313513 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7754813511 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135165933 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135160937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 952696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66305 # Transaction distribution -system.membus.trans_dist::CleanEvict 227453 # Transaction distribution +system.membus.trans_dist::ReadResp 952680 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66304 # Transaction distribution +system.membus.trans_dist::CleanEvict 227429 # Transaction distribution system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 1366 # Transaction distribution -system.membus.trans_dist::ReadExResp 1366 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 952697 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2202231 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2202231 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65303488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65303488 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 1362 # Transaction distribution +system.membus.trans_dist::ReadExResp 1362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 952681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2201992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2201992 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65302144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65302144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1247995 # Request fanout histogram +system.membus.snoop_fanout::samples 1247950 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1247995 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1247950 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1247995 # Request fanout histogram -system.membus.reqLayer0.occupancy 1752388071 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1247950 # Request fanout histogram +system.membus.reqLayer0.occupancy 1752348040 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 5021031104 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5020538027 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |