diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1792 |
1 files changed, 899 insertions, 893 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e148c082a..4c772ec0f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.452564 # Number of seconds simulated -sim_ticks 452563515000 # Number of ticks simulated -final_tick 452563515000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.326731 # Number of seconds simulated +sim_ticks 326731324000 # Number of ticks simulated +final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57394 # Simulator instruction rate (inst/s) -host_op_rate 70660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40544083 # Simulator tick rate (ticks/s) -host_mem_usage 306292 # Number of bytes of host memory used -host_seconds 11162.26 # Real time elapsed on the host +host_inst_rate 133673 # Simulator instruction rate (inst/s) +host_op_rate 164569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68173047 # Simulator tick rate (ticks/s) +host_mem_usage 277340 # Number of bytes of host memory used +host_seconds 4792.68 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 234304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48000768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12823616 # Number of bytes read from this memory -system.physmem.bytes_read::total 61058688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 234304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 234304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243456 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200369 # Number of read requests responded to by this memory -system.physmem.num_reads::total 954042 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 106064158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 28335506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134917389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517726 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517726 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9376487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9376487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9376487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 106064158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 28335506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 144293877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 954043 # Number of read requests accepted -system.physmem.writeReqs 66304 # Number of write requests accepted -system.physmem.readBursts 954043 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66304 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61040512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61058752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 53 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory +system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 953240 # Number of read requests accepted +system.physmem.writeReqs 66334 # Number of write requests accepted +system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19632 # Per bank write bursts -system.physmem.perBankRdBursts::1 19241 # Per bank write bursts -system.physmem.perBankRdBursts::2 656774 # Per bank write bursts -system.physmem.perBankRdBursts::3 20103 # Per bank write bursts -system.physmem.perBankRdBursts::4 19565 # Per bank write bursts -system.physmem.perBankRdBursts::5 20788 # Per bank write bursts -system.physmem.perBankRdBursts::6 19429 # Per bank write bursts -system.physmem.perBankRdBursts::7 19781 # Per bank write bursts -system.physmem.perBankRdBursts::8 19292 # Per bank write bursts -system.physmem.perBankRdBursts::9 19805 # Per bank write bursts -system.physmem.perBankRdBursts::10 19337 # Per bank write bursts -system.physmem.perBankRdBursts::11 19452 # Per bank write bursts -system.physmem.perBankRdBursts::12 19407 # Per bank write bursts -system.physmem.perBankRdBursts::13 20952 # Per bank write bursts -system.physmem.perBankRdBursts::14 19359 # Per bank write bursts -system.physmem.perBankRdBursts::15 20841 # Per bank write bursts -system.physmem.perBankWrBursts::0 4254 # Per bank write bursts -system.physmem.perBankWrBursts::1 4107 # Per bank write bursts +system.physmem.perBankRdBursts::0 19685 # Per bank write bursts +system.physmem.perBankRdBursts::1 19287 # Per bank write bursts +system.physmem.perBankRdBursts::2 657567 # Per bank write bursts +system.physmem.perBankRdBursts::3 20052 # Per bank write bursts +system.physmem.perBankRdBursts::4 19480 # Per bank write bursts +system.physmem.perBankRdBursts::5 20770 # Per bank write bursts +system.physmem.perBankRdBursts::6 19386 # Per bank write bursts +system.physmem.perBankRdBursts::7 19760 # Per bank write bursts +system.physmem.perBankRdBursts::8 19321 # Per bank write bursts +system.physmem.perBankRdBursts::9 19768 # Per bank write bursts +system.physmem.perBankRdBursts::10 19303 # Per bank write bursts +system.physmem.perBankRdBursts::11 19444 # Per bank write bursts +system.physmem.perBankRdBursts::12 19433 # Per bank write bursts +system.physmem.perBankRdBursts::13 20871 # Per bank write bursts +system.physmem.perBankRdBursts::14 19269 # Per bank write bursts +system.physmem.perBankRdBursts::15 19527 # Per bank write bursts +system.physmem.perBankWrBursts::0 4288 # Per bank write bursts +system.physmem.perBankWrBursts::1 4110 # Per bank write bursts system.physmem.perBankWrBursts::2 4140 # Per bank write bursts system.physmem.perBankWrBursts::3 4154 # Per bank write bursts -system.physmem.perBankWrBursts::4 4243 # Per bank write bursts -system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.perBankWrBursts::4 4242 # Per bank write bursts +system.physmem.perBankWrBursts::5 4232 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4093 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4155 # Per bank write bursts +system.physmem.perBankWrBursts::15 4146 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 452563504500 # Total gap between requests +system.physmem.totGap 326731313500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 954043 # Read request sizes (log2) +system.physmem.readPktSize::6 953240 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66304 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 760089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 900 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66334 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,47 +148,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -197,112 +197,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 205577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.529062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.622998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.021434 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59787 29.08% 29.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 62582 30.44% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15931 7.75% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3214 1.56% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3392 1.65% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 47997 23.35% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7735 3.76% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 205577 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 209.250931 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.553257 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2756.803776 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 4005 99.40% 99.40% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::61440-65535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::94208-98303 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::114688-118783 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.396271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.276876 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3401 84.41% 84.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.22% 84.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 462 11.47% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 50 1.24% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.89% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.40% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.45% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.25% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.15% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.15% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads -system.physmem.totQLat 15078460254 # Total ticks spent queuing -system.physmem.totMemAccLat 32961422754 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4768790000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15809.52 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads +system.physmem.totQLat 12733277648 # Total ticks spent queuing +system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34559.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 9.37 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.13 # Data bus utilization in percentage -system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 788510 # Number of row buffer hits during reads -system.physmem.writeRowHits 25885 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes -system.physmem.avgGap 443538.82 # Average gap between requests -system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1031660280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 562909875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6203308800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216399600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 305467849845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3582027000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 346623188280 # Total energy per rank (pJ) -system.physmem_0.averagePower 765.915744 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4235605578 # Time in different power states -system.physmem_0.memoryStateTime::REF 15111980000 # Time in different power states +system.physmem.busUtil 1.56 # Data bus utilization in percentage +system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing +system.physmem.readRowHits 805882 # Number of row buffer hits during reads +system.physmem.writeRowHits 26140 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes +system.physmem.avgGap 320458.66 # Average gap between requests +system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) +system.physmem_0.averagePower 771.975754 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states +system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 433212896922 # Time in different power states +system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 522411120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 285045750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1235535600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212738400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96975747585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 186469836000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 315260347335 # Total energy per rank (pJ) -system.physmem_1.averagePower 696.614859 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 309568131397 # Time in different power states -system.physmem_1.memoryStateTime::REF 15111980000 # Time in different power states +system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) +system.physmem_1.averagePower 704.579541 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states +system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127880371103 # Time in different power states +system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234612924 # Number of BP lookups -system.cpu.branchPred.condPredicted 162473080 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514448 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121580360 # Number of BTB lookups -system.cpu.branchPred.BTBHits 107626063 # Number of BTB hits +system.cpu.branchPred.lookups 174663372 # Number of BP lookups +system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.522573 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300027 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,232 +426,232 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 905127031 # number of cpu cycles simulated +system.cpu.numCycles 653462649 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85998683 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1202051079 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234612924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132661709 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 803240111 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064493 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1917 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3269 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370084311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652880 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 904776257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.657297 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222804793 24.63% 24.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 224059137 24.76% 49.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98313262 10.87% 60.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359599065 39.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 904776257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.328047 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121900634 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 244061321 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484657119 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38638613 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518570 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24546046 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13813 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248144936 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968729 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518570 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178911503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 163289745 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 206869 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319515 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82530055 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190655236 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 24276259 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24947259 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2269584 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41529012 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1706231 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1226042317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5813738555 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358185798 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876436 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4376071754 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 351264087 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7264 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108789745 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 367388846 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095095 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1811043 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5312656 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1169837126 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017086167 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18990404 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 381124500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1038523748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 904776257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.124130 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093860 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 248251839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 347117204 38.36% 38.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227104713 25.10% 63.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217802755 24.07% 87.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96630403 10.68% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16121175 1.78% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 904776257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63882217 18.87% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 158029640 46.67% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116058922 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456367665 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322074351 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215594127 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017086167 # Type of FU issued -system.cpu.iq.rate 1.123694 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338625811 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332937 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3234688378 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1507427240 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934273902 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61876428 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565689 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321902233 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9959480 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued +system.cpu.iq.rate 1.316105 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 115147908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114599 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065775 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19869 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518570 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35329075 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27772 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1169855013 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 367388846 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095095 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6592 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 88 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30218 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784620 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221721 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751329 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303296690 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42334838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5555 # number of nop insts executed -system.cpu.iew.exec_refs 497768330 # number of memory reference insts executed -system.cpu.iew.exec_branches 150610966 # Number of branches executed -system.cpu.iew.exec_stores 194471640 # Number of stores executed -system.cpu.iew.exec_rate 1.076922 # Inst execution rate -system.cpu.iew.wb_sent 963724922 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960426352 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536046741 # num instructions producing a value -system.cpu.iew.wb_consumers 893290325 # num instructions consuming a value -system.cpu.iew.wb_rate 1.061096 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600081 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 357426439 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10252 # number of nop insts executed +system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed +system.cpu.iew.exec_branches 143379422 # Number of branches executed +system.cpu.iew.exec_stores 152688943 # Number of stores executed +system.cpu.iew.exec_rate 1.301023 # Inst execution rate +system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487338276 # num instructions producing a value +system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value +system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500772 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 853952830 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.923623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.715196 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 515313788 60.34% 60.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174402011 20.42% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72937800 8.54% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32899590 3.85% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8538808 1.00% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14259214 1.67% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7267758 0.85% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5975049 0.70% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22358812 2.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 853952830 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -692,387 +697,387 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22358812 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1977741776 # The number of ROB reads -system.cpu.rob.rob_writes 2343140199 # The number of ROB writes -system.cpu.timesIdled 648615 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 350774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1500478116 # The number of ROB reads +system.cpu.rob.rob_writes 1798380886 # The number of ROB writes +system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.412828 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.412828 # CPI: Total CPI of All Threads -system.cpu.ipc 0.707800 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.707800 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995808121 # number of integer regfile reads -system.cpu.int_regfile_writes 567906123 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794435958 # number of cc regfile reads -system.cpu.cc_regfile_writes 384896498 # number of cc regfile writes -system.cpu.misc_regfile_reads 715821566 # number of misc regfile reads +system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868460109 # number of integer regfile reads +system.cpu.int_regfile_writes 500697086 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads +system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes +system.cpu.misc_regfile_reads 632347857 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756183 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.937153 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216547 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756695 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258388 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.937153 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756452 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347867 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347867 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906808 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906808 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414200564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414200564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414203721 # number of overall hits -system.cpu.dcache.overall_hits::total 414203721 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3035071 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3035071 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044669 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits +system.cpu.dcache.overall_hits::total 371035352 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4079740 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4079740 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4080386 # number of overall misses -system.cpu.dcache.overall_misses::total 4080386 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76845731000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76845731000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10002174850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10002174850 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86847905850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86847905850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86847905850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86847905850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328827 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses +system.cpu.dcache.overall_misses::total 3447085 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280304 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280304 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284107 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284107 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008101 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.491873 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.491873 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21287.607997 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21284.237778 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 351058 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4882 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.908644 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2756183 # number of writebacks -system.cpu.dcache.writebacks::total 2756183 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999866 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999866 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323646 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks +system.cpu.dcache.writebacks::total 2756452 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1323512 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1323512 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1323512 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1323512 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035205 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756228 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756228 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756869 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756869 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65547149000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 65547149000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5956550350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5956550350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5499000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5499000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71503699350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 71503699350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71509198350 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 71509198350 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8261.248740 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8261.248740 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8578.783151 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8578.783151 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25938.555060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25938.555060 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169029 # number of replacements -system.cpu.icache.tags.tagsinuse 510.720775 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364910405 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169539 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.588578 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.720775 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997502 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997502 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1979880 # number of replacements +system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745338281 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745338281 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364910416 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364910416 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364910416 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364910416 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364910416 # number of overall hits -system.cpu.icache.overall_hits::total 364910416 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5173868 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5173868 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5173868 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5173868 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5173868 # number of overall misses -system.cpu.icache.overall_misses::total 5173868 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41967552420 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41967552420 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41967552420 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41967552420 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41967552420 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41967552420 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370084284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370084284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370084284 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370084284 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370084284 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370084284 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013980 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013980 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013980 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013980 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013980 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013980 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.446295 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8111.446295 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8111.446295 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8111.446295 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 79493 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3635 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits +system.cpu.icache.overall_hits::total 245759426 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses +system.cpu.icache.overall_misses::total 1983591 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.868776 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.120377 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 15851796 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925416 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 760180 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116881 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7205559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 7189951 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 987519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8269921 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23778205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661668416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352824192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1014492608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1297843 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9224254 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.222027 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.558758 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7819520 84.77% 84.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 761435 8.25% 93.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 643299 6.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9224254 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15851110000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754813511 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135160937 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 952680 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66304 # Transaction distribution -system.membus.trans_dist::CleanEvict 227429 # Transaction distribution -system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 1362 # Transaction distribution -system.membus.trans_dist::ReadExResp 1362 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 952681 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2201992 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2201992 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65302144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65302144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 951856 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution +system.membus.trans_dist::CleanEvict 227102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 185 # Transaction distribution +system.membus.trans_dist::ReadExReq 1383 # Transaction distribution +system.membus.trans_dist::ReadExResp 1383 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1247950 # Request fanout histogram +system.membus.snoop_fanout::samples 1246861 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1247950 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1247950 # Request fanout histogram -system.membus.reqLayer0.occupancy 1752348040 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 5020538027 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.snoop_fanout::total 1246861 # Request fanout histogram +system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |