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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
commit4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch)
treec6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
parent542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff)
downloadgem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt')
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt475
1 files changed, 297 insertions, 178 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 801f115d2..b8fd6e344 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.708285 # Nu
sim_ticks 708285420500 # Number of ticks simulated
final_tick 708285420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74841 # Simulator instruction rate (inst/s)
-host_tick_rate 28116271 # Simulator tick rate (ticks/s)
-host_mem_usage 262240 # Number of bytes of host memory used
-host_seconds 25191.30 # Real time elapsed on the host
-sim_insts 1885333786 # Number of instructions simulated
+host_inst_rate 110657 # Simulator instruction rate (inst/s)
+host_op_rate 150700 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56615274 # Simulator tick rate (ticks/s)
+host_mem_usage 229476 # Number of bytes of host memory used
+host_seconds 12510.50 # Real time elapsed on the host
+sim_insts 1384379033 # Number of instructions simulated
+sim_ops 1885333786 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94806144 # Number of bytes read from this memory
system.physmem.bytes_inst_read 201024 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
@@ -281,7 +283,8 @@ system.cpu.iew.wb_penalized 0 # nu
system.cpu.iew.wb_rate 1.741158 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.534869 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1192760864 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 38418907 # The number of times a branch was mispredicted
@@ -302,7 +305,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1198732893 # Number of insts commited each cycle
-system.cpu.commit.count 1885344802 # Number of instructions committed
+system.cpu.commit.committedInsts 1384390049 # Number of instructions committed
+system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908385853 # Number of memory references committed
system.cpu.commit.loads 631388869 # Number of loads committed
@@ -317,12 +321,13 @@ system.cpu.rob.rob_reads 4196573290 # Th
system.cpu.rob.rob_writes 6322749564 # The number of ROB writes
system.cpu.timesIdled 1340847 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51326273 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1885333786 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated
-system.cpu.cpi 0.751363 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.751363 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.330914 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.330914 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 1384379033 # Number of Instructions Simulated
+system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated
+system.cpu.cpi 1.023254 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.023254 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.977275 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.977275 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12567200244 # number of integer regfile reads
system.cpu.int_regfile_writes 2359430733 # number of integer regfile writes
system.cpu.fp_regfile_reads 68800397 # number of floating regfile reads
@@ -335,26 +340,39 @@ system.cpu.icache.total_refs 384162744 # To
system.cpu.icache.sampled_refs 28920 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13283.635685 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1638.335274 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.799968 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 384163979 # number of ReadReq hits
-system.cpu.icache.demand_hits 384163979 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 384163979 # number of overall hits
-system.cpu.icache.ReadReq_misses 34037 # number of ReadReq misses
-system.cpu.icache.demand_misses 34037 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 34037 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 300707500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 300707500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 300707500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 384198016 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 384198016 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 384198016 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 8834.723977 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 8834.723977 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 8834.723977 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1638.335274 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.799968 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.799968 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 384163979 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 384163979 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 384163979 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 384163979 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 384163979 # number of overall hits
+system.cpu.icache.overall_hits::total 384163979 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 34037 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 34037 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 34037 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 34037 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 34037 # number of overall misses
+system.cpu.icache.overall_misses::total 34037 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 300707500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 300707500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 300707500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 300707500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 300707500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 300707500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 384198016 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 384198016 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 384198016 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 384198016 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 384198016 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 384198016 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8834.723977 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 8834.723977 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 775 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 775 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 775 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 33262 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 33262 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 33262 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 180621500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 180621500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 180621500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 5430.265769 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 5430.265769 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 5430.265769 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 775 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 775 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 775 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 775 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 775 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 775 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33262 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 33262 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 33262 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 33262 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 33262 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 33262 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 180621500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 180621500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 180621500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 180621500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 180621500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 180621500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5430.265769 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5430.265769 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1531781 # number of replacements
system.cpu.dcache.tagsinuse 4094.791758 # Cycle average of tags in use
@@ -391,40 +412,63 @@ system.cpu.dcache.total_refs 1029515809 # To
system.cpu.dcache.sampled_refs 1535877 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 670.311365 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 305571000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4094.791758 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 753356755 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 276118556 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 15246 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 1029475311 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 1029475311 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1938073 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 817122 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 2755195 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 2755195 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 69347083500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 28485572000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 97832655500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 97832655500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 755294828 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 15249 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 1032230506 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 1032230506 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.000197 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35781.461018 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 34860.855539 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35508.432434 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35508.432434 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4094.791758 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999705 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999705 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 753356755 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 753356755 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276118556 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276118556 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 15246 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 15246 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11672 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11672 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 1029475311 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1029475311 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1029475311 # number of overall hits
+system.cpu.dcache.overall_hits::total 1029475311 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1938073 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1938073 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 817122 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 817122 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 2755195 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2755195 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2755195 # number of overall misses
+system.cpu.dcache.overall_misses::total 2755195 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 69347083500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 69347083500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 28485572000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 28485572000 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 108500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 108500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 97832655500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 97832655500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 97832655500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 97832655500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 755294828 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 755294828 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15249 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 15249 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11672 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11672 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1032230506 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1032230506 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1032230506 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1032230506 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002566 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002951 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000197 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35781.461018 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34860.855539 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36166.666667 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35508.432434 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 106815 # number of writebacks
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-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34089.271013 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480005 # number of replacements
system.cpu.l2cache.tagsinuse 31970.457215 # Cycle average of tags in use
@@ -467,40 +520,82 @@ system.cpu.l2cache.total_refs 85123 # To
system.cpu.l2cache.sampled_refs 1512725 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.056271 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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@@ -509,35 +604,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048597500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048597500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97624500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45921977500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 46019602000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97624500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45921977500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 46019602000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965108 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999079 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908943 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.706781 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31069.092423 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.839866 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------