diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 70391a345..c008b73ab 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.659244 # Nu sim_ticks 659244465000 # Number of ticks simulated final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88407 # Simulator instruction rate (inst/s) -host_op_rate 120399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42099861 # Simulator tick rate (ticks/s) -host_mem_usage 243836 # Number of bytes of host memory used -host_seconds 15659.07 # Real time elapsed on the host +host_inst_rate 153116 # Simulator instruction rate (inst/s) +host_op_rate 208523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72914339 # Simulator tick rate (ticks/s) +host_mem_usage 237584 # Number of bytes of host memory used +host_seconds 9041.36 # Real time elapsed on the host sim_insts 1384375635 # Number of instructions simulated sim_ops 1885330387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory @@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks |