diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1335 |
1 files changed, 668 insertions, 667 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 1e57970d1..ac8776e10 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.659992 # Number of seconds simulated -sim_ticks 659991928000 # Number of ticks simulated -final_tick 659991928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.635788 # Number of seconds simulated +sim_ticks 635788224000 # Number of ticks simulated +final_tick 635788224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102750 # Simulator instruction rate (inst/s) -host_op_rate 139931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48985343 # Simulator tick rate (ticks/s) -host_mem_usage 254632 # Number of bytes of host memory used -host_seconds 13473.25 # Real time elapsed on the host -sim_insts 1384374560 # Number of instructions simulated -sim_ops 1885329312 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 198528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94517696 # Number of bytes read from this memory -system.physmem.bytes_read::total 94716224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 198528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 198528 # Number of instructions bytes read from this memory +host_inst_rate 107590 # Simulator instruction rate (inst/s) +host_op_rate 146523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49411882 # Simulator tick rate (ticks/s) +host_mem_usage 254872 # Number of bytes of host memory used +host_seconds 12867.11 # Real time elapsed on the host +sim_insts 1384378595 # Number of instructions simulated +sim_ops 1885333347 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 160512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30246144 # Number of bytes read from this memory +system.physmem.bytes_read::total 30406656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 160512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 160512 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3102 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2508 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472596 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475104 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 300804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 143210382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 143511185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 300804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 300804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6409581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6409581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6409581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 300804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 143210382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 149920767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1479941 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 252461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47572671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47825132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 252461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6653587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6653587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6653587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 252461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47572671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54478719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 475105 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 1550203 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 94716224 # Total number of bytes read from memory +system.physmem.cpureqs 545524 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30406656 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 94716224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30406656 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4222 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4164 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 92954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 91941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 92050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 91689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 92209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 92061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 92149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 92666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 91875 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 92213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 92439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 92957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 92247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 91863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 92572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 91834 # Track reads on a per bank basis +system.physmem.servicedByWrQ 162 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4321 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29801 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29611 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4108 # Tr system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 659991863500 # Total gap between requests +system.physmem.totGap 635788203500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1479941 # Categorize read packet sizes +system.physmem.readPktSize::6 475105 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,18 +102,18 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4164 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4321 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1408404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2873 # Wh system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 5597502027 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 50332290027 # Sum of mem lat for all requests -system.physmem.totBusLat 5902876000 # Total cycles spent in databus access -system.physmem.totBankLat 38831912000 # Total cycles spent in bank access -system.physmem.avgQLat 3793.07 # Average queueing delay per request -system.physmem.avgBankLat 26313.89 # Average bank access latency per request +system.physmem.totQLat 2296699471 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17086173471 # Sum of mem lat for all requests +system.physmem.totBusLat 1899772000 # Total cycles spent in databus access +system.physmem.totBankLat 12889702000 # Total cycles spent in bank access +system.physmem.avgQLat 4835.74 # Average queueing delay per request +system.physmem.avgBankLat 27139.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34106.96 # Average memory access latency -system.physmem.avgRdBW 143.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.41 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 143.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.41 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 35975.21 # Average memory access latency +system.physmem.avgRdBW 47.83 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.65 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.83 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.65 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.94 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.08 # Average read queue length over time -system.physmem.avgWrQLen 14.18 # Average write queue length over time -system.physmem.readRowHits 809039 # Number of row buffer hits during reads -system.physmem.writeRowHits 36662 # Number of row buffer hits during writes -system.physmem.readRowHitRate 54.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.47 # Row buffer hit rate for writes -system.physmem.avgGap 426892.12 # Average gap between requests +system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.03 # Average read queue length over time +system.physmem.avgWrQLen 17.42 # Average write queue length over time +system.physmem.readRowHits 249227 # Number of row buffer hits during reads +system.physmem.writeRowHits 48069 # Number of row buffer hits during writes +system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.72 # Row buffer hit rate for writes +system.physmem.avgGap 1174768.44 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,577 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1319983857 # number of cpu cycles simulated +system.cpu.numCycles 1271576449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 454350981 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 358310478 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33373061 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 312072233 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 240275028 # Number of BTB hits +system.cpu.BPredUnit.lookups 450228409 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 355532784 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 33221025 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 286250905 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 237054856 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53876645 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2808673 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 374001286 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2331861224 # Number of instructions fetch has processed -system.cpu.fetch.Branches 454350981 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 294151673 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 622796021 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 170528608 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 135818762 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 24217 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 352463772 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11980006 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1269746213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.542801 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.164977 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 53630453 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2814194 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 368782120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2317566621 # Number of instructions fetch has processed +system.cpu.fetch.Branches 450228409 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 290685309 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 618187609 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 167802769 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 122950545 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 34033 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 346967374 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10833079 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1244485983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575716 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.174798 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 646995456 50.95% 50.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44687712 3.52% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 102379693 8.06% 62.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59922071 4.72% 67.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 74129472 5.84% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45582835 3.59% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31361893 2.47% 79.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30601811 2.41% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 234085270 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 626344117 50.33% 50.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 45317842 3.64% 53.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101227769 8.13% 62.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 59470859 4.78% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 73017121 5.87% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44727211 3.59% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30024154 2.41% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31448495 2.53% 81.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232908415 18.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1269746213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.344209 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.766583 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 425403268 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107718588 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 581478902 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18055452 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 137090003 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 51078179 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15137 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3127640414 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28961 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 137090003 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 461511464 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39177126 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 530700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 561763722 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69673198 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3042064401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 391 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4490697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56029467 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2572 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2999547883 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14489457877 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13880825981 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 608631896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993146442 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1006401441 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25504 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 180658895 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 975543094 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 514319343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 34765547 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38827815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2864053634 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 32821 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2484775177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 12535683 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 966091505 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2435627475 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10643 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1269746213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886378 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1244485983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.354071 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.822593 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 419135073 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95311788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 577111124 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18421558 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134506440 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 50263790 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 26327 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3103411757 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 60284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134506440 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 455352486 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27182944 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 495803 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 558181591 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68766719 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3020461835 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1786182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58542729 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2987223490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14381793689 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13781741718 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 600051971 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993152898 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 994070592 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23484 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 177920569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971527729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 505697139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 29364054 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38323451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2844663565 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34202 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2471693501 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 7154025 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 946732451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2394075214 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11217 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1244485983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.986116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 414113290 32.61% 32.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 194811826 15.34% 47.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 206120235 16.23% 64.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171548762 13.51% 77.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 130841431 10.30% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97116191 7.65% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37554058 2.96% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12317792 0.97% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5322628 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 394145382 31.67% 31.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 193214413 15.53% 47.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204405304 16.42% 63.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171173190 13.75% 77.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 129740055 10.43% 87.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 97310600 7.82% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 36398713 2.92% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12543196 1.01% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5555130 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1269746213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1244485983 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 947301 1.02% 1.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24145 0.03% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56191268 60.42% 61.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35841535 38.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 746380 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24393 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55867065 61.34% 62.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 34441237 37.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1133457764 45.62% 45.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11237396 0.45% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876496 0.28% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5506177 0.22% 46.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23536328 0.95% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838863420 33.76% 81.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 463922306 18.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1129092447 45.68% 45.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11228574 0.45% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501982 0.22% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23586280 0.95% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 837187213 33.87% 81.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 456845236 18.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2484775177 # Type of FU issued -system.cpu.iq.rate 1.882428 # Inst issue rate -system.cpu.iq.fu_busy_cnt 93004249 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.037430 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6215984950 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3740236476 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2293829225 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128851549 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 90009348 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59026271 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2510712861 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 67066565 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78532237 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2471693501 # Type of FU issued +system.cpu.iq.rate 1.943803 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91079075 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036849 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6158633993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704145010 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2281572785 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 127472092 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 87353789 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58523777 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2496546302 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66226274 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 80772254 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 344155119 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5694 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1300004 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 237323252 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340138947 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 411099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 228700241 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 137090003 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17084434 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1439762 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2864100864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 11154453 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 975543094 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 514319343 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22441 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1430096 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1300004 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 35278606 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1697024 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36975630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2406030122 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 793312488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78745055 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134506440 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8643138 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 547079 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2844711818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 10610498 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971527729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 505697139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23185 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 540297 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 411099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 34712988 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1840552 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 36553540 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2395281486 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 793221583 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 76412015 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14409 # number of nop insts executed -system.cpu.iew.exec_refs 1235149676 # number of memory reference insts executed -system.cpu.iew.exec_branches 329779468 # Number of branches executed -system.cpu.iew.exec_stores 441837188 # Number of stores executed -system.cpu.iew.exec_rate 1.822772 # Inst execution rate -system.cpu.iew.wb_sent 2378266547 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2352855496 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1358943525 # num instructions producing a value -system.cpu.iew.wb_consumers 2560958188 # num instructions consuming a value +system.cpu.iew.exec_nop 14051 # number of nop insts executed +system.cpu.iew.exec_refs 1229345389 # number of memory reference insts executed +system.cpu.iew.exec_branches 327128098 # Number of branches executed +system.cpu.iew.exec_stores 436123806 # Number of stores executed +system.cpu.iew.exec_rate 1.883710 # Inst execution rate +system.cpu.iew.wb_sent 2368179118 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2340096562 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1354502475 # num instructions producing a value +system.cpu.iew.wb_consumers 2541864992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.782488 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.530639 # average fanout of values written-back +system.cpu.iew.wb_rate 1.840311 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.532877 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 978761117 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22178 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33359188 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1132656212 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.664530 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.366367 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 959367728 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22985 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 33197953 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1109979545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.698540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.378671 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 484847147 42.81% 42.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 300235204 26.51% 69.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 89818902 7.93% 77.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 73190759 6.46% 83.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44951546 3.97% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23093029 2.04% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848859 1.40% 91.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9835568 0.87% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90835198 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 463287159 41.74% 41.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 297974077 26.85% 68.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91457957 8.24% 76.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72253905 6.51% 83.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45208298 4.07% 87.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23225084 2.09% 89.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15854658 1.43% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10141159 0.91% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90577248 8.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1132656212 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384385576 # Number of instructions committed -system.cpu.commit.committedOps 1885340328 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1109979545 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384389611 # Number of instructions committed +system.cpu.commit.committedOps 1885344363 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908384066 # Number of memory references committed -system.cpu.commit.loads 631387975 # Number of loads committed +system.cpu.commit.refs 908385680 # Number of memory references committed +system.cpu.commit.loads 631388782 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299635189 # Number of branches committed +system.cpu.commit.branches 299635996 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653702043 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705271 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90835198 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90577248 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3905904114 # The number of ROB reads -system.cpu.rob.rob_writes 5865307964 # The number of ROB writes -system.cpu.timesIdled 1232544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50237644 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384374560 # Number of Instructions Simulated -system.cpu.committedOps 1885329312 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384374560 # Number of Instructions Simulated -system.cpu.cpi 0.953488 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.953488 # CPI: Total CPI of All Threads -system.cpu.ipc 1.048781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.048781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11951457171 # number of integer regfile reads -system.cpu.int_regfile_writes 2254061534 # number of integer regfile writes -system.cpu.fp_regfile_reads 71109797 # number of floating regfile reads -system.cpu.fp_regfile_writes 50119198 # number of floating regfile writes -system.cpu.misc_regfile_reads 3727888158 # number of misc regfile reads -system.cpu.misc_regfile_writes 13774490 # number of misc regfile writes -system.cpu.icache.replacements 23076 # number of replacements -system.cpu.icache.tagsinuse 1653.132974 # Cycle average of tags in use -system.cpu.icache.total_refs 352429997 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24765 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14230.971007 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3864096043 # The number of ROB reads +system.cpu.rob.rob_writes 5823945497 # The number of ROB writes +system.cpu.timesIdled 351641 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27090466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384378595 # Number of Instructions Simulated +system.cpu.committedOps 1885333347 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384378595 # Number of Instructions Simulated +system.cpu.cpi 0.918518 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.918518 # CPI: Total CPI of All Threads +system.cpu.ipc 1.088710 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.088710 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11907054979 # number of integer regfile reads +system.cpu.int_regfile_writes 2251695031 # number of integer regfile writes +system.cpu.fp_regfile_reads 70501707 # number of floating regfile reads +system.cpu.fp_regfile_writes 50326111 # number of floating regfile writes +system.cpu.misc_regfile_reads 3707678526 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776104 # number of misc regfile writes +system.cpu.icache.replacements 23916 # number of replacements +system.cpu.icache.tagsinuse 1661.487549 # Cycle average of tags in use +system.cpu.icache.total_refs 346930644 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 25614 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13544.571094 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1653.132974 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.807194 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.807194 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 352434103 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 352434103 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 352434103 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 352434103 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 352434103 # number of overall hits -system.cpu.icache.overall_hits::total 352434103 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 29669 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 29669 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 29669 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 29669 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 29669 # number of overall misses -system.cpu.icache.overall_misses::total 29669 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 256567500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 256567500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 256567500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 256567500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 256567500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 256567500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 352463772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 352463772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 352463772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 352463772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 352463772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 352463772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8647.662543 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8647.662543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8647.662543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8647.662543 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1661.487549 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.811273 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.811273 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 346934721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 346934721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 346934721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 346934721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 346934721 # number of overall hits +system.cpu.icache.overall_hits::total 346934721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 32652 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 32652 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 32652 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 32652 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 32652 # number of overall misses +system.cpu.icache.overall_misses::total 32652 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 492196499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 492196499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 492196499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 492196499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 492196499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 492196499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 346967373 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 346967373 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 346967373 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 346967373 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 346967373 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 346967373 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15074.007687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15074.007687 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15074.007687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15074.007687 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1459 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.685714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 738 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 738 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 738 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 738 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 738 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 738 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28931 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28931 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28931 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28931 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28931 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28931 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178433000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178433000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6167.536552 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6167.536552 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2714 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2714 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2714 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2714 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2714 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2714 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29938 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 29938 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 29938 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 29938 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 29938 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 29938 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 396628999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 396628999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 396628999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 396628999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 396628999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 396628999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13248.346550 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13248.346550 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533235 # number of replacements -system.cpu.dcache.tagsinuse 4094.869938 # Cycle average of tags in use -system.cpu.dcache.total_refs 976399177 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537331 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 635.126188 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 278705000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.869938 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999724 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999724 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 700249991 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 700249991 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276118441 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276118441 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11312 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11312 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10779 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10779 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 976368432 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84515499000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84515499000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31029320000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31029320000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 296000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115544819000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115544819000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 115544819000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 115544819000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 702322482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 702322482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533079 # number of replacements +system.cpu.dcache.tagsinuse 4094.602102 # Cycle average of tags in use +system.cpu.dcache.total_refs 974126836 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 633.712385 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 342496000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.602102 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999659 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999659 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 697989238 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 697989238 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276101323 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276101323 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 12267 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 12267 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11586 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11586 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 974090561 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 974090561 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 974090561 # number of overall hits +system.cpu.dcache.overall_hits::total 974090561 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2001936 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2001936 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 834355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 834355 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2836291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2836291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2836291 # number of overall misses +system.cpu.dcache.overall_misses::total 2836291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68815075500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68815075500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39938491970 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39938491970 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 108753567470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 108753567470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 108753567470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 108753567470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 699991174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 699991174 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11322 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11322 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10779 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10779 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 979258160 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 979258160 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 979258160 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 979258160 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002951 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000883 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000883 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40779.669972 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40779.669972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37968.569705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37968.569705 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29600 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29600 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39984.669491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39984.669491 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21.500000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11586 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11586 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 976926852 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 976926852 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 976926852 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 976926852 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002860 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002860 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003013 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003013 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000163 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000163 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002903 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002903 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002903 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002903 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34374.263463 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34374.263463 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47867.504803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47867.504803 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38343.585856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38343.585856 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1801 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 752 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 85 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.016667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.847059 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108671 # number of writebacks -system.cpu.dcache.writebacks::total 108671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 607721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 607721 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 740509 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 10 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 10 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1348230 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1348230 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1348230 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2635948000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2635948000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 59174086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 59174086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 59174086500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 59174086500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002086 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002086 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 96247 # number of writebacks +system.cpu.dcache.writebacks::total 96247 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 537314 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 537314 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 757477 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1294791 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1294791 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274471 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999306 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999306 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910742 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910742 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304011 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304011 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39634.671582 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48436.566558 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48382.575123 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.198334 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.198334 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36156.080980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36156.080980 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |