diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing')
3 files changed, 287 insertions, 178 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 116b954da..1aaeea9d1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index f17e243b1..542867b6f 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:55:24 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:31:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4c3a340 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index f4aa63ff2..b6f8c26dc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.629535 # Nu sim_ticks 629535413500 # Number of ticks simulated final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111054 # Simulator instruction rate (inst/s) -host_op_rate 151240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50501117 # Simulator tick rate (ticks/s) -host_mem_usage 257896 # Number of bytes of host memory used -host_seconds 12465.77 # Real time elapsed on the host +host_inst_rate 106173 # Simulator instruction rate (inst/s) +host_op_rate 144593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48281629 # Simulator tick rate (ticks/s) +host_mem_usage 278772 # Number of bytes of host memory used +host_seconds 13038.82 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -264,14 +264,14 @@ system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # By system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation -system.physmem.totQLat 3804882250 # Total ticks spent queuing -system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3804806750 # Total ticks spent queuing +system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks -system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s @@ -303,20 +303,41 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34627840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 438247561 # Number of BP lookups -system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted +system.cpu.branchPred.lookups 438247722 # Number of BP lookups +system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups -system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits +system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -338,6 +359,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -363,94 +405,94 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 1259070828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch +system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available @@ -486,7 +528,7 @@ system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued @@ -519,17 +561,17 @@ system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Ty system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued -system.cpu.iq.rate 1.934087 # Inst issue rate +system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued +system.cpu.iq.rate 1.934086 # Inst issue rate system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -540,13 +582,13 @@ system.cpu.iew.lsq.thread0.squashedStores 208692629 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions @@ -556,43 +598,43 @@ system.cpu.iew.memOrderViolationEvents 1430281 # Nu system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12446 # number of nop insts executed -system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed +system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed system.cpu.iew.exec_branches 319532182 # Number of branches executed system.cpu.iew.exec_stores 423276586 # Number of stores executed system.cpu.iew.exec_rate 1.874346 # Inst execution rate -system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1349155886 # num instructions producing a value -system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value +system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1349155649 # num instructions producing a value +system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle +system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -605,10 +647,10 @@ system.cpu.commit.int_insts 1653698867 # Nu system.cpu.commit.function_calls 41577833 # Number of function calls committed. system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791959297 # The number of ROB reads -system.cpu.rob.rob_writes 5711929091 # The number of ROB writes +system.cpu.rob.rob_reads 3791959363 # The number of ROB reads +system.cpu.rob.rob_writes 5711929117 # The number of ROB writes system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated @@ -616,11 +658,11 @@ system.cpu.cpi 0.909490 # CP system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads -system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes +system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads +system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads +system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution @@ -743,7 +785,7 @@ system.cpu.l2cache.tags.total_refs 1110777 # To system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy @@ -788,16 +830,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2426 # system.cpu.l2cache.overall_misses::cpu.data 472563 # number of overall misses system.cpu.l2cache.overall_misses::total 474989 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746506500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30922725250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4757394750 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35503901250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35680120000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35503901250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35680120000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1464549 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses) @@ -827,16 +869,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,18 +912,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses @@ -896,24 +938,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1532970 # number of replacements system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy @@ -925,20 +967,20 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits -system.cpu.dcache.overall_hits::total 971375738 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits +system.cpu.dcache.overall_hits::total 971375795 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses @@ -949,28 +991,28 @@ system.cpu.dcache.demand_misses::cpu.data 2796744 # n system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses system.cpu.dcache.overall_misses::total 2796744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses @@ -981,16 +1023,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked @@ -1019,14 +1061,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -1035,14 +1077,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |