diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing')
3 files changed, 753 insertions, 745 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 1aaeea9d1..48782c31e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 542867b6f..8802e13a7 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:31:04 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:43:02 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x4c3a340 + 0: system.cpu.isa: ISA system set to: 0 0x5c9e4b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -1386,4 +1386,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 629535413500 because target called exit() +Exiting @ tick 634728078000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e51d34500..fbd52f02a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.628792 # Number of seconds simulated -sim_ticks 628791732500 # Number of ticks simulated -final_tick 628791732500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.634728 # Number of seconds simulated +sim_ticks 634728078000 # Number of ticks simulated +final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86286 # Simulator instruction rate (inst/s) -host_op_rate 117510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39191918 # Simulator tick rate (ticks/s) -host_mem_usage 321468 # Number of bytes of host memory used -host_seconds 16043.91 # Real time elapsed on the host +host_inst_rate 97161 # Simulator instruction rate (inst/s) +host_op_rate 132320 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44547849 # Simulator tick rate (ticks/s) +host_mem_usage 267228 # Number of bytes of host memory used +host_seconds 14248.23 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242560 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory +system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472540 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48096307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48342722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246415 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246415 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6727620 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6727620 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6727620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48096307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55070342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474962 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474992 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30374848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30397568 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4292 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29853 # Per bank write bursts -system.physmem.perBankRdBursts::1 29663 # Per bank write bursts -system.physmem.perBankRdBursts::2 29734 # Per bank write bursts -system.physmem.perBankRdBursts::3 29691 # Per bank write bursts -system.physmem.perBankRdBursts::4 29781 # Per bank write bursts -system.physmem.perBankRdBursts::5 29812 # Per bank write bursts -system.physmem.perBankRdBursts::6 29626 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29868 # Per bank write bursts +system.physmem.perBankRdBursts::1 29664 # Per bank write bursts +system.physmem.perBankRdBursts::2 29737 # Per bank write bursts +system.physmem.perBankRdBursts::3 29712 # Per bank write bursts +system.physmem.perBankRdBursts::4 29799 # Per bank write bursts +system.physmem.perBankRdBursts::5 29810 # Per bank write bursts +system.physmem.perBankRdBursts::6 29625 # Per bank write bursts system.physmem.perBankRdBursts::7 29426 # Per bank write bursts -system.physmem.perBankRdBursts::8 29463 # Per bank write bursts -system.physmem.perBankRdBursts::9 29476 # Per bank write bursts -system.physmem.perBankRdBursts::10 29540 # Per bank write bursts -system.physmem.perBankRdBursts::11 29638 # Per bank write bursts -system.physmem.perBankRdBursts::12 29686 # Per bank write bursts -system.physmem.perBankRdBursts::13 29802 # Per bank write bursts -system.physmem.perBankRdBursts::14 29621 # Per bank write bursts -system.physmem.perBankRdBursts::15 29795 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankRdBursts::8 29475 # Per bank write bursts +system.physmem.perBankRdBursts::9 29463 # Per bank write bursts +system.physmem.perBankRdBursts::10 29528 # Per bank write bursts +system.physmem.perBankRdBursts::11 29636 # Per bank write bursts +system.physmem.perBankRdBursts::12 29682 # Per bank write bursts +system.physmem.perBankRdBursts::13 29788 # Per bank write bursts +system.physmem.perBankRdBursts::14 29619 # Per bank write bursts +system.physmem.perBankRdBursts::15 29790 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::3 4147 # Per bank write bursts system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4090 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4139 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 628791712500 # Total gap between requests +system.physmem.totGap 634728009000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474962 # Read request sizes (log2) +system.physmem.readPktSize::6 474992 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -146,22 +146,22 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 194074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.290755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.832062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.398992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 73771 38.01% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 88634 45.67% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20233 10.43% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 463 0.24% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 411 0.21% 94.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 515 0.27% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 585 0.30% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 564 0.29% 95.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8898 4.58% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 194074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.655603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.114528 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 505.912792 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.491390 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.469672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863565 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 975 24.33% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 5771153000 # Total ticks spent queuing -system.physmem.totMemAccLat 14670034250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2373035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12159.86 # Average queueing delay per DRAM burst +system.physmem.totQLat 4985394000 # Total ticks spent queuing +system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30909.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.73 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 18.42 # Average write queue length when enqueuing -system.physmem.readRowHits 296657 # Number of row buffer hits during reads -system.physmem.writeRowHits 49944 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.56 # Row buffer hit rate for writes -system.physmem.avgGap 1162147.84 # Average gap between requests -system.physmem.pageHitRate 64.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 162139876750 # Time in different power states -system.physmem.memoryStateTime::REF 20996560000 # Time in different power states +system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing +system.physmem.readRowHits 298015 # Number of row buffer hits during reads +system.physmem.writeRowHits 49917 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes +system.physmem.avgGap 1173054.41 # Average gap between requests +system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states +system.physmem.memoryStateTime::REF 21194940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 445650242000 # Time in different power states +system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 55070241 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408884 # Transaction distribution -system.membus.trans_dist::ReadResp 408882 # Transaction distribution +system.membus.throughput 54558418 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408916 # Transaction distribution +system.membus.trans_dist::ReadResp 408916 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4292 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4292 # Transaction distribution -system.membus.trans_dist::ReadExReq 66078 # Transaction distribution -system.membus.trans_dist::ReadExResp 66078 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024604 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024604 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627712 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34627712 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34627712 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution +system.membus.trans_dist::ReadExReq 66076 # Transaction distribution +system.membus.trans_dist::ReadExResp 66076 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34629760 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1214449500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4441072458 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 439434227 # Number of BP lookups -system.cpu.branchPred.condPredicted 352242826 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30627071 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 250632586 # Number of BTB lookups -system.cpu.branchPred.BTBHits 230940186 # Number of BTB hits +system.cpu.branchPred.lookups 478607550 # Number of BP lookups +system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups +system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.142921 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52229993 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2805540 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -365,239 +365,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1257583466 # number of cpu cycles simulated +system.cpu.numCycles 1269456157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 355252330 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2281557009 # Number of instructions fetch has processed -system.cpu.fetch.Branches 439434227 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 283170179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601713503 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 156847289 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133155767 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11076 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 125 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 335955320 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11758504 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1216301526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.576674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.174492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed +system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614632846 50.53% 50.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42470987 3.49% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 96126752 7.90% 61.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 57281313 4.71% 66.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 72527941 5.96% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45003441 3.70% 76.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31089370 2.56% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31572340 2.60% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 225596536 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1216301526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.349427 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.814239 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405937331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105620938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561845304 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16741500 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 126156453 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44653834 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11972 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3026383079 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27573 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 126156453 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441649817 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37679339 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 449718 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540872152 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69494047 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2944559238 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4802711 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54195204 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 788 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2928884357 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14250328437 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12163279231 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 83987601 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 935744267 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20476 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 177752072 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 970380112 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 488270478 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36212412 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40741930 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792865970 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2433397099 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13404605 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 895018158 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2348989049 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6466 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1216301526 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.000653 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.872636 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 380324245 31.27% 31.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183454055 15.08% 46.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204117167 16.78% 63.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169768830 13.96% 77.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132683622 10.91% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92575300 7.61% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37909888 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12415448 1.02% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3052971 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1216301526 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714605 0.81% 0.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24383 0.03% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55145870 62.89% 63.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31799244 36.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1104322039 45.38% 45.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223967 0.46% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502004 0.23% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23392771 0.96% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838298218 34.45% 81.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442406331 18.18% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2433397099 # Type of FU issued -system.cpu.iq.rate 1.934979 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87684102 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036034 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6061689588 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3605336566 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2248845458 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122494843 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82642602 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56425705 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2457771318 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63309883 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84349734 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued +system.cpu.iq.rate 1.964874 # Inst issue rate +system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 338992931 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10163 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1428185 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 211275181 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 448 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 126156453 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15953141 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1561672 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792906296 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1415032 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 970380112 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 488270478 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 17864 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555530 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1428185 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32514856 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1483129 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33997985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2358061254 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792590559 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75335845 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12476 # number of nop insts executed -system.cpu.iew.exec_refs 1216220468 # number of memory reference insts executed -system.cpu.iew.exec_branches 319843836 # Number of branches executed -system.cpu.iew.exec_stores 423629909 # Number of stores executed -system.cpu.iew.exec_rate 1.875073 # Inst execution rate -system.cpu.iew.wb_sent 2330961284 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2305271163 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347649196 # num instructions producing a value -system.cpu.iew.wb_consumers 2523801543 # num instructions consuming a value +system.cpu.iew.exec_nop 12697 # number of nop insts executed +system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed +system.cpu.iew.exec_branches 329019811 # Number of branches executed +system.cpu.iew.exec_stores 429891953 # Number of stores executed +system.cpu.iew.exec_rate 1.909637 # Inst execution rate +system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1389701712 # num instructions producing a value +system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833096 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533976 # average fanout of values written-back +system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 907570051 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30615394 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1090145073 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.729436 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.397108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449857024 41.27% 41.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288588820 26.47% 67.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95106380 8.72% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70218402 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46473981 4.26% 87.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22183134 2.03% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15845043 1.45% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10980592 1.01% 91.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90891697 8.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1090145073 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -643,239 +644,239 @@ system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction -system.cpu.commit.bw_lim_events 90891697 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3792141440 # The number of ROB reads -system.cpu.rob.rob_writes 5711980108 # The number of ROB writes -system.cpu.timesIdled 352856 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41281940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3962036316 # The number of ROB reads +system.cpu.rob.rob_writes 6083536675 # The number of ROB writes +system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.908415 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.908415 # CPI: Total CPI of All Threads -system.cpu.ipc 1.100818 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.100818 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11756762903 # number of integer regfile reads -system.cpu.int_regfile_writes 2218718479 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads -system.cpu.fp_regfile_writes 49537143 # number of floating regfile writes -system.cpu.misc_regfile_reads 1677857394 # number of misc regfile reads +system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads +system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads +system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes +system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads +system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes +system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 169149196 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1493034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1493032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52723 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3231718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1549696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104535104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106084800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106084800 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 274816 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929401499 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 43182746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371256268 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 22529 # number of replacements -system.cpu.icache.tags.tagsinuse 1644.627190 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 335917634 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24213 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13873.441292 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 24993 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1644.627190 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.803041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.803041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1684 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1552 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 671939144 # Number of tag accesses -system.cpu.icache.tags.data_accesses 671939144 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 335924107 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 335924107 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 335924107 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 335924107 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 335924107 # number of overall hits -system.cpu.icache.overall_hits::total 335924107 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31211 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31211 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31211 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31211 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31211 # number of overall misses -system.cpu.icache.overall_misses::total 31211 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 530208992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 530208992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 530208992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 530208992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 530208992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 530208992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 335955318 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 335955318 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 335955318 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 335955318 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 335955318 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 335955318 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16987.888629 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16987.888629 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16987.888629 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16987.888629 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16987.888629 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16987.888629 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1881 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.825684 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 716098748 # Number of tag accesses +system.cpu.icache.tags.data_accesses 716098748 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 357999320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 357999320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 357999320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 357999320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 357999320 # number of overall hits +system.cpu.icache.overall_hits::total 357999320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34446 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34446 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34446 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34446 # number of overall misses +system.cpu.icache.overall_misses::total 34446 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 570147243 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 570147243 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 570147243 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 570147243 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 570147243 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 570147243 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 358033766 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 358033766 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 358033766 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 358033766 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 358033766 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 358033766 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16551.914388 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16551.914388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16551.914388 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1683 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.781250 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60.107143 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2702 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2702 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2702 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2702 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2702 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2702 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28509 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28509 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28509 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28509 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28509 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28509 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424344751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 424344751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424344751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 424344751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424344751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 424344751 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14884.589112 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14884.589112 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14884.589112 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14884.589112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14884.589112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14884.589112 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3230 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3230 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3230 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3230 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 454582253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 454582253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 454582253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14562.476070 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29018678000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29161730750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143052750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29018678000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29161730750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277538 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999302 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999302 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911182 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911182 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307434 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304217 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100021 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307434 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304217 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59063.893476 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61738.279347 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61722.437782 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2438 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406478 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408916 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4530 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4530 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66076 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66076 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472554 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 472554 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145569750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24308392500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24453962250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45304530 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45304530 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3923643500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3923643500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145569750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28232036000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28377605750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145569750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28232036000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28377605750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277540 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999338 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999338 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.303748 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.303748 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59708.675144 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59802.480085 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59801.920810 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.621690 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.621690 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59063.893476 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61409.992805 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61398.029211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59063.893476 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61409.992805 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61398.029211 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59380.766088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59380.766088 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532947 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.376885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 969983510 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1537043 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 631.071161 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 400583250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376885 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1532989 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.399228 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 981387634 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1537085 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 638.473236 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 399634250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.399228 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999609 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999609 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 978 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1947074947 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1947074947 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 693859178 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693859178 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276090749 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276090749 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10001 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10001 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1969885597 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1969885597 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 705264252 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 705264252 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276089331 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276089331 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969949927 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969949927 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969949927 # number of overall hits -system.cpu.dcache.overall_hits::total 969949927 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1954107 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1954107 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 844929 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 844929 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 981353583 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 981353583 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 981353583 # number of overall hits +system.cpu.dcache.overall_hits::total 981353583 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1954339 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1954339 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 846347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 846347 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2799036 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2799036 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2799036 # number of overall misses -system.cpu.dcache.overall_misses::total 2799036 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79576585056 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79576585056 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58758638704 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58758638704 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 210750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 210750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 138335223760 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 138335223760 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 138335223760 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 138335223760 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695813285 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695813285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses +system.cpu.dcache.overall_misses::total 2800686 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10004 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10004 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972748963 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972748963 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972748963 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972748963 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003051 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003051 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002877 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002877 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002877 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002877 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40722.736808 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40722.736808 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69542.693770 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69542.693770 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49422.452502 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49422.452502 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49422.452502 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2414 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 988 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.703704 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.739130 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96318 # number of writebacks -system.cpu.dcache.writebacks::total 96318 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489582 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 768115 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 768115 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96290 # number of writebacks +system.cpu.dcache.writebacks::total 96290 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489763 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489763 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769304 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769304 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1257697 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1257697 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1257697 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1257697 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464525 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464525 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541339 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541339 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541339 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541339 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42200288024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42200288024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993959708 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993959708 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47194247732 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47194247732 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47194247732 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47194247732 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28815.000102 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28815.000102 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65013.665582 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65013.665582 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30618.992793 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30618.992793 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1259067 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1259067 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1259067 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1259067 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464576 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464576 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77043 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77043 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541619 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541619 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41415183522 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41415183522 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4998292971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4998292971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46413476493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46413476493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46413476493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46413476493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002071 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002071 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001566 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001566 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |