diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/40.perlbmk/ref/arm/linux/o3-timing | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1645 |
1 files changed, 830 insertions, 815 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index fbd52f02a..e42758d84 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.634728 # Number of seconds simulated -sim_ticks 634728078000 # Number of ticks simulated -final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.297198 # Number of seconds simulated +sim_ticks 297198275500 # Number of ticks simulated +final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97161 # Simulator instruction rate (inst/s) -host_op_rate 132320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44547849 # Simulator tick rate (ticks/s) -host_mem_usage 267228 # Number of bytes of host memory used -host_seconds 14248.23 # Real time elapsed on the host -sim_insts 1384370590 # Number of instructions simulated -sim_ops 1885325342 # Number of ops (including micro ops) simulated +host_inst_rate 98901 # Simulator instruction rate (inst/s) +host_op_rate 121761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45880544 # Simulator tick rate (ticks/s) +host_mem_usage 261988 # Number of bytes of host memory used +host_seconds 6477.65 # Real time elapsed on the host +sim_insts 640649298 # Number of instructions simulated +sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory -system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory +system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474992 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62035569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290424 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290424 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18565376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18587136 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29868 # Per bank write bursts -system.physmem.perBankRdBursts::1 29664 # Per bank write bursts -system.physmem.perBankRdBursts::2 29737 # Per bank write bursts -system.physmem.perBankRdBursts::3 29712 # Per bank write bursts -system.physmem.perBankRdBursts::4 29799 # Per bank write bursts -system.physmem.perBankRdBursts::5 29810 # Per bank write bursts -system.physmem.perBankRdBursts::6 29625 # Per bank write bursts -system.physmem.perBankRdBursts::7 29426 # Per bank write bursts -system.physmem.perBankRdBursts::8 29475 # Per bank write bursts -system.physmem.perBankRdBursts::9 29463 # Per bank write bursts -system.physmem.perBankRdBursts::10 29528 # Per bank write bursts -system.physmem.perBankRdBursts::11 29636 # Per bank write bursts -system.physmem.perBankRdBursts::12 29682 # Per bank write bursts -system.physmem.perBankRdBursts::13 29788 # Per bank write bursts -system.physmem.perBankRdBursts::14 29619 # Per bank write bursts -system.physmem.perBankRdBursts::15 29790 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18318 # Per bank write bursts +system.physmem.perBankRdBursts::1 18131 # Per bank write bursts +system.physmem.perBankRdBursts::2 18196 # Per bank write bursts +system.physmem.perBankRdBursts::3 18163 # Per bank write bursts +system.physmem.perBankRdBursts::4 18256 # Per bank write bursts +system.physmem.perBankRdBursts::5 18279 # Per bank write bursts +system.physmem.perBankRdBursts::6 18091 # Per bank write bursts +system.physmem.perBankRdBursts::7 17906 # Per bank write bursts +system.physmem.perBankRdBursts::8 17946 # Per bank write bursts +system.physmem.perBankRdBursts::9 17953 # Per bank write bursts +system.physmem.perBankRdBursts::10 18007 # Per bank write bursts +system.physmem.perBankRdBursts::11 18104 # Per bank write bursts +system.physmem.perBankRdBursts::12 18147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18252 # Per bank write bursts +system.physmem.perBankRdBursts::14 18085 # Per bank write bursts +system.physmem.perBankRdBursts::15 18250 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4171 # Per bank write bursts +system.physmem.perBankWrBursts::6 4170 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4090 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4091 # Per bank write bursts system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::15 4139 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 634728009000 # Total gap between requests +system.physmem.totGap 297198223500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474992 # Read request sizes (log2) +system.physmem.readPktSize::6 290424 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 235690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49717 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 106390 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 4985394000 # Total ticks spent queuing -system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads +system.physmem.totQLat 3531270750 # Total ticks spent queuing +system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.60 # Data bus utilization in percentage +system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing -system.physmem.readRowHits 298015 # Number of row buffer hits during reads -system.physmem.writeRowHits 49917 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes -system.physmem.avgGap 1173054.41 # Average gap between requests -system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states -system.physmem.memoryStateTime::REF 21194940000 # Time in different power states +system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing +system.physmem.readRowHits 199840 # Number of row buffer hits during reads +system.physmem.writeRowHits 49907 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes +system.physmem.avgGap 833604.16 # Average gap between requests +system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states +system.physmem.memoryStateTime::REF 9923940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states +system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54558418 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408916 # Transaction distribution -system.membus.trans_dist::ReadResp 408916 # Transaction distribution +system.membus.throughput 76774820 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224345 # Transaction distribution +system.membus.trans_dist::ReadResp 224344 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution -system.membus.trans_dist::ReadExReq 66076 # Transaction distribution -system.membus.trans_dist::ReadExResp 66076 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34629760 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution +system.membus.trans_dist::ReadExReq 66079 # Transaction distribution +system.membus.trans_dist::ReadExResp 66079 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22817344 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 478607550 # Number of BP lookups -system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups -system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits +system.cpu.branchPred.lookups 271863224 # Number of BP lookups +system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups +system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -364,519 +364,518 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1269456157 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 594396552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed -system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed +system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued -system.cpu.iq.rate 1.964874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued +system.cpu.iq.rate 1.934083 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12697 # number of nop insts executed -system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed -system.cpu.iew.exec_branches 329019811 # Number of branches executed -system.cpu.iew.exec_stores 429891953 # Number of stores executed -system.cpu.iew.exec_rate 1.909637 # Inst execution rate -system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1389701712 # num instructions producing a value -system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value +system.cpu.iew.exec_nop 633128 # number of nop insts executed +system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed +system.cpu.iew.exec_branches 162537737 # Number of branches executed +system.cpu.iew.exec_stores 207479483 # Number of stores executed +system.cpu.iew.exec_rate 1.878131 # Inst execution rate +system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back +system.cpu.iew.wb_producers 606518919 # num instructions producing a value +system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back +system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384381606 # Number of instructions committed -system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle +system.cpu.commit.committedInsts 640654410 # Number of instructions committed +system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908382478 # Number of memory references committed -system.cpu.commit.loads 631387181 # Number of loads committed -system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 298259106 # Number of branches committed -system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. -system.cpu.commit.function_calls 41577833 # Number of function calls committed. +system.cpu.commit.refs 381221434 # Number of memory references committed +system.cpu.commit.loads 252240938 # Number of loads committed +system.cpu.commit.membars 5740 # Number of memory barriers committed +system.cpu.commit.branches 137364859 # Number of branches committed +system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. +system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. +system.cpu.commit.function_calls 19275340 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 930022484 49.33% 49.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 11168279 0.59% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 1375288 0.07% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 6876469 0.36% 50.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 5501172 0.29% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 22010188 1.17% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 631387181 33.49% 85.31% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction -system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction +system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3962036316 # The number of ROB reads -system.cpu.rob.rob_writes 6083536675 # The number of ROB writes -system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384370590 # Number of Instructions Simulated -system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads -system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads -system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads -system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes -system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads -system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1926179188 # The number of ROB reads +system.cpu.rob.rob_writes 3042778169 # The number of ROB writes +system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 640649298 # Number of Instructions Simulated +system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads +system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads +system.cpu.int_regfile_writes 646986163 # number of integer regfile writes +system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads +system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes +system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads +system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes +system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads +system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 24993 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10545 # number of replacements +system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.825684 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 716098748 # Number of tag accesses -system.cpu.icache.tags.data_accesses 716098748 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 357999320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 357999320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 357999320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 357999320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 357999320 # number of overall hits -system.cpu.icache.overall_hits::total 357999320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34446 # number of overall misses -system.cpu.icache.overall_misses::total 34446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 570147243 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 570147243 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 570147243 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 570147243 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 358033766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 358033766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 358033766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 358033766 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16551.914388 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16551.914388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16551.914388 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1683 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1626.781544 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.794327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.794327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1664 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1549 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 415715422 # Number of tag accesses +system.cpu.icache.tags.data_accesses 415715422 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 207833630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 207833630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 207833630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 207833630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 207833630 # number of overall hits +system.cpu.icache.overall_hits::total 207833630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16808 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16808 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16808 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16808 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16808 # number of overall misses +system.cpu.icache.overall_misses::total 16808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373718245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373718245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373718245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373718245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373718245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373718245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 207850438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 207850438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 207850438 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 207850438 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 207850438 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 207850438 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000081 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000081 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000081 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000081 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000081 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000081 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22234.545752 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22234.545752 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1690 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60.107143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,201 +887,217 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.310557 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308569 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998716 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998716 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953370 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953370 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.364689 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192204 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2364 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 451 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1969885597 # 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number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses -system.cpu.dcache.overall_misses::total 2800686 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked +system.cpu.dcache.demand_misses::cpu.data 2612788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2612788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2612944 # number of overall misses +system.cpu.dcache.overall_misses::total 2612944 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 134694562447 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 134694562447 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 458866051 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 458866051 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 458870112 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 458870112 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005694 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005694 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005694 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51552.044195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51548.966395 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3326 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.194444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96290 # number of writebacks -system.cpu.dcache.writebacks::total 96290 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489763 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489763 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769304 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769304 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 91367 # number of writebacks +system.cpu.dcache.writebacks::total 91367 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881385 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 881385 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 945064 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 945064 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1259067 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1259067 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1259067 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1259067 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464576 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464576 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77043 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77043 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541619 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541619 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41415183522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41415183522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4998292971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4998292971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46413476493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46413476493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46413476493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46413476493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002071 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002071 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001566 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001566 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1826449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1826449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1826449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1826449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 714700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 714700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71639 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71639 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 786486 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 786486 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |