diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt | 516 |
1 files changed, 258 insertions, 258 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index c1630ee45..b1e10c075 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.395727 # Number of seconds simulated -sim_ticks 395726778500 # Number of ticks simulated -final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1825974 # Simulator instruction rate (inst/s) -host_op_rate 2248015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127888505 # Simulator tick rate (ticks/s) -host_mem_usage 268260 # Number of bytes of host memory used -host_seconds 350.86 # Real time elapsed on the host -sim_insts 640654411 # Number of instructions simulated -sim_ops 788730070 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory -system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory -system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory -system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 791453558 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 640654411 # Number of instructions committed -system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction -system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 893703778 # Transaction distribution -system.membus.trans_dist::ReadResp 893709517 # Transaction distribution -system.membus.trans_dist::WriteReq 128951477 # Transaction distribution -system.membus.trans_dist::WriteResp 128951477 # Transaction distribution -system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution -system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1022670353 # Request fanout histogram +sim_seconds 0.395727 +sim_ticks 395726778500 +final_tick 395726778500 +sim_freq 1000000000000 +host_inst_rate 761557 +host_op_rate 937577 +host_tick_rate 470407263 +host_mem_usage 279508 +host_seconds 841.24 +sim_insts 640654411 +sim_ops 788730070 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.physmem.bytes_read::cpu.inst 2573511596 +system.physmem.bytes_read::cpu.data 1144718516 +system.physmem.bytes_read::total 3718230112 +system.physmem.bytes_inst_read::cpu.inst 2573511596 +system.physmem.bytes_inst_read::total 2573511596 +system.physmem.bytes_written::cpu.data 523317413 +system.physmem.bytes_written::total 523317413 +system.physmem.num_reads::cpu.inst 643377899 +system.physmem.num_reads::cpu.data 250335238 +system.physmem.num_reads::total 893713137 +system.physmem.num_writes::cpu.data 128957216 +system.physmem.num_writes::total 128957216 +system.physmem.bw_read::cpu.inst 6503253598 +system.physmem.bw_read::cpu.data 2892699151 +system.physmem.bw_read::total 9395952748 +system.physmem.bw_inst_read::cpu.inst 6503253598 +system.physmem.bw_inst_read::total 6503253598 +system.physmem.bw_write::cpu.data 1322421027 +system.physmem.bw_write::total 1322421027 +system.physmem.bw_total::cpu.inst 6503253598 +system.physmem.bw_total::cpu.data 4215120178 +system.physmem.bw_total::total 10718373776 +system.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 673 +system.cpu.pwrStateResidencyTicks::ON 395726778500 +system.cpu.numCycles 791453558 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 640654411 +system.cpu.committedOps 788730070 +system.cpu.num_int_alu_accesses 682251400 +system.cpu.num_fp_alu_accesses 24239771 +system.cpu.num_func_calls 37261296 +system.cpu.num_conditional_control_insts 91575866 +system.cpu.num_int_insts 682251400 +system.cpu.num_fp_insts 24239771 +system.cpu.num_int_register_reads 1268495038 +system.cpu.num_int_register_writes 468423268 +system.cpu.num_fp_register_reads 28064643 +system.cpu.num_fp_register_writes 21684311 +system.cpu.num_cc_register_reads 2369173294 +system.cpu.num_cc_register_writes 351919006 +system.cpu.num_mem_refs 381221435 +system.cpu.num_load_insts 252240938 +system.cpu.num_store_insts 128980497 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 791453558 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 137364860 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% +system.cpu.op_class::IntMult 5173441 0.66% 49.56% +system.cpu.op_class::IntDiv 0 0.00% 49.56% +system.cpu.op_class::FloatAdd 0 0.00% 49.56% +system.cpu.op_class::FloatCmp 0 0.00% 49.56% +system.cpu.op_class::FloatCvt 0 0.00% 49.56% +system.cpu.op_class::FloatMult 0 0.00% 49.56% +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% +system.cpu.op_class::FloatDiv 0 0.00% 49.56% +system.cpu.op_class::FloatMisc 0 0.00% 49.56% +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdAdd 0 0.00% 49.56% +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% +system.cpu.op_class::SimdAlu 0 0.00% 49.56% +system.cpu.op_class::SimdCmp 0 0.00% 49.56% +system.cpu.op_class::SimdCvt 0 0.00% 49.56% +system.cpu.op_class::SimdMisc 0 0.00% 49.56% +system.cpu.op_class::SimdMult 0 0.00% 49.56% +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% +system.cpu.op_class::SimdShift 0 0.00% 49.56% +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% +system.cpu.op_class::MemRead 245222568 31.09% 82.76% +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 788730744 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.membus.trans_dist::ReadReq 893703778 +system.membus.trans_dist::ReadResp 893709517 +system.membus.trans_dist::WriteReq 128951477 +system.membus.trans_dist::WriteResp 128951477 +system.membus.trans_dist::SoftPFReq 3620 +system.membus.trans_dist::SoftPFResp 3620 +system.membus.trans_dist::LoadLockedReq 5739 +system.membus.trans_dist::StoreCondReq 5739 +system.membus.trans_dist::StoreCondResp 5739 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 +system.membus.pkt_count::total 2045340706 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 +system.membus.pkt_size::total 4241547525 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1022670353 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1022670353 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1022670353 ---------- End Simulation Statistics ---------- |