diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 848 |
1 files changed, 436 insertions, 412 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index baba5d53b..d4c7242b6 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.326119 # Number of seconds simulated -sim_ticks 2326118592000 # Number of ticks simulated -final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043695 # Number of seconds simulated +sim_ticks 1043695084000 # Number of ticks simulated +final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 706219 # Simulator instruction rate (inst/s) -host_op_rate 958037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1189016431 # Simulator tick rate (ticks/s) -host_mem_usage 318376 # Number of bytes of host memory used -host_seconds 1956.34 # Real time elapsed on the host -sim_insts 1381604339 # Number of instructions simulated -sim_ops 1874244941 # Number of ops (including micro ops) simulated +host_inst_rate 520727 # Simulator instruction rate (inst/s) +host_op_rate 639745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850028397 # Simulator tick rate (ticks/s) +host_mem_usage 259968 # Number of bytes of host memory used +host_seconds 1227.84 # Real time elapsed on the host +sim_insts 639366786 # Number of instructions simulated +sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory -system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 14864384 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408063 # Transaction distribution -system.membus.trans_dist::ReadResp 408063 # Transaction distribution -system.membus.trans_dist::Writeback 66099 # Transaction distribution +system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory +system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21818480 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34576320 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22771840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -137,117 +137,119 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4652237184 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 2087390168 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1381604339 # Number of instructions committed -system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698868 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382479 # number of memory refs -system.cpu.num_load_insts 631387181 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.committedInsts 639366786 # Number of instructions committed +system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4652237184 # Number of busy cycles +system.cpu.num_busy_cycles 2087390168 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 298259106 # Number of branches fetched +system.cpu.Branches 137364859 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction -system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction -system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1885337770 # Class of executed instruction -system.cpu.icache.tags.replacements 18364 # number of replacements -system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. +system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.icache.tags.replacements 8769 # number of replacements +system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits -system.cpu.icache.overall_hits::total 1390251699 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses -system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits +system.cpu.icache.overall_hits::total 643367691 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses +system.cpu.icache.overall_misses::total 10208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 643377899 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,60 +520,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks -system.cpu.dcache.writebacks::total 96257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks +system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) +system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |