diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 1364 |
1 files changed, 682 insertions, 682 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e6b9bff19..be07be0d5 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,686 +1,686 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.046047 # Number of seconds simulated -sim_ticks 1046047111500 # Number of ticks simulated -final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1255251 # Simulator instruction rate (inst/s) -host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2053674689 # Simulator tick rate (ticks/s) -host_mem_usage 277480 # Number of bytes of host memory used -host_seconds 509.35 # Real time elapsed on the host -sim_insts 639366787 # Number of instructions simulated -sim_ops 785501035 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory -system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2092094223 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 639366787 # Number of instructions committed -system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1272307653 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction -system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits -system.cpu.dcache.overall_hits::total 378498833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses -system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 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number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency 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-system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits -system.cpu.icache.overall_hits::total 643367692 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses -system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 8769 # number of writebacks -system.cpu.icache.writebacks::total 8769 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses 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Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 257791 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits -system.cpu.l2cache.overall_hits::total 501975 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses -system.cpu.l2cache.overall_misses::total 290375 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks -system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257791 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224282 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190103 # Transaction distribution -system.membus.trans_dist::ReadExReq 66093 # Transaction distribution -system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 290376 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 290376 # Request fanout histogram -system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 1.046047 +sim_ticks 1046047111500 +final_tick 1046047111500 +sim_freq 1000000000000 +host_inst_rate 550252 +host_op_rate 676018 +host_tick_rate 900249421 +host_mem_usage 289500 +host_seconds 1161.95 +sim_insts 639366787 +sim_ops 785501035 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.physmem.bytes_read::cpu.inst 112576 +system.physmem.bytes_read::cpu.data 18471424 +system.physmem.bytes_read::total 18584000 +system.physmem.bytes_inst_read::cpu.inst 112576 +system.physmem.bytes_inst_read::total 112576 +system.physmem.bytes_written::writebacks 4230272 +system.physmem.bytes_written::total 4230272 +system.physmem.num_reads::cpu.inst 1759 +system.physmem.num_reads::cpu.data 288616 +system.physmem.num_reads::total 290375 +system.physmem.num_writes::writebacks 66098 +system.physmem.num_writes::total 66098 +system.physmem.bw_read::cpu.inst 107620 +system.physmem.bw_read::cpu.data 17658310 +system.physmem.bw_read::total 17765930 +system.physmem.bw_inst_read::cpu.inst 107620 +system.physmem.bw_inst_read::total 107620 +system.physmem.bw_write::writebacks 4044055 +system.physmem.bw_write::total 4044055 +system.physmem.bw_total::writebacks 4044055 +system.physmem.bw_total::cpu.inst 107620 +system.physmem.bw_total::cpu.data 17658310 +system.physmem.bw_total::total 21809985 +system.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 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