stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 41 insertions, 5 deletions

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index dc10302b1..6e9e09ef8 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.326119                       # Nu
 sim_ticks                                2326118592000                       # Number of ticks simulated
 final_tick                               2326118592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 664911                       # Simulator instruction rate (inst/s)
-host_op_rate                                   901999                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1119467924                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296296                       # Number of bytes of host memory used
-host_seconds                                  2077.88                       # Real time elapsed on the host
+host_inst_rate                                 575384                       # Simulator instruction rate (inst/s)
+host_op_rate                                   780549                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              968736790                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250996                       # Number of bytes of host memory used
+host_seconds                                  2401.19                       # Real time elapsed on the host
 sim_insts                                  1381604339                       # Number of instructions simulated
 sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            113472                       # Number of bytes read from this memory
@@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks           1818624                       # To
 system.physmem.bw_total::cpu.inst               48782                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            12996978                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               14864384                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     14864384                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              408063                       # Transaction distribution
+system.membus.trans_dist::ReadResp             408063                       # Transaction distribution
+system.membus.trans_dist::Writeback             66099                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66093                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66093                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side      1014411                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count                       1014411                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side     34576320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size                   34576320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               34576320                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          1069047000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         4267404000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                45389617                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1480676                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1480676                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        96257                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        72780                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        72780                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side        39606                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side      3163563                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                  3203169                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side      1267392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side    104314240                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size             105581632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         105581632                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      921113500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      29704500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2300479500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------