stats: Update stats for unified cache configuration

This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.

1 files changed, 178 insertions, 178 deletions

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 1b9ad306d..ac5d108eb 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.368273                       # Number of seconds simulated
-sim_ticks                                2368273403000                       # Number of ticks simulated
-final_tick                               2368273403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.326119                       # Number of seconds simulated
+sim_ticks                                2326118592000                       # Number of ticks simulated
+final_tick                               2326118592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 821983                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1115078                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1408999350                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241788                       # Number of bytes of host memory used
-host_seconds                                  1680.82                       # Real time elapsed on the host
+host_inst_rate                                 541548                       # Simulator instruction rate (inst/s)
+host_op_rate                                   734649                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              911769830                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240408                       # Number of bytes of host memory used
+host_seconds                                  2551.21                       # Real time elapsed on the host
 sim_insts                                  1381604339                       # Number of instructions simulated
 sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            144448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          94437440                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             94581888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       144448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          144448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            113472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          30232512                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30345984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       113472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          113472                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230336                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230336                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2257                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1475585                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1477842                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               1773                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             472383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                474156                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                60993                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39876072                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                39937065                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           60993                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              60993                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1786253                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1786253                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1786253                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               60993                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39876072                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41723318                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                48782                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12996978                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13045760                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           48782                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              48782                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1818624                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1818624                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1818624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               48782                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12996978                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               14864384                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,7 +77,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       4736546806                       # number of cpu cycles simulated
+system.cpu.numCycles                       4652237184                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1381604339                       # Number of instructions committed
@@ -96,18 +96,18 @@ system.cpu.num_mem_refs                     908382479                       # nu
 system.cpu.num_load_insts                   631387181                       # Number of load instructions
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4736546806                       # Number of busy cycles
+system.cpu.num_busy_cycles                 4652237184                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  18364                       # number of replacements
-system.cpu.icache.tagsinuse               1392.329214                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1392.317060                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1390251699                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               70204.095289                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1392.329214                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.679848                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.679848                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1392.317060                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.679842                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.679842                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1390251699                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1390251699                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1390251699                       # number of demand (read+write) hits
@@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst        19803                       # n
 system.cpu.icache.demand_misses::total          19803                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        19803                       # number of overall misses
 system.cpu.icache.overall_misses::total         19803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    352238000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    352238000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    352238000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    352238000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    352238000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    352238000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    331911000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    331911000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    331911000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    331911000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    331911000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    331911000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1390271502                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1390271502                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1390271502                       # number of demand (read+write) accesses
@@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000014
 system.cpu.icache.demand_miss_rate::total     0.000014                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000014                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000014                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17787.102964                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17787.102964                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16760.642327                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16760.642327                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        19803
 system.cpu.icache.demand_mshr_misses::total        19803                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        19803                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        19803                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312632000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    312632000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312632000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    312632000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312632000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    312632000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    292305000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    292305000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    292305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    292305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    292305000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    292305000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000014                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000014                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1529557                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.965929                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.947189                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                895757408                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 584.067848                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              991199000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.965929                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999748                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999748                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    4094.947189                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999743                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999743                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    618874540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       618874540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits
@@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data      1533653                       # n
 system.cpu.dcache.demand_misses::total        1533653                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1533653                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1533653                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  78190013000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  78190013000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  36055529000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36055529000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data   3722046000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total   3722046000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  81912059000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  81912059000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  81912059000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  81912059000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39777575000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39777575000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39777575000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39777575000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    620335413                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    620335413                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.001709
 system.cpu.dcache.demand_miss_rate::total     0.001709                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.001709                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.001709                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53409.773267                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53409.773267                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53409.773267                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25936.489545                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25936.489545                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       109047                       # number of writebacks
-system.cpu.dcache.writebacks::total            109047                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        96257                       # number of writebacks
+system.cpu.dcache.writebacks::total             96257                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460873                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1460873                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        72780                       # number of WriteReq MSHR misses
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1533653
 system.cpu.dcache.demand_mshr_misses::total      1533653                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1533653                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1533653                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75268267000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75268267000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33133783000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33133783000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576486000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576486000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78844753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  78844753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78844753000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  78844753000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36710269000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  36710269000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36710269000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36710269000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002355                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002355                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000263                       # mshr miss rate for WriteReq accesses
@@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001709
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001709                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               1478696                       # number of replacements
-system.cpu.l2cache.tagsinuse             32690.092056                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   77413                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               1511439                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.051218                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                441378                       # number of replacements
+system.cpu.l2cache.tagsinuse             32692.891822                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1102614                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                474121                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.325596                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  3194.112587                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     32.917167                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  29463.062302                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.097477                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001005                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.899141                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.997622                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        17546                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        51381                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          68927                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       109047                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       109047                       # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks  1298.141733                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     30.233408                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  31364.516681                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.039616                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000923                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.957169                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.997708                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        18030                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1054583                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1072613                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        96257                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        96257                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         6687                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         6687                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        17546                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        58068                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           75614                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        17546                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        58068                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          75614                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2257                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1409492                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1411749                       # number of ReadReq misses
+system.cpu.l2cache.demand_hits::cpu.inst        18030                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1061270                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1079300                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        18030                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1061270                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1079300                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1773                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       406290                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       408063                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66093                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66093                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2257                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1475585                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1477842                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2257                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1475585                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1477842                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117369000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73293584000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  73410953000                       # number of ReadReq miss cycles
+system.cpu.l2cache.demand_misses::cpu.inst         1773                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       472383                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        474156                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1773                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       472383                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       474156                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     92202000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  21127080000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  21219282000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3436836000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total   3436836000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    117369000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  76730420000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  76847789000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    117369000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  76730420000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  76847789000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     92202000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  24563916000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  24656118000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     92202000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  24563916000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  24656118000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        19803                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data      1460873                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total      1480676                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       109047                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       109047                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        96257                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        96257                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        72780                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        72780                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        19803                       # number of demand (read+write) accesses
@@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total      1553456                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst        19803                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1533653                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      1553456                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113973                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.964829                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.953449                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.089532                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278115                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.275592                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.908120                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.908120                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113973                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.962137                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.951325                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113973                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.962137                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.951325                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.215330                       # average ReadReq miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.089532                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.308012                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.305227                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.089532                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.308012                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.305227                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.384095                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.003542                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.014704                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.215330                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.384095                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52000.003383                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.215330                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000.012654                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.384095                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52000.003383                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000.012654                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -378,50 +378,50 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2257                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1409492                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1411749                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1773                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406290                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       408063                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2257                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1475585                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1477842                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2257                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1475585                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1477842                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     90285000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56379680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56469965000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1773                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1773                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       472383                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       474156                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     70926000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  16251600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  16322526000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2643720000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2643720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     90285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59023400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  59113685000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     90285000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59023400000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  59113685000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.964829                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.953449                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     70926000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  18895320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  18966246000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     70926000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  18895320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  18966246000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.089532                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278115                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.275592                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.908120                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.908120                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.962137                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.951325                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.962137                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.951325                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.089532                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.308012                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.305227                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.089532                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.308012                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.305227                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------