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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt')
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt226
1 files changed, 113 insertions, 113 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index ac5d108eb..dc10302b1 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 541548 # Simulator instruction rate (inst/s)
-host_op_rate 734649 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 911769830 # Simulator tick rate (ticks/s)
-host_mem_usage 240408 # Number of bytes of host memory used
-host_seconds 2551.21 # Real time elapsed on the host
+host_inst_rate 664911 # Simulator instruction rate (inst/s)
+host_op_rate 901999 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1119467924 # Simulator tick rate (ticks/s)
+host_mem_usage 296296 # Number of bytes of host memory used
+host_seconds 2077.88 # Real time elapsed on the host
sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
@@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1529557 # number of replacements
-system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use
-system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits
-system.cpu.dcache.overall_hits::total 895737438 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
-system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks
-system.cpu.dcache.writebacks::total 96257 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 441378 # number of replacements
system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks.
@@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1529557 # number of replacements
+system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use
+system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits
+system.cpu.dcache.overall_hits::total 895737438 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
+system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks
+system.cpu.dcache.writebacks::total 96257 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------