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authorAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2012-02-12 16:07:43 -0600
commit4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch)
treec6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
parent542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff)
downloadgem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt')
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt398
1 files changed, 244 insertions, 154 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 117215dc5..70fd39037 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 2.369902 # Nu
sim_ticks 2369901960000 # Number of ticks simulated
final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1407810 # Simulator instruction rate (inst/s)
-host_tick_rate 1780114775 # Simulator tick rate (ticks/s)
-host_mem_usage 224180 # Number of bytes of host memory used
-host_seconds 1331.32 # Real time elapsed on the host
-sim_insts 1874244950 # Number of instructions simulated
+host_inst_rate 1307856 # Simulator instruction rate (inst/s)
+host_op_rate 1774200 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2243399723 # Simulator tick rate (ticks/s)
+host_mem_usage 226844 # Number of bytes of host memory used
+host_seconds 1056.39 # Real time elapsed on the host
+sim_insts 1381604347 # Number of instructions simulated
+sim_ops 1874244950 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94696320 # Number of bytes read from this memory
system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1411 # Nu
system.cpu.numCycles 4739803920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1874244950 # Number of instructions executed
+system.cpu.committedInsts 1381604347 # Number of instructions committed
+system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs 1390251708 # To
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits
-system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1390251708 # number of overall hits
-system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses
-system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 19803 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1390251708 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1390251708 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1390251708 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1390251708 # number of overall hits
+system.cpu.icache.overall_hits::total 1390251708 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses
+system.cpu.icache.overall_misses::total 19803 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 372036000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 372036000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 372036000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1390271511 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1390271511 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1390271511 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 312627000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312627000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 312627000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312627000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 312627000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1529557 # number of replacements
system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 895757409 # To
system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999746 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 895737439 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses
-system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 1533653 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4094.960333 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 618874541 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 618874541 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 895737439 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 895737439 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 895737439 # number of overall hits
+system.cpu.dcache.overall_hits::total 895737439 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
+system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 79725982000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 79725982000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794826000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 3794826000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 83520808000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 83520808000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 83520808000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 83520808000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 620335414 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 620335414 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 897271092 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 897271092 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 107259 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 3576486000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 107259 # number of writebacks
+system.cpu.dcache.writebacks::total 107259 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75343363000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 75343363000 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1478755 # number of replacements
system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 75453 # To
system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.881757 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 6687 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 73826 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 66093 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 1479630 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3436836000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.908120 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 3041.423322 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 32.598415 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 28860.822381 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.092817 # Average percentage of cache occupancy
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+system.cpu.l2cache.occ_percent::cpu.data 0.880762 # Average percentage of cache occupancy
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 66099 # number of writebacks
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-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------