Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 117 insertions, 117 deletions

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 06a14cc7a..1b9ad306d 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.369932                       # Number of seconds simulated
-sim_ticks                                2369931974000                       # Number of ticks simulated
-final_tick                               2369931974000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.368273                       # Number of seconds simulated
+sim_ticks                                2368273403000                       # Number of ticks simulated
+final_tick                               2368273403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 844398                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1145486                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1448435887                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232760                       # Number of bytes of host memory used
-host_seconds                                  1636.20                       # Real time elapsed on the host
+host_inst_rate                                 821983                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1115078                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1408999350                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241788                       # Number of bytes of host memory used
+host_seconds                                  1680.82                       # Real time elapsed on the host
 sim_insts                                  1381604339                       # Number of instructions simulated
 sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            144448                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data            1475585                       # Nu
 system.physmem.num_reads::total               1477842                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                60950                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39848165                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                39909115                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           60950                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              60950                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1785003                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1785003                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1785003                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               60950                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39848165                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41694118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                60993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39876072                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                39937065                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           60993                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              60993                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1786253                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1786253                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1786253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               60993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39876072                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41723318                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,7 +77,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       4739863948                       # number of cpu cycles simulated
+system.cpu.numCycles                       4736546806                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1381604339                       # Number of instructions committed
@@ -96,18 +96,18 @@ system.cpu.num_mem_refs                     908382479                       # nu
 system.cpu.num_load_insts                   631387181                       # Number of load instructions
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4739863948                       # Number of busy cycles
+system.cpu.num_busy_cycles                 4736546806                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  18364                       # number of replacements
-system.cpu.icache.tagsinuse               1392.322496                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1392.329214                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1390251699                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               70204.095289                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1392.322496                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.679845                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.679845                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1392.329214                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.679848                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.679848                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1390251699                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1390251699                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1390251699                       # number of demand (read+write) hits
@@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst        19803                       # n
 system.cpu.icache.demand_misses::total          19803                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        19803                       # number of overall misses
 system.cpu.icache.overall_misses::total         19803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    372133000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    372133000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    372133000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    372133000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    372133000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    372133000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    352238000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    352238000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    352238000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    352238000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    352238000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    352238000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1390271502                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1390271502                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1390271502                       # number of demand (read+write) accesses
@@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000014
 system.cpu.icache.demand_miss_rate::total     0.000014                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000014                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000014                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18791.748725                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18791.748725                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18791.748725                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18791.748725                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18791.748725                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18791.748725                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 17787.102964                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 17787.102964                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        19803
 system.cpu.icache.demand_mshr_misses::total        19803                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        19803                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        19803                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312724000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    312724000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312724000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    312724000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312724000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    312724000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312632000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    312632000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312632000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    312632000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312632000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    312632000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000014                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000014                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15791.748725                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15791.748725                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15791.748725                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1529557                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.950469                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.965929                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                895757408                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 584.067848                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1004561000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.950469                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999744                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999744                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle              991199000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.965929                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999748                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999748                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    618874540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       618874540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits
@@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data      1533653                       # n
 system.cpu.dcache.demand_misses::total        1533653                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1533653                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1533653                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  79650958000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  79650958000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3794840000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3794840000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  83445798000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  83445798000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  83445798000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  83445798000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  78190013000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  78190013000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3722046000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3722046000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  81912059000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  81912059000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  81912059000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  81912059000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    620335413                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    620335413                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.001709
 system.cpu.dcache.demand_miss_rate::total     0.001709                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.001709                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.001709                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.849009                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.849009                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.247595                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.247595                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.829342                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54409.829342                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.829342                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54409.829342                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53409.773267                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53409.773267                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53409.773267                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1533653
 system.cpu.dcache.demand_mshr_misses::total      1533653                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1533653                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1533653                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75268339000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75268339000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576500000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576500000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78844839000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  78844839000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78844839000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  78844839000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75268267000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75268267000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576486000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576486000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78844753000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  78844753000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78844753000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  78844753000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002355                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002355                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000263                       # mshr miss rate for WriteReq accesses
@@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001709
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001709                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.849009                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.849009                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.247595                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.247595                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.829342                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.829342                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.829342                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.829342                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1478696                       # number of replacements
-system.cpu.l2cache.tagsinuse             32689.689328                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             32690.092056                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   77413                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               1511439                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.051218                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  3194.581985                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     32.931287                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  29462.176056                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.097491                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks  3194.112587                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     32.917167                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  29463.062302                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.097477                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.001005                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.899114                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.997610                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.899141                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.997622                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst        17546                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        51381                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          68927                       # number of ReadReq hits
@@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total       1477842                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2257                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data      1475585                       # number of overall misses
 system.cpu.l2cache.overall_misses::total      1477842                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117364000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117369000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73293584000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  73410948000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  73410953000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3436836000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total   3436836000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    117364000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    117369000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data  76730420000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  76847784000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    117364000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total  76847789000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    117369000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data  76730420000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  76847784000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  76847789000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        19803                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data      1460873                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total      1480676                       # number of ReadReq accesses(hits+misses)
@@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.951325                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113973                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.962137                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.951325                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.215330                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.003542                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.215330                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000.003383                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.215330                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000.003383                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total      1477842
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2257                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      1475585                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total      1477842                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     90280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     90285000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56379680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56469960000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56469965000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2643720000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2643720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     90280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     90285000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59023400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  59113680000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     90280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  59113685000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     90285000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59023400000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  59113680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  59113685000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.964829                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.953449                       # mshr miss rate for ReadReq accesses
@@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.951325
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.962137                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.951325                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------