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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:34 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:34 -0600
commitcfb805cc71bd1c4b72691b69faa879663e548c11 (patch)
tree4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/long/se/40.perlbmk/ref/arm/linux/simple-timing
parent612f8f074fa1099cf70faf495d46cc647762a031 (diff)
downloadgem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing')
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini78
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout5
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt54
3 files changed, 123 insertions, 14 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 0bdfc6610..11c9b066a 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -105,10 +108,35 @@ hit_latency=2
sequential_access=false
size=262144
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
+is_stage2=false
size=64
walker=system.cpu.dtb.walker
@@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
+is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -163,24 +192,60 @@ eventq_index=0
type=ArmISA
eventq_index=0
fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
-id_mmfr0=3
+id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
-id_mmfr3=4027589137
+id_mmfr3=34611729
id_pfr0=49
-id_pfr1=1
-midr=890224640
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
+is_stage2=false
size=64
walker=system.cpu.itb.walker
@@ -188,6 +253,7 @@ walker=system.cpu.itb.walker
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
+is_stage2=false
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -236,7 +302,7 @@ system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
[system.cpu.tracer]
type=ExeTracer
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index 973b4e1bf..f8adf17ee 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:24:06
-gem5 started Jan 22 2014 23:11:12
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 17:50:08
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x56b7d00
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index ecd5fda89..f64dc7529 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 968971 # Simulator instruction rate (inst/s)
-host_op_rate 1314478 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1631393565 # Simulator tick rate (ticks/s)
-host_mem_usage 255816 # Number of bytes of host memory used
-host_seconds 1425.85 # Real time elapsed on the host
+host_inst_rate 908275 # Simulator instruction rate (inst/s)
+host_op_rate 1232140 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1529204664 # Simulator tick rate (ticks/s)
+host_mem_usage 276728 # Number of bytes of host memory used
+host_seconds 1521.13 # Real time elapsed on the host
sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.0 # La
system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
@@ -107,7 +149,7 @@ system.cpu.num_func_calls 80372855 # nu
system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
system.cpu.num_int_insts 1653698868 # number of integer instructions
system.cpu.num_fp_insts 52289415 # number of float instructions
-system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read
+system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read
system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written