diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
commit | e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb (patch) | |
tree | 553bace58f742b4c98ac52d600a1103901011b8b /tests/long/se/40.perlbmk/ref/arm/linux | |
parent | 0d8d6e44419e2c5464012b66abc62aaad433026b (diff) | |
download | gem5-e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb.tar.xz |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux')
-rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt | 247 |
1 files changed, 143 insertions, 104 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 11060cf95..7a6d5db32 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,33 +4,37 @@ sim_seconds 0.541786 # Nu sim_ticks 541786101000 # Number of ticks simulated final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183531 # Simulator instruction rate (inst/s) -host_op_rate 225950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155207340 # Simulator tick rate (ticks/s) -host_mem_usage 320704 # Number of bytes of host memory used -host_seconds 3490.72 # Real time elapsed on the host +host_inst_rate 115987 # Simulator instruction rate (inst/s) +host_op_rate 142796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98087491 # Simulator tick rate (ticks/s) +host_mem_usage 309428 # Number of bytes of host memory used +host_seconds 5523.50 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18593856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34319552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted @@ -415,8 +419,8 @@ system.cpu.dcache.tags.total_refs 378457747 # To system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.645412 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id @@ -427,61 +431,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 249632505 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 128813764 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 378446269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 378446269 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits system.cpu.dcache.overall_hits::total 378446269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 713747 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 851460 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32255064217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 379297729 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 379297729 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -493,45 +497,45 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 752 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68391 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 69143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 69143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23590 # number of replacements @@ -626,9 +630,11 @@ system.cpu.l2cache.tags.sampled_refs 290493 # Sa system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.519731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29632.926805 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.904325 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id @@ -639,57 +645,75 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 513866 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 491102 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 517097 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 22764 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 494333 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 517097 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 22764 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 494333 # 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number of cycles access was blocked @@ -701,43 +725,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 32 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 32 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 32 # 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Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution |