diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/se/40.perlbmk/ref/arm/linux | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt | 892 | ||||
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1768 |
2 files changed, 1332 insertions, 1328 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 7545f6451..06d9deeed 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,96 +1,96 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525654 # Number of seconds simulated -sim_ticks 525654485500 # Number of ticks simulated -final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525648 # Number of seconds simulated +sim_ticks 525647850500 # Number of ticks simulated +final_tick 525647850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 282925 # Simulator instruction rate (inst/s) -host_op_rate 348318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232138645 # Simulator tick rate (ticks/s) -host_mem_usage 279272 # Number of bytes of host memory used -host_seconds 2264.40 # Real time elapsed on the host +host_inst_rate 304424 # Simulator instruction rate (inst/s) +host_op_rate 374786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 249775392 # Simulator tick rate (ticks/s) +host_mem_usage 281156 # Number of bytes of host memory used +host_seconds 2104.48 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory -system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18639040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291235 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291229 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 313031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35146146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35459177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 313031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8047730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8047730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8047730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 313031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35146146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 43506907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291235 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291235 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18619136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18639040 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18281 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts -system.physmem.perBankRdBursts::2 18221 # Per bank write bursts -system.physmem.perBankRdBursts::3 18176 # Per bank write bursts -system.physmem.perBankRdBursts::4 18285 # Per bank write bursts -system.physmem.perBankRdBursts::5 18412 # Per bank write bursts -system.physmem.perBankRdBursts::6 18178 # Per bank write bursts +system.physmem.perBankRdBursts::0 18288 # Per bank write bursts +system.physmem.perBankRdBursts::1 18134 # Per bank write bursts +system.physmem.perBankRdBursts::2 18217 # Per bank write bursts +system.physmem.perBankRdBursts::3 18185 # Per bank write bursts +system.physmem.perBankRdBursts::4 18292 # Per bank write bursts +system.physmem.perBankRdBursts::5 18424 # Per bank write bursts +system.physmem.perBankRdBursts::6 18179 # Per bank write bursts system.physmem.perBankRdBursts::7 17990 # Per bank write bursts -system.physmem.perBankRdBursts::8 18034 # Per bank write bursts -system.physmem.perBankRdBursts::9 18056 # Per bank write bursts -system.physmem.perBankRdBursts::10 18101 # Per bank write bursts -system.physmem.perBankRdBursts::11 18200 # Per bank write bursts -system.physmem.perBankRdBursts::12 18218 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18258 # Per bank write bursts +system.physmem.perBankRdBursts::8 18031 # Per bank write bursts +system.physmem.perBankRdBursts::9 18051 # Per bank write bursts +system.physmem.perBankRdBursts::10 18108 # Per bank write bursts +system.physmem.perBankRdBursts::11 18204 # Per bank write bursts +system.physmem.perBankRdBursts::12 18211 # Per bank write bursts +system.physmem.perBankRdBursts::13 18269 # Per bank write bursts +system.physmem.perBankRdBursts::14 18079 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4135 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts +system.physmem.perBankWrBursts::4 4223 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::9 4093 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::14 4095 # Per bank write bursts +system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 525654384500 # Total gap between requests +system.physmem.totGap 525647749500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291229 # Read request sizes (log2) +system.physmem.readPktSize::6 291235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -146,23 +146,23 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4020 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4021 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,43 +194,43 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 102644 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.570282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.559533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.016403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36015 35.09% 35.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41909 40.83% 75.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13148 12.81% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1006 0.98% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 491 0.48% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1034 1.01% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 399 0.39% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 481 0.47% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8161 7.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 102644 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.515182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.167653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.604541 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads -system.physmem.totQLat 15538679500 # Total ticks spent queuing -system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers -system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.442509 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422441 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.830286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3129 77.87% 77.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 889 22.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads +system.physmem.totQLat 15528676000 # Total ticks spent queuing +system.physmem.totMemAccLat 20983501000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53377.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 72127.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 8.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -238,67 +238,67 @@ system.physmem.busUtil 0.34 # Da system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing -system.physmem.readRowHits 202495 # Number of row buffer hits during reads -system.physmem.writeRowHits 51707 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes -system.physmem.avgGap 1471073.79 # Average gap between requests -system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ) -system.physmem_0.averagePower 407.411950 # Core power per rank (mW) -system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states -system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ) +system.physmem.avgWrQLen 28.92 # Average write queue length when enqueuing +system.physmem.readRowHits 202546 # Number of row buffer hits during reads +system.physmem.writeRowHits 51789 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.35 # Row buffer hit rate for writes +system.physmem.avgGap 1471030.52 # Average gap between requests +system.physmem.pageHitRate 71.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 366410520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 194736630 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1040362260 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 173638080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 28886236080.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8300918550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634993280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 57345491820 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 51305938080 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 64928910000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 214198815120 # Total energy per rank (pJ) +system.physmem_0.averagePower 407.494892 # Core power per rank (mW) +system.physmem_0.totalIdleTime 503139346250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3209706000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12289528000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 243772297750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 133609273250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7009209500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 125757836000 # Time in different power states +system.physmem_1.actEnergy 366546180 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 194797350 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ) -system.physmem_1.averagePower 406.546781 # Core power per rank (mW) -system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 147261657 # Number of BP lookups -system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups -system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits +system.physmem_1.writeEnergy 171226440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28725815040.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8187694890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1628706720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 56919000150 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 51113801760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 65311053315 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 213675530385 # Total energy per rank (pJ) +system.physmem_1.averagePower 406.499389 # Core power per rank (mW) +system.physmem_1.totalIdleTime 503405920500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3197022000 # Time in different power states +system.physmem_1.memoryStateTime::REF 12221338000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 245475081750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 133108808000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6823284750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 124822316000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 147257105 # Number of BP lookups +system.cpu.branchPred.condPredicted 98226689 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1384794 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 89640439 # Number of BTB lookups +system.cpu.branchPred.BTBHits 63297158 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 70.612280 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19276056 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1321 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 15995188 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 15989428 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5760 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1051308971 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1051295701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 8620171 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.640991 # CPI: cycles per instruction -system.cpu.ipc 0.609388 # IPC: instructions per cycle +system.cpu.cpi 1.640970 # CPI: cycles per instruction +system.cpu.ipc 0.609396 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -468,30 +468,30 @@ system.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked -system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955914808 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95380893 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.107040 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378447440 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 483.826867 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 850680500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.107040 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 759379166 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759379166 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 249618713 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249618713 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits @@ -500,10 +500,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits -system.cpu.dcache.overall_hits::total 378437929 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 378432478 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378432478 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378435962 # number of overall hits +system.cpu.dcache.overall_hits::total 378435962 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses @@ -514,16 +514,16 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37264745000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37264745000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10940214000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10940214000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48204959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48204959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48204959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48204959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250331905 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250331905 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) @@ -532,10 +532,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379285349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379285349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379288974 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379288974 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379283382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379283382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379287007 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379287007 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -546,22 +546,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56651.465970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56642.080031 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks -system.cpu.dcache.writebacks::total 88688 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88684 # number of writebacks +system.cpu.dcache.writebacks::total 88684 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -580,16 +580,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36543095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36543095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5486426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5486426000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42029521500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42029521500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42031323500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42031323500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -600,206 +600,206 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24889 # number of replacements +system.cpu.icache.tags.tagsinuse 1710.890314 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257795451 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 26639 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9677.369684 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits -system.cpu.icache.overall_hits::total 257789639 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses -system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1710.890314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 515670821 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515670821 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257795451 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257795451 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257795451 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257795451 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257795451 # number of overall hits +system.cpu.icache.overall_hits::total 257795451 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 26640 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 26640 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 26640 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 26640 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 26640 # number of overall misses +system.cpu.icache.overall_misses::total 26640 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 538801500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 538801500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 538801500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 538801500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 538801500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 538801500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 257822091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257822091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257822091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257822091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257822091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257822091 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20225.281532 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20225.281532 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20225.281532 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20225.281532 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24885 # number of writebacks -system.cpu.icache.writebacks::total 24885 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 24889 # number of writebacks +system.cpu.icache.writebacks::total 24889 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26640 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 26640 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 26640 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 26640 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 26640 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 26640 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 512162500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 512162500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 512162500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 512162500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 512162500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 512162500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258837 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19225.319069 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19225.319069 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258839 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32651.545544 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1316953 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291607 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.516191 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 3958663000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 40.523746 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.271478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.750321 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001237 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29227 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 13160335 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13160335 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88684 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88684 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23557 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23557 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24064 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 24064 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24064 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits +system.cpu.l2cache.demand_hits::total 517570 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24064 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits -system.cpu.l2cache.overall_hits::total 517573 # number of overall hits +system.cpu.l2cache.overall_hits::total 517570 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2576 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2576 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2576 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses +system.cpu.l2cache.demand_misses::total 291266 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2576 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses -system.cpu.l2cache.overall_misses::total 291260 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 291266 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5348515000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5348515000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 218253000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 218253000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30325726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30325726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 218253000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35674241000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35892494000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 218253000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35674241000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35892494000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88684 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88684 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 23557 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 23557 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26640 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 26640 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 26637 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 26640 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 808833 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 26637 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 808836 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 26640 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 808833 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 808836 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096697 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096697 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096697 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.360105 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096697 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.360105 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80926.525548 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80926.525548 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.543478 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 123229.261225 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 123229.261225 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -820,124 +820,124 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 26 system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2572 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2572 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 291236 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4687605000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4687605000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28098015500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28098015500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192261000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32785620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32977881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192261000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32785620500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32977881500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096547 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360068 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360068 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1611825 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 803048 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2033 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2018 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 739513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882157 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 26640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78168 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258837 # Total snoops (count) +system.cpu.toL2Bus.pkt_count::total 2420660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59034112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258839 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1067675 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005002 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070750 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062349 99.50% 99.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5311 0.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1067675 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919485500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 39960496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 548040 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256844 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225138 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225144 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190702 # Transaction distribution +system.membus.trans_dist::CleanEvict 190707 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839275 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22869312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22869312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 291229 # Request fanout histogram +system.membus.snoop_fanout::samples 291235 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291235 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 291229 # Request fanout histogram -system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291235 # Request fanout histogram +system.membus.reqLayer0.occupancy 917214500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1553534250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index bcc6de449..1f99db17b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.338999 # Number of seconds simulated -sim_ticks 338998876000 # Number of ticks simulated -final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.339069 # Number of seconds simulated +sim_ticks 339069355000 # Number of ticks simulated +final_tick 339069355000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210128 # Simulator instruction rate (inst/s) -host_op_rate 258696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111189218 # Simulator tick rate (ticks/s) -host_mem_usage 277020 # Number of bytes of host memory used -host_seconds 3048.85 # Real time elapsed on the host +host_inst_rate 212003 # Simulator instruction rate (inst/s) +host_op_rate 261004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112204360 # Simulator tick rate (ticks/s) +host_mem_usage 277184 # Number of bytes of host memory used +host_seconds 3021.89 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory -system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory -system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 956909 # Number of read requests accepted -system.physmem.writeReqs 66317 # Number of write requests accepted -system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 272000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48065856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12979392 # Number of bytes read from this memory +system.physmem.bytes_read::total 61317248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 272000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 272000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4246400 # Number of bytes written to this memory +system.physmem.bytes_written::total 4246400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 751029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 958082 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66350 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66350 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 802196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141758184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 38279461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180839840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 802196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 802196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12523692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12523692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12523692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 802196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141758184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 38279461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193363532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 958083 # Number of read requests accepted +system.physmem.writeReqs 66350 # Number of write requests accepted +system.physmem.readBursts 958083 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66350 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61296960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20352 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61317312 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4246400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 318 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 71 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19928 # Per bank write bursts -system.physmem.perBankRdBursts::1 19580 # Per bank write bursts -system.physmem.perBankRdBursts::2 657267 # Per bank write bursts -system.physmem.perBankRdBursts::3 20958 # Per bank write bursts -system.physmem.perBankRdBursts::4 19729 # Per bank write bursts -system.physmem.perBankRdBursts::5 20737 # Per bank write bursts -system.physmem.perBankRdBursts::6 19560 # Per bank write bursts -system.physmem.perBankRdBursts::7 19988 # Per bank write bursts -system.physmem.perBankRdBursts::8 19522 # Per bank write bursts -system.physmem.perBankRdBursts::9 20089 # Per bank write bursts -system.physmem.perBankRdBursts::10 19525 # Per bank write bursts -system.physmem.perBankRdBursts::11 19708 # Per bank write bursts -system.physmem.perBankRdBursts::12 19661 # Per bank write bursts -system.physmem.perBankRdBursts::13 21032 # Per bank write bursts -system.physmem.perBankRdBursts::14 19553 # Per bank write bursts -system.physmem.perBankRdBursts::15 19787 # Per bank write bursts -system.physmem.perBankWrBursts::0 4255 # Per bank write bursts -system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4152 # Per bank write bursts -system.physmem.perBankWrBursts::4 4244 # Per bank write bursts -system.physmem.perBankWrBursts::5 4226 # Per bank write bursts +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19573 # Per bank write bursts +system.physmem.perBankRdBursts::2 657828 # Per bank write bursts +system.physmem.perBankRdBursts::3 21032 # Per bank write bursts +system.physmem.perBankRdBursts::4 19718 # Per bank write bursts +system.physmem.perBankRdBursts::5 21045 # Per bank write bursts +system.physmem.perBankRdBursts::6 19700 # Per bank write bursts +system.physmem.perBankRdBursts::7 20038 # Per bank write bursts +system.physmem.perBankRdBursts::8 19491 # Per bank write bursts +system.physmem.perBankRdBursts::9 20101 # Per bank write bursts +system.physmem.perBankRdBursts::10 19540 # Per bank write bursts +system.physmem.perBankRdBursts::11 19692 # Per bank write bursts +system.physmem.perBankRdBursts::12 19618 # Per bank write bursts +system.physmem.perBankRdBursts::13 21105 # Per bank write bursts +system.physmem.perBankRdBursts::14 19493 # Per bank write bursts +system.physmem.perBankRdBursts::15 19881 # Per bank write bursts +system.physmem.perBankWrBursts::0 4272 # Per bank write bursts +system.physmem.perBankWrBursts::1 4107 # Per bank write bursts +system.physmem.perBankWrBursts::2 4147 # Per bank write bursts +system.physmem.perBankWrBursts::3 4153 # Per bank write bursts +system.physmem.perBankWrBursts::4 4251 # Per bank write bursts +system.physmem.perBankWrBursts::5 4229 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4097 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4152 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::14 4095 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338998865500 # Total gap between requests +system.physmem.totGap 339069344500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 956909 # Read request sizes (log2) +system.physmem.readPktSize::6 958083 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66317 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66350 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 765133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -149,47 +149,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -198,134 +198,137 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads -system.physmem.totQLat 27417238749 # Total ticks spent queuing -system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 196319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 333.816859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.183939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.380336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 65406 33.32% 33.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 61086 31.12% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15476 7.88% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3179 1.62% 73.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3479 1.77% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2336 1.19% 76.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2511 1.28% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34323 17.48% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8523 4.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 196319 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4003 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 214.941294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.155298 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2727.024521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3978 99.38% 99.38% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-36863 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::69632-73727 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::126976-131071 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4003 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.550087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.475287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.816460 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3400 84.94% 84.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 19 0.47% 85.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 373 9.32% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 54 1.35% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.50% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.67% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.52% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.35% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.35% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 14 0.35% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.15% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.17% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.15% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 4 0.10% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4003 # Writes before turning the bus around for reads +system.physmem.totQLat 27518767878 # Total ticks spent queuing +system.physmem.totMemAccLat 45476861628 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4788825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28732.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47482.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 180.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 180.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.51 # Data bus utilization in percentage system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing -system.physmem.readRowHits 804753 # Number of row buffer hits during reads -system.physmem.writeRowHits 22823 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes -system.physmem.avgGap 331304.00 # Average gap between requests -system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ) -system.physmem_0.averagePower 558.898453 # Core power per rank (mW) -system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states -system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states -system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ) -system.physmem_1.averagePower 480.731167 # Core power per rank (mW) -system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states -system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174659469 # Number of BP lookups -system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits +system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing +system.physmem.readRowHits 804881 # Number of row buffer hits during reads +system.physmem.writeRowHits 22802 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.40 # Row buffer hit rate for writes +system.physmem.avgGap 330982.45 # Average gap between requests +system.physmem.pageHitRate 80.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 901474980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 479122545 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5703739020 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174499380 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27325665120.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14491103160 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 673386240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 138371323560 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 679220160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 661319340.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 189506984115 # Total energy per rank (pJ) +system.physmem_0.averagePower 558.903308 # Core power per rank (mW) +system.physmem_0.totalIdleTime 305432505529 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 523884278 # Time in different power states +system.physmem_0.memoryStateTime::REF 11566244000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 219111500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1768844578 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21546721193 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 303444549451 # Time in different power states +system.physmem_1.actEnergy 500335500 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 265908060 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134695940 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171325620 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 25432573920.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6980276430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1364879040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 70621447890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 30989177760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 25472740305 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 162933984825 # Total energy per rank (pJ) +system.physmem_1.averagePower 480.532913 # Core power per rank (mW) +system.physmem_1.totalIdleTime 320205691246 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2610959521 # Time in different power states +system.physmem_1.memoryStateTime::REF 10814464000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 84633345250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 80700935022 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5438217483 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 154871433724 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 175312537 # Number of BP lookups +system.cpu.branchPred.condPredicted 119126010 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4023429 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 95987051 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67762694 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 70.595662 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18784914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299715 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16714738 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16702890 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 11848 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279488 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,7 +358,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,7 +388,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,7 +418,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -446,134 +449,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 677997753 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678138711 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 35026134 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824295259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175312537 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103250498 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638595633 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8083491 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247757876 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12590 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 677669366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.498301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.263018 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 215620652 31.82% 31.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148930568 21.98% 53.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72932404 10.76% 64.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240185742 35.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 677669366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258520 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215526 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75794919 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258105460 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277738151 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62003234 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4027602 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 64856939 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 14426 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924580293 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 10545635 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4027602 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118744370 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 157469679 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209680 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 295125429 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102092606 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906546743 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6881182 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27980774 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218296 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49244088 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 491152 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980952632 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318034270 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001843328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457465 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 106174402 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138250974 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271864033 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160594184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6150346 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12039275 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899826395 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860048195 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9222152 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114019 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244270336 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 677669366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.269127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.103925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 215576710 31.81% 31.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182398349 26.92% 58.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 173866168 25.66% 84.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 93397486 13.78% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12428213 1.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2440 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 677669366 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66592795 23.99% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636888 0.23% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 132895197 47.87% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66486163 23.95% 96.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5670687 2.04% 98.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 5308776 1.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413112342 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187450 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -596,91 +599,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.37% 49.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550158 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478201 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 259635092 30.19% 80.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153408617 17.84% 98.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 7019173 0.82% 99.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 3831959 0.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued -system.cpu.iq.rate 1.268482 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860048195 # Type of FU issued +system.cpu.iq.rate 1.268248 # Inst issue rate +system.cpu.iq.fu_busy_cnt 277608649 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.322783 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2621941266 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980329396 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820105906 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62655291 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30642249 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878687 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1100523479 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 37133365 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13978556 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19623095 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18653 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31613688 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918749 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18225 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4027602 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10592950 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5943 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899848973 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271864033 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160594184 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 932 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3107 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18653 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3297561 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3294434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6591995 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850188945 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263367686 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9859250 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10143 # number of nop insts executed -system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed -system.cpu.iew.exec_branches 143380865 # Number of branches executed -system.cpu.iew.exec_stores 152688992 # Number of stores executed -system.cpu.iew.exec_rate 1.253946 # Inst execution rate -system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back -system.cpu.iew.wb_producers 486195731 # num instructions producing a value -system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value -system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9996 # number of nop insts executed +system.cpu.iew.exec_refs 416059985 # number of memory reference insts executed +system.cpu.iew.exec_branches 143387028 # Number of branches executed +system.cpu.iew.exec_stores 152692299 # Number of stores executed +system.cpu.iew.exec_rate 1.253710 # Inst execution rate +system.cpu.iew.wb_sent 846316526 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844984593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 486213090 # num instructions producing a value +system.cpu.iew.wb_consumers 804713496 # num instructions consuming a value +system.cpu.iew.wb_rate 1.246035 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.604206 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103170323 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4009286 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 663080037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.047357 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 372743600 56.21% 56.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137229465 20.70% 76.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51343947 7.74% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28225650 4.26% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14387181 2.17% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14772519 2.23% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871150 1.19% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6554658 0.99% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29951867 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 663080037 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -730,82 +733,82 @@ system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1524889115 # The number of ROB reads -system.cpu.rob.rob_writes 1798376442 # The number of ROB writes -system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29951867 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1525019812 # The number of ROB reads +system.cpu.rob.rob_writes 1798395927 # The number of ROB writes +system.cpu.timesIdled 10540 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 469345 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads -system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868460616 # number of integer regfile reads -system.cpu.int_regfile_writes 500698081 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads -system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes -system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads +system.cpu.cpi 1.058518 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058518 # CPI: Total CPI of All Threads +system.cpu.ipc 0.944717 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944717 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868485327 # number of integer regfile reads +system.cpu.int_regfile_writes 500716513 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616072 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959512 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322428373 # number of cc regfile reads +system.cpu.cc_regfile_writes 369236255 # number of cc regfile writes +system.cpu.misc_regfile_reads 606835918 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756456 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756526 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.910931 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371056816 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2757038 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.585311 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 286323500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.910931 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751754868 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751754868 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243133490 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243133490 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906319 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906319 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits -system.cpu.dcache.overall_hits::total 371036694 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371039809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371039809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371042966 # number of overall hits +system.cpu.dcache.overall_hits::total 371042966 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2398664 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2398664 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1045158 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1045158 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses -system.cpu.dcache.overall_misses::total 3446049 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3443822 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3443822 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3444469 # number of overall misses +system.cpu.dcache.overall_misses::total 3444469 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80554008500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80554008500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9982772350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9982772350 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 90536780850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90536780850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90536780850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90536780850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245532154 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245532154 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -814,469 +817,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374483631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374483631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374487435 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374487435 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009769 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009769 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008105 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009196 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009198 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009198 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33582.864670 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33582.864670 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9551.448059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9551.448059 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26289.622649 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26289.622649 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26284.684475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26284.684475 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 344610 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks -system.cpu.dcache.writebacks::total 2756456 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 70.776340 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756526 # number of writebacks +system.cpu.dcache.writebacks::total 2756526 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 363119 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 363119 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323999 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323999 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 687118 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 687118 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 687118 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 687118 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035545 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035545 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721159 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756704 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756704 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75270268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75270268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5954605850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5954605850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81224874350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 81224874350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81230450850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 81230450850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1980154 # number of replacements -system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36977.943745 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36977.943745 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8256.994435 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8256.994435 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8686.137072 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8686.137072 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29464.488879 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29464.488879 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29459.651001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29459.651001 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1980658 # number of replacements +system.cpu.icache.tags.tagsinuse 510.043873 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245773558 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1981168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.054880 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275783500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.043873 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996179 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996179 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits -system.cpu.icache.overall_hits::total 245752746 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses -system.cpu.icache.overall_misses::total 1983875 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 497497160 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497497160 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245773612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245773612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245773612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245773612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245773612 # number of overall hits +system.cpu.icache.overall_hits::total 245773612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1984230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1984230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1984230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1984230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1984230 # number of overall misses +system.cpu.icache.overall_misses::total 1984230 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16225163428 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16225163428 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16225163428 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16225163428 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16225163428 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16225163428 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247757842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247757842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247757842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247757842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247757842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247757842 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008009 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008009 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8177.057815 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8177.057815 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8177.057815 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8177.057815 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 86855 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 219 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3239 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks -system.cpu.icache.writebacks::total 1980154 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 26.815375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.285714 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1980658 # number of writebacks +system.cpu.icache.writebacks::total 1980658 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2752 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2752 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2752 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2752 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2752 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2752 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1981478 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1981478 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1981478 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1981478 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1981478 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1981478 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15191208442 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15191208442 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15191208442 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15191208442 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15191208442 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15191208442 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007998 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007998 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007998 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.604647 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.604647 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350180 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355046 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 4259 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 297120 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4789962 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 297363 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16097.095848 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3953275 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 313560 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.607715 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3358223 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718689 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718689 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976463 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1976463 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286254 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1286254 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1976463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2004943 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3981406 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1976463 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2004943 # number of overall hits -system.cpu.l2cache.overall_hits::total 3981406 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2160 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2160 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 4204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749865 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 749865 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 752025 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 756229 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 752025 # number of overall misses -system.cpu.l2cache.overall_misses::total 756229 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 187813000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 187813000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 349759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63761970000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 63761970000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 349759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 63949783000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 64299542500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 349759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 63949783000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 64299542500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 735798 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 735798 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3358223 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3358223 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980667 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1980667 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1980667 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4737635 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1980667 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4737635 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 15676.959856 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.135992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.956846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982489 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 460 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1553 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3714 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9969 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.028076 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960510 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145611380 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145611380 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 735645 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 735645 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3358020 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3358020 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718668 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718668 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976918 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1976918 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285460 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1285460 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1976918 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2004128 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3981046 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1976918 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2004128 # number of overall hits +system.cpu.l2cache.overall_hits::total 3981046 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2183 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2183 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4253 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4253 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750727 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 750727 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4253 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 752910 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 757163 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4253 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 752910 # number of overall misses +system.cpu.l2cache.overall_misses::total 757163 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 189493000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 189493000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 353014500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 353014500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63858972500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 63858972500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 353014500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 64048465500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 64401480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 353014500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 64048465500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 64401480000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 735645 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 735645 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3358020 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3358020 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 308 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 308 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720851 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720851 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1981171 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1981171 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036187 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2036187 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1981171 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2757038 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4738209 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1981171 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2757038 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4738209 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002123 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002123 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368282 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368282 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002123 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.272772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159622 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002123 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.272772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159622 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86950.462963 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86950.462963 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83196.836346 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83196.836346 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85031.265628 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85031.265628 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85026.549498 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85026.549498 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368693 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368693 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002147 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.273087 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159799 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002147 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.273087 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159799 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86803.939533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86803.939533 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83003.644486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83003.644486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85062.842418 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85062.842418 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85056.295672 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85056.295672 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3549 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66317 # number of writebacks -system.cpu.l2cache.writebacks::total 66317 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 785 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 785 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1052 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1052 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1837 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1837 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1838 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202613 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 202613 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 181 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 181 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1375 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1375 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4203 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4203 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748813 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748813 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4203 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 750188 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 754391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4203 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 750188 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 957004 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20275662144 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2881000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2881000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 136635500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 136635500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 324486000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles +system.cpu.l2cache.unused_prefetches 3562 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 66350 # number of writebacks +system.cpu.l2cache.writebacks::total 66350 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 796 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 796 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1085 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1085 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1881 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1883 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1881 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1883 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202894 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202894 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4251 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4251 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749642 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749642 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 751029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 755280 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4251 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 751029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202894 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 958174 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20344447507 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4667000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4667000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 140070000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 140070000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327411500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327411500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59289686000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59289686000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327411500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59429756000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59757167500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327411500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59429756000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80101615007 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.368160 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.368160 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202223 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100271.311655 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15152.597403 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15152.597403 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100987.743331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100987.743331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77019.877676 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77019.877676 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79090.667279 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79090.667279 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79119.223996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83598.193029 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9476008 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4737217 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 94 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 93 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 552356 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4017663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4001539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 231013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 255559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1981478 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036187 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5943305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8271218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14214523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253556928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352868096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606425024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 553229 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4266048 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5291746 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.327151 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4646773 87.81% 87.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 644972 12.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5291746 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9475188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2972215996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135722477 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1255754 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 941197 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 955532 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution -system.membus.trans_dist::CleanEvict 230803 # Transaction distribution -system.membus.trans_dist::UpgradeReq 181 # Transaction distribution -system.membus.trans_dist::ReadExReq 1375 # Transaction distribution -system.membus.trans_dist::ReadExResp 1375 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 956694 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66350 # Transaction distribution +system.membus.trans_dist::CleanEvict 231013 # Transaction distribution +system.membus.trans_dist::UpgradeReq 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 956696 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2213835 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2213835 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65563584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65563584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957090 # Request fanout histogram +system.membus.snoop_fanout::samples 958391 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 958391 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957090 # Request fanout histogram -system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 958391 # Request fanout histogram +system.membus.reqLayer0.occupancy 1760245062 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5035040414 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |