diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/40.perlbmk/ref/arm/linux | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux')
4 files changed, 1977 insertions, 1936 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 3a1bb990b..dc7a25182 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,597 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1252658454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 126529 # Simulator instruction rate (inst/s) -host_mem_usage 303852 # Number of bytes of host memory used -host_op_rate 172315 # Simulator op (including micro ops) rate (op/s) -host_seconds 10941.24 # Real time elapsed on the host -host_tick_rate 114489637 # Simulator tick rate (ticks/s) +sim_seconds 0.537826 # Number of seconds simulated +sim_ticks 537826498500 # Number of ticks simulated +final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1384383018 # Number of instructions simulated -sim_ops 1885337770 # Number of ops (including micro ops) simulated -sim_seconds 1.252658 # Number of seconds simulated -sim_ticks 1252658454500 # Number of ticks simulated +host_inst_rate 114564 # Simulator instruction rate (inst/s) +host_op_rate 141043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96175687 # Simulator tick rate (ticks/s) +host_mem_usage 263048 # Number of bytes of host memory used +host_seconds 5592.13 # Real time elapsed on the host +sim_insts 640655084 # Number of instructions simulated +sim_ops 788730743 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.275361 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 183176705 # Number of BTB hits -system.cpu.branchPred.BTBLookups 198510960 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 2809 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 27775706 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 271023918 # Number of conditional branches predicted -system.cpu.branchPred.lookups 347774230 # Number of BP lookups -system.cpu.branchPred.usedRAS 40383236 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 1384383018 # Number of instructions committed -system.cpu.committedOps 1885337770 # Number of ops (including micro ops) committed -system.cpu.cpi 1.809699 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 9985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 622157845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 622157845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30504.122168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30504.122168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28441.732178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28441.732178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 620694666 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 620694666 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44632990969 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44632990969 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002352 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002352 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 1463179 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1463179 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 1721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41566397026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41566397026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1461458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1461458 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64418.412606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64418.412606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62661.295309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62661.295309 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 276792059 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276792059 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9251708000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9251708000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 143619 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143619 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 70841 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4560363750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4560363750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 72778 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72778 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 899093523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 899093523 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33535.453099 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 897486725 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 897486725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 53884698969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53884698969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.001787 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001787 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 1606798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1606798 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 72562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 46126760776 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46126760776 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001706 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1534236 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534236 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 899093523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 899093523 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33535.453099 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 897486725 # number of overall hits -system.cpu.dcache.overall_hits::total 897486725 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 53884698969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53884698969 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.001787 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001787 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 1606798 # number of overall misses -system.cpu.dcache.overall_misses::total 1606798 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 72562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 46126760776 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46126760776 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001706 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1534236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534236 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1240 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1699 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 584.986075 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1799761222 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.531713 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999642 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999642 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1530140 # number of replacements -system.cpu.dcache.tags.sampled_refs 1534236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1799761222 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4094.531713 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 897506695 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 756574250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 96100 # number of writebacks -system.cpu.dcache.writebacks::total 96100 # number of writebacks -system.cpu.discardedOps 58655042 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 655834828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 655834828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15794.863845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15794.863845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13774.677486 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13774.677486 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 655779494 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 655779494 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 873992996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 873992996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 55334 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 55334 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 762208004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 762208004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 55334 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 55334 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 655834828 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 655834828 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15794.863845 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 655779494 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 655779494 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 873992996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 873992996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 55334 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 55334 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 762208004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 762208004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 55334 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 55334 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 655834828 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 655834828 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15794.863845 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 655779494 # number of overall hits -system.cpu.icache.overall_hits::total 655779494 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 873992996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 873992996 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 55334 # number of overall misses -system.cpu.icache.overall_misses::total 55334 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 762208004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 762208004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 55334 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 55334 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 11851.508033 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 1311724989 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1727.262157 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.843390 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.843390 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1765 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.861816 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 53568 # number of replacements -system.cpu.icache.tags.sampled_refs 55333 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 1311724989 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1727.262157 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 655779494 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 103571975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.552578 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 72778 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72778 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66889.147375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66889.147375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54354.270691 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54354.270691 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 6688 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6688 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4420703750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4420703750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.908104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.908104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3592273750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3592273750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.908104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1516792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1516792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72703.861690 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72703.861690 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60134.219047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60134.219047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 1107826 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1107826 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29733407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29733407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.269626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 408966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 30 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24591047000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24591047000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 408936 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408936 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 96100 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 96100 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 96100 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96100 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 1589570 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1589570 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71894.916073 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1114514 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1114514 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 34154111250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34154111250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.298858 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.298858 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 475056 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475056 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28183320750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28183320750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.298839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 475026 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475026 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 1589570 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1589570 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71894.916073 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1114514 # number of overall hits -system.cpu.l2cache.overall_hits::total 1114514 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 34154111250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34154111250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.298858 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.298858 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 475056 # number of overall misses -system.cpu.l2cache.overall_misses::total 475056 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28183320750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28183320750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.298839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 475026 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475026 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2580 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29670 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 2.395162 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 14033128 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 1330.818076 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 31344.832788 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040613 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997182 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 442246 # number of replacements -system.cpu.l2cache.tags.sampled_refs 474990 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 14033128 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 32675.650864 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1137678 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks -system.cpu.l2cache.writebacks::total 66099 # number of writebacks -system.cpu.numCycles 2505316909 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 2401744934 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 107882816 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 110667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3164572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3275239 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 938935000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 83558996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2375968224 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 86123089 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3541312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104341504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 107882816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 1516792 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1516791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72778 # Transaction distribution -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 34631936 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1016149 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1016149 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1205459500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4468586250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 27646751 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34631936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34631936 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 408935 # Transaction distribution -system.membus.trans_dist::ReadResp 408935 # Transaction distribution -system.membus.trans_dist::Writeback 66099 # Transaction distribution -system.membus.trans_dist::ReadExReq 66090 # Transaction distribution -system.membus.trans_dist::ReadExResp 66090 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 2314919.25 # Average gap between requests -system.physmem.avgMemAccLat 29362.18 # Average memory access latency per DRAM burst -system.physmem.avgQLat 10612.18 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 24.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 24.27 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.38 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 26.46 # Average write queue length when enqueuing -system.physmem.busUtil 0.22 # Data bus utilization in percentage -system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 133348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 133348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 24269664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 24269664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3377087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 24269664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 27646751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 3377087 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3377087 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 204371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 169.307779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 122.893449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.869772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 84097 41.15% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 91184 44.62% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16888 8.26% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 803 0.39% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1089 0.53% 94.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1331 0.65% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 576 0.28% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 520 0.25% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7883 3.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 204371 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 30374976 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 30401600 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 26624 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 4230336 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 30401600 # Number of bytes read from this memory -system.physmem.bytes_read::total 30401600 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 639262116250 # Time in different power states -system.physmem.memoryStateTime::REF 41828800000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 571561257500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory +system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290531 # Number of read requests accepted +system.physmem.writeReqs 66098 # Number of write requests accepted +system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 475025 # Number of read requests responded to by this memory -system.physmem.num_reads::total 475025 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.pageHitRate 62.20 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 29837 # Per bank write bursts -system.physmem.perBankRdBursts::1 29647 # Per bank write bursts -system.physmem.perBankRdBursts::2 29757 # Per bank write bursts -system.physmem.perBankRdBursts::3 29702 # Per bank write bursts -system.physmem.perBankRdBursts::4 29776 # Per bank write bursts -system.physmem.perBankRdBursts::5 29847 # Per bank write bursts -system.physmem.perBankRdBursts::6 29613 # Per bank write bursts -system.physmem.perBankRdBursts::7 29430 # Per bank write bursts -system.physmem.perBankRdBursts::8 29457 # Per bank write bursts -system.physmem.perBankRdBursts::9 29488 # Per bank write bursts -system.physmem.perBankRdBursts::10 29541 # Per bank write bursts -system.physmem.perBankRdBursts::11 29643 # Per bank write bursts -system.physmem.perBankRdBursts::12 29678 # Per bank write bursts -system.physmem.perBankRdBursts::13 29796 # Per bank write bursts -system.physmem.perBankRdBursts::14 29601 # Per bank write bursts -system.physmem.perBankRdBursts::15 29796 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts -system.physmem.perBankWrBursts::1 4100 # Per bank write bursts +system.physmem.perBankRdBursts::0 18283 # Per bank write bursts +system.physmem.perBankRdBursts::1 18133 # Per bank write bursts +system.physmem.perBankRdBursts::2 18223 # Per bank write bursts +system.physmem.perBankRdBursts::3 18187 # Per bank write bursts +system.physmem.perBankRdBursts::4 18258 # Per bank write bursts +system.physmem.perBankRdBursts::5 18313 # Per bank write bursts +system.physmem.perBankRdBursts::6 18090 # Per bank write bursts +system.physmem.perBankRdBursts::7 17910 # Per bank write bursts +system.physmem.perBankRdBursts::8 17943 # Per bank write bursts +system.physmem.perBankRdBursts::9 17966 # Per bank write bursts +system.physmem.perBankRdBursts::10 18023 # Per bank write bursts +system.physmem.perBankRdBursts::11 18118 # Per bank write bursts +system.physmem.perBankRdBursts::12 18159 # Per bank write bursts +system.physmem.perBankRdBursts::13 18277 # Per bank write bursts +system.physmem.perBankRdBursts::14 18081 # Per bank write bursts +system.physmem.perBankRdBursts::15 18260 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts +system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts +system.physmem.perBankWrBursts::3 4147 # Per bank write bursts +system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::10 4094 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4094 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.067006 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 508.980201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 474221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 537826410500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 290531 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66098 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -621,30 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 475025 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 475025 # Read request sizes (log2) -system.physmem.readReqs 475025 # Number of read requests accepted -system.physmem.readRowHitRate 60.31 # Row buffer hit rate for reads -system.physmem.readRowHits 286253 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 416 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 2373045000 # Total ticks spent in databus transfers -system.physmem.totGap 1252658366500 # Total gap between requests -system.physmem.totMemAccLat 13935557250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 5036638500 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489144 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.467620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859483 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3026 75.52% 75.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2 0.05% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -660,8 +140,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see @@ -672,12 +152,12 @@ system.physmem.wrQLenPdf::23 4008 # Wh system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -709,17 +189,537 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 66099 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66099 # Write request sizes (log2) -system.physmem.writeReqs 66099 # Number of write requests accepted -system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes -system.physmem.writeRowHits 50044 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads +system.physmem.totQLat 3341298000 # Total ticks spent queuing +system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.33 # Data bus utilization in percentage +system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing +system.physmem.readRowHits 194846 # Number of row buffer hits during reads +system.physmem.writeRowHits 49995 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgGap 1508083.78 # Average gap between requests +system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states +system.physmem.memoryStateTime::REF 17958980000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 42437954 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224439 # Transaction distribution +system.membus.trans_dist::ReadResp 224439 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66092 # Transaction distribution +system.membus.trans_dist::ReadExResp 66092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22824256 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 154837020 # Number of BP lookups +system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 1075652997 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 640655084 # Number of instructions committed +system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed +system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.678989 # CPI: cycles per instruction +system.cpu.ipc 0.595596 # IPC: instructions per cycle +system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked +system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 23597 # number of replacements +system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses +system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits +system.cpu.icache.overall_hits::total 289999264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses +system.cpu.icache.overall_misses::total 25348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 257750 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2831 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29389 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7553321 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7553321 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 513976 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 513976 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 517207 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517207 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 517207 # number of overall hits +system.cpu.l2cache.overall_hits::total 517207 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 224469 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224469 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66092 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66092 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 290561 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses +system.cpu.l2cache.overall_misses::total 290561 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 807768 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # 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mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1354 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1577 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759392478 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759392478 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 249628224 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249628224 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 128813893 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813893 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 378442117 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378442117 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 378442117 # number of overall hits +system.cpu.dcache.overall_hits::total 378442117 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 713850 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137584 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137584 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 851434 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses +system.cpu.dcache.overall_misses::total 851434 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks +system.cpu.dcache.writebacks::total 91420 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index fbd52f02a..e42758d84 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.634728 # Number of seconds simulated -sim_ticks 634728078000 # Number of ticks simulated -final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.297198 # Number of seconds simulated +sim_ticks 297198275500 # Number of ticks simulated +final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97161 # Simulator instruction rate (inst/s) -host_op_rate 132320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44547849 # Simulator tick rate (ticks/s) -host_mem_usage 267228 # Number of bytes of host memory used -host_seconds 14248.23 # Real time elapsed on the host -sim_insts 1384370590 # Number of instructions simulated -sim_ops 1885325342 # Number of ops (including micro ops) simulated +host_inst_rate 98901 # Simulator instruction rate (inst/s) +host_op_rate 121761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45880544 # Simulator tick rate (ticks/s) +host_mem_usage 261988 # Number of bytes of host memory used +host_seconds 6477.65 # Real time elapsed on the host +sim_insts 640649298 # Number of instructions simulated +sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory -system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory +system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474992 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62035569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290424 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290424 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18565376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18587136 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29868 # Per bank write bursts -system.physmem.perBankRdBursts::1 29664 # Per bank write bursts -system.physmem.perBankRdBursts::2 29737 # Per bank write bursts -system.physmem.perBankRdBursts::3 29712 # Per bank write bursts -system.physmem.perBankRdBursts::4 29799 # Per bank write bursts -system.physmem.perBankRdBursts::5 29810 # Per bank write bursts -system.physmem.perBankRdBursts::6 29625 # Per bank write bursts -system.physmem.perBankRdBursts::7 29426 # Per bank write bursts -system.physmem.perBankRdBursts::8 29475 # Per bank write bursts -system.physmem.perBankRdBursts::9 29463 # Per bank write bursts -system.physmem.perBankRdBursts::10 29528 # Per bank write bursts -system.physmem.perBankRdBursts::11 29636 # Per bank write bursts -system.physmem.perBankRdBursts::12 29682 # Per bank write bursts -system.physmem.perBankRdBursts::13 29788 # Per bank write bursts -system.physmem.perBankRdBursts::14 29619 # Per bank write bursts -system.physmem.perBankRdBursts::15 29790 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18318 # Per bank write bursts +system.physmem.perBankRdBursts::1 18131 # Per bank write bursts +system.physmem.perBankRdBursts::2 18196 # Per bank write bursts +system.physmem.perBankRdBursts::3 18163 # Per bank write bursts +system.physmem.perBankRdBursts::4 18256 # Per bank write bursts +system.physmem.perBankRdBursts::5 18279 # Per bank write bursts +system.physmem.perBankRdBursts::6 18091 # Per bank write bursts +system.physmem.perBankRdBursts::7 17906 # Per bank write bursts +system.physmem.perBankRdBursts::8 17946 # Per bank write bursts +system.physmem.perBankRdBursts::9 17953 # Per bank write bursts +system.physmem.perBankRdBursts::10 18007 # Per bank write bursts +system.physmem.perBankRdBursts::11 18104 # Per bank write bursts +system.physmem.perBankRdBursts::12 18147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18252 # Per bank write bursts +system.physmem.perBankRdBursts::14 18085 # Per bank write bursts +system.physmem.perBankRdBursts::15 18250 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4171 # Per bank write bursts +system.physmem.perBankWrBursts::6 4170 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4090 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4091 # Per bank write bursts system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::15 4139 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 634728009000 # Total gap between requests +system.physmem.totGap 297198223500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474992 # Read request sizes (log2) +system.physmem.readPktSize::6 290424 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 235690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49717 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,93 +193,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 106390 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 4985394000 # Total ticks spent queuing -system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads +system.physmem.totQLat 3531270750 # Total ticks spent queuing +system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.60 # Data bus utilization in percentage +system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing -system.physmem.readRowHits 298015 # Number of row buffer hits during reads -system.physmem.writeRowHits 49917 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes -system.physmem.avgGap 1173054.41 # Average gap between requests -system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states -system.physmem.memoryStateTime::REF 21194940000 # Time in different power states +system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing +system.physmem.readRowHits 199840 # Number of row buffer hits during reads +system.physmem.writeRowHits 49907 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes +system.physmem.avgGap 833604.16 # Average gap between requests +system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states +system.physmem.memoryStateTime::REF 9923940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states +system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54558418 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408916 # Transaction distribution -system.membus.trans_dist::ReadResp 408916 # Transaction distribution +system.membus.throughput 76774820 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 224345 # Transaction distribution +system.membus.trans_dist::ReadResp 224344 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution -system.membus.trans_dist::ReadExReq 66076 # Transaction distribution -system.membus.trans_dist::ReadExResp 66076 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34629760 # Total data (bytes) +system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution +system.membus.trans_dist::ReadExReq 66079 # Transaction distribution +system.membus.trans_dist::ReadExResp 66079 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22817344 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 478607550 # Number of BP lookups -system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups -system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits +system.cpu.branchPred.lookups 271863224 # Number of BP lookups +system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups +system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -364,519 +364,518 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1269456157 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 594396552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed -system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed +system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued -system.cpu.iq.rate 1.964874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued +system.cpu.iq.rate 1.934083 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12697 # number of nop insts executed -system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed -system.cpu.iew.exec_branches 329019811 # Number of branches executed -system.cpu.iew.exec_stores 429891953 # Number of stores executed -system.cpu.iew.exec_rate 1.909637 # Inst execution rate -system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1389701712 # num instructions producing a value -system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value +system.cpu.iew.exec_nop 633128 # number of nop insts executed +system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed +system.cpu.iew.exec_branches 162537737 # Number of branches executed +system.cpu.iew.exec_stores 207479483 # Number of stores executed +system.cpu.iew.exec_rate 1.878131 # Inst execution rate +system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back +system.cpu.iew.wb_producers 606518919 # num instructions producing a value +system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back +system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384381606 # Number of instructions committed -system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle +system.cpu.commit.committedInsts 640654410 # Number of instructions committed +system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908382478 # Number of memory references committed -system.cpu.commit.loads 631387181 # Number of loads committed -system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 298259106 # Number of branches committed -system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. -system.cpu.commit.function_calls 41577833 # Number of function calls committed. +system.cpu.commit.refs 381221434 # Number of memory references committed +system.cpu.commit.loads 252240938 # Number of loads committed +system.cpu.commit.membars 5740 # Number of memory barriers committed +system.cpu.commit.branches 137364859 # Number of branches committed +system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. +system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. +system.cpu.commit.function_calls 19275340 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 930022484 49.33% 49.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 11168279 0.59% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 1375288 0.07% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.99% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 6876469 0.36% 50.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 5501172 0.29% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 22010188 1.17% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.82% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 631387181 33.49% 85.31% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction -system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction +system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3962036316 # The number of ROB reads -system.cpu.rob.rob_writes 6083536675 # The number of ROB writes -system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384370590 # Number of Instructions Simulated -system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads -system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads -system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads -system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes -system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads -system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1926179188 # The number of ROB reads +system.cpu.rob.rob_writes 3042778169 # The number of ROB writes +system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 640649298 # Number of Instructions Simulated +system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads +system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads +system.cpu.int_regfile_writes 646986163 # number of integer regfile writes +system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads +system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes +system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads +system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes +system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads +system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 24993 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10545 # number of replacements +system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.825684 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 716098748 # Number of tag accesses -system.cpu.icache.tags.data_accesses 716098748 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 357999320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 357999320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 357999320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 357999320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 357999320 # number of overall hits -system.cpu.icache.overall_hits::total 357999320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34446 # number of overall misses -system.cpu.icache.overall_misses::total 34446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 570147243 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 570147243 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 570147243 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 570147243 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 570147243 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 358033766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 358033766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 358033766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 358033766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 358033766 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16551.914388 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16551.914388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16551.914388 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1683 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1626.781544 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.794327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.794327 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1664 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1549 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 415715422 # Number of tag accesses +system.cpu.icache.tags.data_accesses 415715422 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 207833630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 207833630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 207833630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 207833630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 207833630 # number of overall hits +system.cpu.icache.overall_hits::total 207833630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16808 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16808 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16808 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16808 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16808 # number of overall misses +system.cpu.icache.overall_misses::total 16808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373718245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373718245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373718245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373718245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373718245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373718245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 207850438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 207850438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 207850438 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 207850438 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 207850438 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 207850438 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000081 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000081 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000081 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000081 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000081 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000081 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22234.545752 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22234.545752 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1690 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60.107143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3230 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3230 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3230 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3230 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3230 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3230 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31216 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31216 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31216 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31216 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31216 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31216 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 454582253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 454582253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 454582253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 454582253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 454582253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 454582253 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,201 +887,217 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2438 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406478 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 408916 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4530 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4530 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66076 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66076 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2438 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3923643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145569750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28232036000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28377605750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145569750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28232036000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28377605750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277540 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274209 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999338 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999338 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.303748 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.303748 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59708.675144 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59802.480085 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59801.920810 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2347 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221998 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224345 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2334 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2334 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66079 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66079 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2347 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288077 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2347 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288077 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290424 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 142668750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13415878250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13558547000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 23342334 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 23342334 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4297620250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4297620250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142668750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17713498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17856167250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142668750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17713498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17856167250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.310557 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308569 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998716 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998716 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953370 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953370 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.364689 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.364689 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60787.707712 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.428445 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60436.145223 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59380.766088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59380.766088 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65037.610285 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65037.610285 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532989 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.399228 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 981387634 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1537085 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 638.473236 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 399634250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.399228 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999609 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 780052 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.850454 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 456274938 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 784148 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 581.873496 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 340792000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.850454 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999231 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999231 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2364 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 451 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1969885597 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1969885597 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 705264252 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 705264252 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276089331 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276089331 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 981353583 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 981353583 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 981353583 # number of overall hits -system.cpu.dcache.overall_hits::total 981353583 # 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number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses -system.cpu.dcache.overall_misses::total 2800686 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked +system.cpu.dcache.demand_misses::cpu.data 2612788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2612788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2612944 # number of overall misses +system.cpu.dcache.overall_misses::total 2612944 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65672832321 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69021730126 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 134694562447 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 134694562447 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 4061 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 458866051 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 458866051 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 458870112 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 458870112 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004838 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007884 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038414 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000522 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005694 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005694 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005694 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51552.044195 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51548.966395 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3326 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.194444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96290 # number of writebacks -system.cpu.dcache.writebacks::total 96290 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489763 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489763 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769304 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769304 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 91367 # number of writebacks +system.cpu.dcache.writebacks::total 91367 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881385 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 881385 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 945064 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 945064 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1259067 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1259067 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1259067 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1259067 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464576 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464576 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77043 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77043 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541619 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541619 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41415183522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41415183522 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4998292971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4998292971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46413476493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46413476493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46413476493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46413476493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002071 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002071 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001566 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001566 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1826449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1826449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1826449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1826449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 714700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 714700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71639 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71639 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 147 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 786339 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 786486 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 786486 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21837733771 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293200916 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2189000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27130934687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27133123687 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000556 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.036198 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001714 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001714 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 620dbb60e..a6a0dd3a8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.945613 # Number of seconds simulated -sim_ticks 945613126000 # Number of ticks simulated -final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.395727 # Number of seconds simulated +sim_ticks 395726778000 # Number of ticks simulated +final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1407956 # Simulator instruction rate (inst/s) -host_op_rate 1917442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 961716087 # Simulator tick rate (ticks/s) -host_mem_usage 309672 # Number of bytes of host memory used -host_seconds 983.26 # Real time elapsed on the host -sim_insts 1384381606 # Number of instructions simulated -sim_ops 1885336358 # Number of ops (including micro ops) simulated +host_inst_rate 935276 # Simulator instruction rate (inst/s) +host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 577711928 # Simulator tick rate (ticks/s) +host_mem_usage 250216 # Number of bytes of host memory used +host_seconds 684.99 # Real time elapsed on the host +sim_insts 640654410 # Number of instructions simulated +sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory -system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory -system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9675679644 # Throughput (bytes/s) -system.membus.data_through_bus 9149449674 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 2573511592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory +system.physmem.bytes_read::total 3718230108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2573511592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2573511592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory +system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 643377898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory +system.physmem.num_reads::total 893713136 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory +system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6503253596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2892699154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9395952750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6503253596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6503253596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1322421029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1322421029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10718373779 # Throughput (bytes/s) +system.membus.data_through_bus 4241547521 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -123,64 +123,66 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1891226253 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 791453557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1384381606 # Number of instructions committed -system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698868 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382479 # number of memory refs -system.cpu.num_load_insts 631387181 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.committedInsts 640654410 # Number of instructions committed +system.cpu.committedOps 788730069 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 2369173291 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1891226253 # Number of busy cycles +system.cpu.num_busy_cycles 791453557 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 298259106 # Number of branches fetched +system.cpu.Branches 137364859 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction -system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction -system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1885337770 # Class of executed instruction +system.cpu.op_class::total 788730743 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index baba5d53b..d4c7242b6 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.326119 # Number of seconds simulated -sim_ticks 2326118592000 # Number of ticks simulated -final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043695 # Number of seconds simulated +sim_ticks 1043695084000 # Number of ticks simulated +final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 706219 # Simulator instruction rate (inst/s) -host_op_rate 958037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1189016431 # Simulator tick rate (ticks/s) -host_mem_usage 318376 # Number of bytes of host memory used -host_seconds 1956.34 # Real time elapsed on the host -sim_insts 1381604339 # Number of instructions simulated -sim_ops 1874244941 # Number of ops (including micro ops) simulated +host_inst_rate 520727 # Simulator instruction rate (inst/s) +host_op_rate 639745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850028397 # Simulator tick rate (ticks/s) +host_mem_usage 259968 # Number of bytes of host memory used +host_seconds 1227.84 # Real time elapsed on the host +sim_insts 639366786 # Number of instructions simulated +sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory -system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 14864384 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408063 # Transaction distribution -system.membus.trans_dist::ReadResp 408063 # Transaction distribution -system.membus.trans_dist::Writeback 66099 # Transaction distribution +system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory +system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21818480 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34576320 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22771840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -137,117 +137,119 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4652237184 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 2087390168 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1381604339 # Number of instructions committed -system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698868 # number of integer instructions -system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written -system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read -system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382479 # number of memory refs -system.cpu.num_load_insts 631387181 # Number of load instructions -system.cpu.num_store_insts 276995298 # Number of store instructions +system.cpu.committedInsts 639366786 # Number of instructions committed +system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4652237184 # Number of busy cycles +system.cpu.num_busy_cycles 2087390168 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 298259106 # Number of branches fetched +system.cpu.Branches 137364859 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction -system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction -system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction -system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1885337770 # Class of executed instruction -system.cpu.icache.tags.replacements 18364 # number of replacements -system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks. +system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.icache.tags.replacements 8769 # number of replacements +system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits -system.cpu.icache.overall_hits::total 1390251699 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses -system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits +system.cpu.icache.overall_hits::total 643367691 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses +system.cpu.icache.overall_misses::total 10208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,123 +258,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 441378 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 256932 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1387 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31024 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13744605 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13744605 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96257 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96257 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18030 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1061270 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1079300 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18030 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1061270 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 568 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1040 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1796115775 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1796115775 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits -system.cpu.dcache.overall_hits::total 895737438 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses -system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits +system.cpu.dcache.overall_hits::total 378498833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses +system.cpu.dcache.overall_misses::total 782143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,60 +520,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks -system.cpu.dcache.writebacks::total 96257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks +system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) +system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |