stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

3 files changed, 15 insertions, 42 deletions

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 35b8ed937..b04619cac 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.489946                       # Nu
 sim_ticks                                489945697500                       # Number of ticks simulated
 final_tick                               489945697500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 199747                       # Simulator instruction rate (inst/s)
-host_op_rate                                   245915                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              152758149                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280032                       # Number of bytes of host memory used
-host_seconds                                  3207.33                       # Real time elapsed on the host
+host_inst_rate                                 235921                       # Simulator instruction rate (inst/s)
+host_op_rate                                   290449                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              180421993                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280028                       # Number of bytes of host memory used
+host_seconds                                  2715.55                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -537,8 +537,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        88712                       # number of writebacks
 system.cpu.dcache.writebacks::total             88712                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          904                       # number of ReadReq MSHR hits
@@ -589,7 +587,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             24859                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1712.892625                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           252585994                       # Total number of references to valid blocks.
@@ -648,8 +645,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        24859                       # number of writebacks
 system.cpu.icache.writebacks::total             24859                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        26613                       # number of ReadReq MSHR misses
@@ -676,7 +671,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395
 system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           258808                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32560.749490                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1247790                       # Total number of references to valid blocks.
@@ -785,8 +779,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
@@ -847,7 +839,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1612172                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       803221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3314                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 4c772ec0f..2624c980a 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.326731                       # Nu
 sim_ticks                                326731324000                       # Number of ticks simulated
 final_tick                               326731324000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133673                       # Simulator instruction rate (inst/s)
-host_op_rate                                   164569                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68173047                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277340                       # Number of bytes of host memory used
-host_seconds                                  4792.68                       # Real time elapsed on the host
+host_inst_rate                                 138534                       # Simulator instruction rate (inst/s)
+host_op_rate                                   170554                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               70652444                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277336                       # Number of bytes of host memory used
+host_seconds                                  4624.49                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -811,8 +811,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets            4812                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    73.103907                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2756452                       # number of writebacks
 system.cpu.dcache.writebacks::total           2756452                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       366436                       # number of ReadReq MSHR hits
@@ -865,7 +863,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1979880                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.626245                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           245759391                       # Total number of references to valid blocks.
@@ -925,8 +922,6 @@ system.cpu.icache.blocked::no_mshrs              2912                       # nu
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    25.917582                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           15                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks      1979880                       # number of writebacks
 system.cpu.icache.writebacks::total           1979880                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3014                       # number of ReadReq MSHR hits
@@ -959,7 +954,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7623.101721
 system.cpu.icache.demand_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued      1350865                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified      1355053                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit         3664                       # number of redundant prefetches already in prefetch queue
@@ -1084,8 +1078,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches             2695                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks        66334                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66334                       # number of writebacks
@@ -1169,7 +1161,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      9474058                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      4736544                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests       643707                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 92b150303..c2f10176e 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.045756                       # Nu
 sim_ticks                                1045756396500                       # Number of ticks simulated
 final_tick                               1045756396500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 725560                       # Simulator instruction rate (inst/s)
-host_op_rate                                   891395                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1186735876                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 325196                       # Number of bytes of host memory used
-host_seconds                                   881.20                       # Real time elapsed on the host
+host_inst_rate                                 744148                       # Simulator instruction rate (inst/s)
+host_op_rate                                   914231                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1217137628                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277972                       # Number of bytes of host memory used
+host_seconds                                   859.19                       # Real time elapsed on the host
 sim_insts                                   639366787                       # Number of instructions simulated
 sim_ops                                     785501035                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks        88995                       # number of writebacks
 system.cpu.dcache.writebacks::total             88995                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
@@ -352,7 +350,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              8769                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1391.385132                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           643367692                       # Total number of references to valid blocks.
@@ -411,8 +408,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         8769                       # number of writebacks
 system.cpu.icache.writebacks::total              8769                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10208                       # number of ReadReq MSHR misses
@@ -439,7 +434,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878
 system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           257772                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        32622.591915                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1218050                       # Total number of references to valid blocks.
@@ -548,8 +542,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
@@ -600,7 +592,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1579165                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       786845                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1110                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.