diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
| commit | f71fa1715793c764ffa95411e87b73179a7c7b3f (patch) | |
| tree | b4095efe0bda4413326c5860754921b7d8ae78e3 /tests/long/se/40.perlbmk/ref/arm/linux | |
| parent | 42fe2df35495685e616f74ad3342953714c7dcc1 (diff) | |
| download | gem5-f71fa1715793c764ffa95411e87b73179a7c7b3f.tar.xz | |
stats: arm: updates
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux')
4 files changed, 1434 insertions, 1425 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index ab62c741a..5cc3f8bc2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.545057 # Number of seconds simulated -sim_ticks 545056655500 # Number of ticks simulated -final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.545048 # Number of seconds simulated +sim_ticks 545048444500 # Number of ticks simulated +final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122221 # Simulator instruction rate (inst/s) -host_op_rate 150470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103982941 # Simulator tick rate (ticks/s) -host_mem_usage 247272 # Number of bytes of host memory used -host_seconds 5241.79 # Real time elapsed on the host -sim_insts 640655084 # Number of instructions simulated -sim_ops 788730743 # Number of ops (including micro ops) simulated +host_inst_rate 131789 # Simulator instruction rate (inst/s) +host_op_rate 162250 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112122004 # Simulator tick rate (ticks/s) +host_mem_usage 314432 # Number of bytes of host memory used +host_seconds 4861.21 # Real time elapsed on the host +sim_insts 640655085 # Number of instructions simulated +sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18429248 # Number of bytes read from this memory -system.physmem.bytes_read::total 18594112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164864 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429312 # Number of bytes read from this memory +system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2576 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287957 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290533 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287958 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 302471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33811619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34114090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7761160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7761160 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7761160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33811619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41875251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290533 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 301889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33812246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34114135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 301889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 301889 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7761277 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7761277 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7761277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 301889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33812246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41875412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290533 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18594112 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18574016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228992 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18287 # Per bank write bursts -system.physmem.perBankRdBursts::1 18141 # Per bank write bursts -system.physmem.perBankRdBursts::2 18224 # Per bank write bursts -system.physmem.perBankRdBursts::3 18184 # Per bank write bursts -system.physmem.perBankRdBursts::4 18267 # Per bank write bursts -system.physmem.perBankRdBursts::5 18318 # Per bank write bursts -system.physmem.perBankRdBursts::6 18100 # Per bank write bursts -system.physmem.perBankRdBursts::7 17916 # Per bank write bursts -system.physmem.perBankRdBursts::8 17940 # Per bank write bursts -system.physmem.perBankRdBursts::9 17966 # Per bank write bursts -system.physmem.perBankRdBursts::10 18025 # Per bank write bursts -system.physmem.perBankRdBursts::11 18111 # Per bank write bursts -system.physmem.perBankRdBursts::12 18143 # Per bank write bursts -system.physmem.perBankRdBursts::13 18269 # Per bank write bursts -system.physmem.perBankRdBursts::14 18078 # Per bank write bursts -system.physmem.perBankRdBursts::15 18262 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts -system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4136 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts -system.physmem.perBankWrBursts::5 4223 # Per bank write bursts +system.physmem.perBankRdBursts::0 18284 # Per bank write bursts +system.physmem.perBankRdBursts::1 18137 # Per bank write bursts +system.physmem.perBankRdBursts::2 18223 # Per bank write bursts +system.physmem.perBankRdBursts::3 18185 # Per bank write bursts +system.physmem.perBankRdBursts::4 18266 # Per bank write bursts +system.physmem.perBankRdBursts::5 18315 # Per bank write bursts +system.physmem.perBankRdBursts::6 18094 # Per bank write bursts +system.physmem.perBankRdBursts::7 17909 # Per bank write bursts +system.physmem.perBankRdBursts::8 17941 # Per bank write bursts +system.physmem.perBankRdBursts::9 17963 # Per bank write bursts +system.physmem.perBankRdBursts::10 18019 # Per bank write bursts +system.physmem.perBankRdBursts::11 18118 # Per bank write bursts +system.physmem.perBankRdBursts::12 18147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18275 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18266 # Per bank write bursts +system.physmem.perBankWrBursts::0 4174 # Per bank write bursts +system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.perBankWrBursts::2 4137 # Per bank write bursts +system.physmem.perBankWrBursts::3 4147 # Per bank write bursts +system.physmem.perBankWrBursts::4 4226 # Per bank write bursts +system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4094 # Per bank write bursts -system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::9 4090 # Per bank write bursts +system.physmem.perBankWrBursts::10 4090 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 545056561000 # Total gap between requests +system.physmem.totGap 545048350000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290533 # Read request sizes (log2) +system.physmem.readPktSize::6 290529 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 376 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,19 +144,19 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see @@ -193,42 +193,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 112303 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 203.039278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.213865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 254.441282 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47271 42.09% 42.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43737 38.95% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8997 8.01% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1907 1.70% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 490 0.44% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 112303 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 112309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.026151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.211216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.422571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47277 42.10% 42.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43772 38.97% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8960 7.98% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1911 1.70% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 490 0.44% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 736 0.66% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 729 0.65% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 499 0.44% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7935 7.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 112309 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.549530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.524570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.056534 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.518625 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.481417 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.460113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.855134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.482415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.461068 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856030 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3042 75.88% 75.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 75.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 24.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads -system.physmem.totQLat 2738025750 # Total ticks spent queuing -system.physmem.totMemAccLat 8179857000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9433.95 # Average queueing delay per DRAM burst +system.physmem.totQLat 2724193250 # Total ticks spent queuing +system.physmem.totMemAccLat 8165799500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9386.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28183.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28136.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s @@ -238,49 +240,49 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing -system.physmem.readRowHits 193900 # Number of row buffer hits during reads -system.physmem.writeRowHits 50093 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing +system.physmem.readRowHits 193908 # Number of row buffer hits during reads +system.physmem.writeRowHits 50072 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 1528348.80 # Average gap between requests +system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes +system.physmem.avgGap 1528342.92 # Average gap between requests system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 424055520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 231379500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 106906564890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 233254311000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 377766467790 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.081659 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 387327017750 # Time in different power states -system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states +system.physmem_0.actEnergy 423889200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 231288750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134182400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 106422668235 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 233674110000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 377701475625 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.972318 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 388027097500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18200260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 139526544250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 138818528500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 424894680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231837375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 105911923725 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 234126803250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 377637362310 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.844791 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 388779883250 # Time in different power states -system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states +system.physmem_1.actEnergy 425113920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231957000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129245000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212556960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35599708560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 106328346345 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 233756848500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 377683776285 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.939845 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 388162097500 # Time in different power states +system.physmem_1.memoryStateTime::REF 18200260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 138072943000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138683202500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 155213668 # Number of BP lookups -system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12879317 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90304208 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82854286 # Number of BTB hits +system.cpu.branchPred.lookups 155052076 # Number of BP lookups +system.cpu.branchPred.condPredicted 105344550 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12879569 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90401009 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82966187 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.750194 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19341274 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.775731 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19284792 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -400,37 +402,37 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1090113311 # number of cpu cycles simulated +system.cpu.numCycles 1090096889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 640655084 # Number of instructions committed -system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 22623250 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 640655085 # Number of instructions committed +system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed +system.cpu.discardedOps 22623818 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.701560 # CPI: cycles per instruction -system.cpu.ipc 0.587696 # IPC: instructions per cycle -system.cpu.tickCycles 1030410775 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59702536 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778141 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378456342 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.812888 # Average number of references to valid blocks. +system.cpu.cpi 1.701535 # CPI: cycles per instruction +system.cpu.ipc 0.587705 # IPC: instructions per cycle +system.cpu.tickCycles 1030366439 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59730450 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778156 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.460333 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378456871 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782252 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.804287 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460333 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249627614 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249627614 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 759399046 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759399046 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249628143 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249628143 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits @@ -439,30 +441,30 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378441379 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378441379 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378444864 # number of overall hits -system.cpu.dcache.overall_hits::total 378444864 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713664 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713664 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 378441908 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378441908 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378445393 # number of overall hits +system.cpu.dcache.overall_hits::total 378445393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713673 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713673 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 851376 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851376 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851517 # number of overall misses -system.cpu.dcache.overall_misses::total 851517 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24697977718 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24697977718 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34888229468 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34888229468 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34888229468 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34888229468 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250341278 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250341278 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 851385 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851385 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851526 # number of overall misses +system.cpu.dcache.overall_misses::total 851526 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24678796218 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24678796218 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10203720250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10203720250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34882516468 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34882516468 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34882516468 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34882516468 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250341816 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250341816 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) @@ -471,10 +473,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379292755 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379292755 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379293293 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379293293 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379296919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379296919 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -485,14 +487,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.290991 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.290991 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.638660 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40978.638660 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40971.853137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40971.853137 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34579.977410 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34579.977410 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74094.634091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74094.634091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40971.495232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40971.495232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.710964 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40964.710964 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,34 +505,34 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 888 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 888 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 882 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 882 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69278 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69278 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69278 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69278 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712776 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712776 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 69272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712791 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712791 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782098 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782098 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23542622277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23542622277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782113 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782113 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782252 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782252 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23523501277 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23523501277 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5052240750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5052240750 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28588153527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28588153527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589872527 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28589872527 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28575742027 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28575742027 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28577461027 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28577461027 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -541,69 +543,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33029.482302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33029.482302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33001.961693 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33001.961693 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72880.770174 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72880.770174 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36553.160252 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36553.160252 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36548.862464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36548.862464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36536.590016 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36536.590016 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36532.295254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36532.295254 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23596 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.064970 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23595 # number of replacements +system.cpu.icache.tags.tagsinuse 1710.136306 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 292011682 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11521.925584 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064970 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1710.136306 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 583983749 # Number of tag accesses -system.cpu.icache.tags.data_accesses 583983749 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 291953853 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 291953853 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 291953853 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 291953853 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 291953853 # number of overall hits -system.cpu.icache.overall_hits::total 291953853 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses -system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 499948995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 499948995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 499948995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 499948995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 499948995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 499948995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 291979201 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 291979201 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 291979201 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 291979201 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1601 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854004 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 584099398 # Number of tag accesses +system.cpu.icache.tags.data_accesses 584099398 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 292011682 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 292011682 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 292011682 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 292011682 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 292011682 # number of overall hits +system.cpu.icache.overall_hits::total 292011682 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25345 # number of overall misses +system.cpu.icache.overall_misses::total 25345 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 498945745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 498945745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 498945745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 498945745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 498945745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 498945745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 292037027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 292037027 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 292037027 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 292037027 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 292037027 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 292037027 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19723.409934 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19723.409934 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19723.409934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19723.409934 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19686.160781 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19686.160781 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19686.160781 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19686.160781 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19686.160781 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19686.160781 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,123 +614,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460820505 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 460820505 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460820505 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 460820505 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460820505 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 460820505 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25345 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25345 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25345 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25345 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25345 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25345 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 459825255 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 459825255 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 459825255 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 459825255 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 459825255 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 459825255 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18179.757969 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18179.757969 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18142.641744 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18142.641744 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18142.641744 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18142.641744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18142.641744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18142.641744 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257753 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32573.758043 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257749 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32573.780035 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 539008 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.855494 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231572 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601388 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925083 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2882.224162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.373270 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29602.182603 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994072 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.903387 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994073 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2793 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29433 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2792 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29435 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7551859 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7551859 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 22766 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 491022 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 513788 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7551951 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7551951 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 22768 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 491036 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 513804 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22766 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 494253 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517019 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22766 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 494253 # number of overall hits -system.cpu.l2cache.overall_hits::total 517019 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2582 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 221893 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224475 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 22768 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 494267 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517035 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22768 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 494267 # number of overall hits +system.cpu.l2cache.overall_hits::total 517035 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 221894 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2582 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290566 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses -system.cpu.l2cache.overall_misses::total 290566 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196430000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17675629250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17872059250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 196430000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22617911000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22814341000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 196430000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22617911000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22814341000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 2577 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 287985 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2577 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 287985 # number of overall misses +system.cpu.l2cache.overall_misses::total 290562 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 195416750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17656346250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17851763000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4948991250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4948991250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 195416750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22605337500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22800754250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 195416750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22605337500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22800754250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25345 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712930 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738275 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 25348 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782237 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 807585 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782237 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 807585 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101862 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311247 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.304058 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 25345 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782252 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 807597 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25345 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782252 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 807597 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101677 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311242 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.304048 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101862 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368154 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359796 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76076.684741 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79658.345464 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79617.147789 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78516.898054 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78516.898054 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101677 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368149 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359786 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101677 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368149 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359786 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75831.102057 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79571.084617 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79528.148402 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74881.470246 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74881.470246 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75831.102057 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78471.218707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75831.102057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78494.843481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78471.218707 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -748,105 +750,105 @@ system.cpu.l2cache.demand_mshr_hits::total 32 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2577 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221866 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224443 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2572 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221867 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2577 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287957 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290534 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163824250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14898374500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15062198750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163824250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19012312250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19176136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163824250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19012312250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19176136500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 162876000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14878894250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15041770250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4120650250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4120650250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 162876000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18999544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19162420500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 162876000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18999544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19162420500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304005 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63571.691890 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67150.327225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67109.238203 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359746 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101480 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359746 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63326.594090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67062.223089 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67019.413961 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62348.129851 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62348.129851 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63326.594090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65980.262747 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65956.770385 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 738275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738274 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55914048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57536256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50689 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55915008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899005 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 899005 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 899017 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38574495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38568245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224002973 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224009973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224442 # Transaction distribution -system.membus.trans_dist::ReadResp 224442 # Transaction distribution +system.membus.trans_dist::ReadReq 224438 # Transaction distribution +system.membus.trans_dist::ReadResp 224438 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647164 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647164 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356631 # Request fanout histogram +system.membus.snoop_fanout::samples 356627 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356631 # Request fanout histogram -system.membus.reqLayer0.occupancy 731518000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 356627 # Request fanout histogram +system.membus.reqLayer0.occupancy 732101500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551221500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551130500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 5365dab14..d04be0b82 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409399 # Number of seconds simulated -sim_ticks 409399480000 # Number of ticks simulated -final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.409388 # Number of seconds simulated +sim_ticks 409388341000 # Number of ticks simulated +final_tick 409388341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92444 # Simulator instruction rate (inst/s) -host_op_rate 113811 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59075206 # Simulator tick rate (ticks/s) -host_mem_usage 244496 # Number of bytes of host memory used -host_seconds 6930.14 # Real time elapsed on the host -sim_insts 640649298 # Number of instructions simulated -sim_ops 788724957 # Number of ops (including micro ops) simulated +host_inst_rate 75979 # Simulator instruction rate (inst/s) +host_op_rate 93540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48552243 # Simulator tick rate (ticks/s) +host_mem_usage 312124 # Number of bytes of host memory used +host_seconds 8431.91 # Real time elapsed on the host +sim_insts 640649299 # Number of instructions simulated +sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7025088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12938560 # Number of bytes read from this memory -system.physmem.bytes_read::total 20195840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244864 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315560 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66326 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66326 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 567153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17159494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31603753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49330400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 567153 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 567153 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10368513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10368513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10368513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 567153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17159494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31603753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59698913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315560 # Number of read requests accepted -system.physmem.writeReqs 66326 # Number of write requests accepted -system.physmem.readBursts 315560 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66326 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20177344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20195840 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19910 # Per bank write bursts -system.physmem.perBankRdBursts::1 19474 # Per bank write bursts -system.physmem.perBankRdBursts::2 19822 # Per bank write bursts -system.physmem.perBankRdBursts::3 19845 # Per bank write bursts -system.physmem.perBankRdBursts::4 19720 # Per bank write bursts -system.physmem.perBankRdBursts::5 20103 # Per bank write bursts -system.physmem.perBankRdBursts::6 19622 # Per bank write bursts -system.physmem.perBankRdBursts::7 19424 # Per bank write bursts -system.physmem.perBankRdBursts::8 19577 # Per bank write bursts -system.physmem.perBankRdBursts::9 19501 # Per bank write bursts -system.physmem.perBankRdBursts::10 19475 # Per bank write bursts -system.physmem.perBankRdBursts::11 19731 # Per bank write bursts -system.physmem.perBankRdBursts::12 19558 # Per bank write bursts -system.physmem.perBankRdBursts::13 20043 # Per bank write bursts -system.physmem.perBankRdBursts::14 19546 # Per bank write bursts -system.physmem.perBankRdBursts::15 19920 # Per bank write bursts -system.physmem.perBankWrBursts::0 4269 # Per bank write bursts -system.physmem.perBankWrBursts::1 4104 # Per bank write bursts -system.physmem.perBankWrBursts::2 4141 # Per bank write bursts -system.physmem.perBankWrBursts::3 4150 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 226496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory +system.physmem.bytes_read::total 20189120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315455 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 553255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17157303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31604769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49315327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 553255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 553255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10371297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10371297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10371297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 553255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17157303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31604769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59686624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315455 # Number of read requests accepted +system.physmem.writeReqs 66342 # Number of write requests accepted +system.physmem.readBursts 315455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20169536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20189120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19899 # Per bank write bursts +system.physmem.perBankRdBursts::1 19575 # Per bank write bursts +system.physmem.perBankRdBursts::2 19715 # Per bank write bursts +system.physmem.perBankRdBursts::3 19833 # Per bank write bursts +system.physmem.perBankRdBursts::4 19635 # Per bank write bursts +system.physmem.perBankRdBursts::5 20130 # Per bank write bursts +system.physmem.perBankRdBursts::6 19631 # Per bank write bursts +system.physmem.perBankRdBursts::7 19419 # Per bank write bursts +system.physmem.perBankRdBursts::8 19547 # Per bank write bursts +system.physmem.perBankRdBursts::9 19463 # Per bank write bursts +system.physmem.perBankRdBursts::10 19540 # Per bank write bursts +system.physmem.perBankRdBursts::11 19765 # Per bank write bursts +system.physmem.perBankRdBursts::12 19604 # Per bank write bursts +system.physmem.perBankRdBursts::13 19959 # Per bank write bursts +system.physmem.perBankRdBursts::14 19457 # Per bank write bursts +system.physmem.perBankRdBursts::15 19977 # Per bank write bursts +system.physmem.perBankWrBursts::0 4260 # Per bank write bursts +system.physmem.perBankWrBursts::1 4107 # Per bank write bursts +system.physmem.perBankWrBursts::2 4142 # Per bank write bursts +system.physmem.perBankWrBursts::3 4156 # Per bank write bursts system.physmem.perBankWrBursts::4 4244 # Per bank write bursts -system.physmem.perBankWrBursts::5 4227 # Per bank write bursts +system.physmem.perBankWrBursts::5 4228 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4095 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4154 # Per bank write bursts +system.physmem.perBankWrBursts::15 4150 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409399425500 # Total gap between requests +system.physmem.totGap 409388286500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315560 # Read request sizes (log2) +system.physmem.readPktSize::6 315455 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66326 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 117599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1337 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66342 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 122393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1340 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,158 +148,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 158 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.677557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.806703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.419690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53973 39.50% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57563 42.13% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14775 10.81% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1288 0.94% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1420 1.04% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1465 1.07% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1207 0.88% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1190 0.87% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3757 2.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136638 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.784581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.732770 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 517.054396 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4014 99.50% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.20% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 5 0.12% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 3 0.07% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.418691 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.384198 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.147646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3405 84.41% 84.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.17% 84.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 450 11.16% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 75 1.86% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 34 0.84% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 21 0.52% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 13 0.32% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 12 0.30% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.15% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads -system.physmem.totQLat 9487812639 # Total ticks spent queuing -system.physmem.totMemAccLat 15399143889 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1576355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30094.15 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.525503 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.653130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.190580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57416 42.00% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14736 10.78% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136711 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 449.952316 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3996 98.96% 98.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 21 0.52% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 8 0.20% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5631 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-14847 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4038 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4038 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.401932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.368431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.138933 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3429 84.92% 84.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.15% 85.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 436 10.80% 95.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 81 2.01% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 33 0.82% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 20 0.50% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.25% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 9 0.22% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads +system.physmem.totQLat 9474891317 # Total ticks spent queuing +system.physmem.totMemAccLat 15383935067 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1575745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30064.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48844.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 48814.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.33 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.47 # Data bus utilization in percentage -system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing -system.physmem.readRowHits 218399 # Number of row buffer hits during reads -system.physmem.writeRowHits 26454 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes -system.physmem.avgGap 1072046.17 # Average gap between requests -system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 517640760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 282442875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1231518600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216464400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96784987680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 160736987250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 286509617805 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.839198 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 266762765318 # Time in different power states -system.physmem_0.memoryStateTime::REF 13670540000 # Time in different power states +system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing +system.physmem.readRowHits 218193 # Number of row buffer hits during reads +system.physmem.writeRowHits 26465 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes +system.physmem.avgGap 1072266.90 # Average gap between requests +system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1231058400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216470880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96374211480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.719632 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 267357168520 # Time in different power states +system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128960598682 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 515168640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 281094000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1226955600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96280028955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 161179933500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 286435482375 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.658112 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 267502793659 # Time in different power states -system.physmem_1.memoryStateTime::REF 13670540000 # Time in different power states +system.physmem_1.actEnergy 514715040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280846500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 286420773645 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.635490 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 267598080337 # Time in different power states +system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 128220707341 # Time in different power states +system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234006176 # Number of BP lookups -system.cpu.branchPred.condPredicted 161868409 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514584 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121529948 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108213709 # Number of BTB hits +system.cpu.branchPred.lookups 233960254 # Number of BP lookups +system.cpu.branchPred.condPredicted 161822373 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121575796 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108259792 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.042833 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25036783 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300149 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.047159 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,84 +425,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 818798961 # number of cpu cycles simulated +system.cpu.numCycles 818776683 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84078294 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200783068 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234006176 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133250492 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718844861 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063585 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 84080283 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200690611 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233960254 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133296622 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718833631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3349 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370656305 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652882 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 818460793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.833394 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.163540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3279 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370702181 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652815 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 818451212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.833527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136795118 16.71% 16.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223180654 27.27% 43.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98074923 11.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360410098 44.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136785734 16.71% 16.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223134622 27.26% 43.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98075130 11.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360455726 44.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 818460793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285792 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.466518 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119991092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159658898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662986 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38629701 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518116 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25135087 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13824 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248129900 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39966537 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518116 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176998470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78894904 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 210510 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464956548 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81882245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190637892 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25457774 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24955109 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267146 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41533192 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1699566 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225425199 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812490436 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358169789 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876588 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 818451212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.466445 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119992571 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159648210 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662538 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38629741 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25181026 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248127712 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39967189 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 177000170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78888622 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464955823 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81877741 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190635480 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25549977 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1694220 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225376851 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812387634 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358166964 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350646969 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 350598621 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108140115 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366205100 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236096667 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1646330 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5328678 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168639452 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379926855 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.242727 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084979 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108139964 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366113107 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095924 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168545112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017136895 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18518107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379832511 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032101117 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 818451212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.242758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 260810349 31.87% 31.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227739162 27.83% 59.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216495712 26.45% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97269955 11.88% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16145606 1.97% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 260801504 31.87% 31.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227738074 27.83% 59.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216482418 26.45% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97282888 11.89% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16146319 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -503,43 +510,43 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 818460793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 818451212 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64512117 19.12% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18144 0.01% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155573719 46.11% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116674794 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155540663 46.10% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116678902 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456371749 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456370981 44.87% 44.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued @@ -564,100 +571,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322115143 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215585851 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478993 1.13% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322128329 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215587412 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017122920 # Type of FU issued -system.cpu.iq.rate 1.242213 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1505031237 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565815 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1017136895 # Type of FU issued +system.cpu.iq.rate 1.242264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337386313 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3146752380 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504842501 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934271178 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960122 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 1320712858 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113964162 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18388 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107116171 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113872169 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107115428 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065787 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22375 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518116 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35326355 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41902 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168657365 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35325435 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168563023 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366205100 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236096667 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 109 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 45517 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18388 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437362 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784555 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221917 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974750423 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42372497 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 366113107 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095924 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18393 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974751162 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297617 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42385733 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5553 # number of nop insts executed -system.cpu.iew.exec_refs 497763737 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613650 # Number of branches executed -system.cpu.iew.exec_stores 194466026 # Number of stores executed -system.cpu.iew.exec_rate 1.190464 # Inst execution rate -system.cpu.iew.wb_sent 963723367 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960423035 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536681402 # num instructions producing a value -system.cpu.iew.wb_consumers 893284482 # num instructions consuming a value +system.cpu.iew.exec_nop 5554 # number of nop insts executed +system.cpu.iew.exec_refs 497765227 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613464 # Number of branches executed +system.cpu.iew.exec_stores 194467610 # Number of stores executed +system.cpu.iew.exec_rate 1.190497 # Inst execution rate +system.cpu.iew.wb_sent 963723916 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960423621 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536680580 # num instructions producing a value +system.cpu.iew.wb_consumers 893282190 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.172966 # insts written-back per cycle +system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357409752 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357407190 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 767640271 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.027474 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786859 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 767630958 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.027486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786865 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 430932808 56.14% 56.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172476946 22.47% 78.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566678 9.58% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31624021 4.12% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8540196 1.11% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14250754 1.86% 95.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7269409 0.95% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6618976 0.86% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360483 2.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 430922921 56.14% 56.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172477665 22.47% 78.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31624091 4.12% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14250533 1.86% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360346 2.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 767640271 # Number of insts commited each cycle -system.cpu.commit.committedInsts 640654410 # Number of instructions committed -system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 767630958 # Number of insts commited each cycle +system.cpu.commit.committedInsts 640654411 # Number of instructions committed +system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 381221434 # Number of memory references committed system.cpu.commit.loads 252240938 # Number of loads committed system.cpu.commit.membars 5740 # Number of memory barriers committed -system.cpu.commit.branches 137364859 # Number of branches committed +system.cpu.commit.branches 137364860 # Number of branches committed system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. system.cpu.commit.function_calls 19275340 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction @@ -690,382 +697,382 @@ system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Cl system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1891410858 # The number of ROB reads -system.cpu.rob.rob_writes 2343104087 # The number of ROB writes -system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 338168 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 640649298 # Number of Instructions Simulated -system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.278077 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.278077 # CPI: Total CPI of All Threads -system.cpu.ipc 0.782426 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.782426 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995803851 # number of integer regfile reads -system.cpu.int_regfile_writes 567906934 # number of integer regfile writes +system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction +system.cpu.commit.bw_lim_events 22360346 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1891399121 # The number of ROB reads +system.cpu.rob.rob_writes 2343098694 # The number of ROB writes +system.cpu.timesIdled 647342 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 325471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 640649299 # Number of Instructions Simulated +system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads +system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995806500 # number of integer regfile reads +system.cpu.int_regfile_writes 567906149 # number of integer regfile writes system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794434058 # number of cc regfile reads -system.cpu.cc_regfile_writes 384899317 # number of cc regfile writes -system.cpu.misc_regfile_reads 715816288 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794435390 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898944 # number of cc regfile writes +system.cpu.misc_regfile_reads 715817585 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756182 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.932940 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414226912 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756694 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.262202 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2756184 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.932971 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414226707 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.262019 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.932940 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.932971 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839344268 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839344268 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286295518 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286295518 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127916671 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127916671 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3177 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3177 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839343974 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839343974 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286295255 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286295255 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127916705 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127916705 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3174 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3174 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414212189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414212189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414215366 # number of overall hits -system.cpu.dcache.overall_hits::total 414215366 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031489 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031489 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1034806 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1034806 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414211960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414211960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414215134 # number of overall hits +system.cpu.dcache.overall_hits::total 414215134 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031607 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031607 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1034772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1034772 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4066295 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4066295 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4066942 # number of overall misses -system.cpu.dcache.overall_misses::total 4066942 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35316006617 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35316006617 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10004118304 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10004118304 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 202750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 202750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45320124921 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45320124921 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45320124921 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45320124921 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289327007 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289327007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4066379 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4066379 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4067026 # number of overall misses +system.cpu.dcache.overall_misses::total 4067026 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35304231919 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35304231919 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981686625 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9981686625 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 189500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45285918544 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45285918544 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45285918544 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45285918544 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289326862 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289326862 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3824 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3824 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3821 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3821 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418278484 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418278484 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418282308 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418282308 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418278339 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418278339 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418282160 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418282160 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169195 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169195 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169327 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169327 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9667.626883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9667.626883 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11145.311622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11143.538541 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.385407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.385407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.266641 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.266641 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.669392 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11136.669392 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11134.897722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11134.897722 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 349732 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 343566 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5194 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5188 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 67.333847 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 66.223207 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735277 # number of writebacks -system.cpu.dcache.writebacks::total 735277 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996280 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 996280 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313945 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 313945 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735673 # number of writebacks +system.cpu.dcache.writebacks::total 735673 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996398 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 996398 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313907 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 313907 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1310225 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1310225 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1310225 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1310225 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1310305 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1310305 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1310305 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1310305 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720861 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720861 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720865 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720865 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756070 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756070 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756711 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756711 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23121613833 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23121613833 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5599042571 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5599042571 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5366500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5366500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28720656404 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28720656404 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28726022904 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28726022904 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23117834450 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23117834450 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596502782 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596502782 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5770003 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5770003 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714337232 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28714337232 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720107235 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28720107235 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167626 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167626 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167757 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167757 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11360.805614 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11360.805614 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7767.159787 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7767.159787 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8372.074883 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8372.074883 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10420.873346 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10420.873346 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10420.396953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10420.396953 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11358.948614 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11358.948614 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.593436 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.593436 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9001.564743 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9001.564743 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.565406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.565406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.235920 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.235920 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169874 # number of replacements -system.cpu.icache.tags.tagsinuse 510.641329 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 365482216 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5170384 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.687635 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 247770250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.641329 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997346 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997346 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169973 # number of replacements +system.cpu.icache.tags.tagsinuse 511.005918 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 365527993 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5170483 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.695135 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 247768250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.005918 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 746482947 # Number of tag accesses -system.cpu.icache.tags.data_accesses 746482947 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 365482251 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 365482251 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 365482251 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 365482251 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 365482251 # number of overall hits -system.cpu.icache.overall_hits::total 365482251 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174022 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174022 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174022 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174022 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174022 # number of overall misses -system.cpu.icache.overall_misses::total 5174022 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41654200685 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41654200685 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41654200685 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41654200685 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41654200685 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41654200685 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370656273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370656273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370656273 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370656273 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370656273 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370656273 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013959 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013959 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013959 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013959 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013959 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013959 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8050.642360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8050.642360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8050.642360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8050.642360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 76485 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 746574800 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746574800 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365528016 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365528016 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365528016 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 365528016 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 365528016 # number of overall hits +system.cpu.icache.overall_hits::total 365528016 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174133 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174133 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174133 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174133 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174133 # number of overall misses +system.cpu.icache.overall_misses::total 5174133 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647669446 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41647669446 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41647669446 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41647669446 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41647669446 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41647669446 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370702149 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370702149 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370702149 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370702149 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370702149 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370702149 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013958 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.207364 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8049.207364 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8049.207364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.207364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8049.207364 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75182 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3130 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.358280 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.019808 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3620 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3620 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3620 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3620 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3620 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3620 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170402 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170402 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170402 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170402 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170402 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170402 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36439121179 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36439121179 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36439121179 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36439121179 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36439121179 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36439121179 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013949 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013949 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013949 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7047.637917 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7047.637917 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3630 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3630 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3630 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3630 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3630 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3630 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170503 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5170503 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5170503 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5170503 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5170503 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5170503 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431563436 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36431563436 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431563436 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36431563436 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431563436 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36431563436 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013948 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013948 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013948 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.038545 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.038545 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.038545 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.038545 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1347058 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355234 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 7153 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 1347095 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1354943 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 6866 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790478 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 299258 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16361.552831 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7824313 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 315622 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.790138 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13409363000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 738.976811 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.067019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8785.583028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6707.925973 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.045104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007878 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.536229 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.409419 # Average percentage of cache occupancy +system.cpu.l2cache.prefetcher.pfSpanPage 4789921 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 299164 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16361.556320 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7824806 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 315528 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.799086 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13406100000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 743.987058 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512594 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582471 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474196 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.045409 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.535375 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410063 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6482 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9882 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1470 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4840 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6518 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 9846 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1451 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4880 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2079 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7315 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.395630 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.603149 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139634451 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139634451 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5166743 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1926167 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7092910 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 735277 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 735277 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2089 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7268 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397827 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600952 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139642343 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139642343 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5166932 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1926211 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7093143 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 735673 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 735673 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718012 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718012 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5166743 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2644179 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7810922 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5166743 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2644179 # number of overall hits -system.cpu.l2cache.overall_hits::total 7810922 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3643 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 109683 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 113326 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2832 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2832 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 112515 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 116158 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 112515 # number of overall misses -system.cpu.l2cache.overall_misses::total 116158 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 270029959 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8565404562 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8835434521 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 207607487 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 207607487 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 270029959 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8773012049 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9043042008 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 270029959 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8773012049 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9043042008 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170386 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 717988 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 717988 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5166932 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2644199 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7811131 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5166932 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2644199 # number of overall hits +system.cpu.l2cache.overall_hits::total 7811131 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3553 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 109639 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 113192 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2858 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2858 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3553 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 112497 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 116050 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3553 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 112497 # number of overall misses +system.cpu.l2cache.overall_misses::total 116050 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 261165964 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561744931 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8822910895 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 205223699 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 205223699 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 261165964 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8766968630 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9028134594 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 261165964 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8766968630 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9028134594 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170485 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7206236 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 735277 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 735277 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720844 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720844 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5170386 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756694 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7927080 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5170386 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756694 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7927080 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000705 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053876 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015726 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003929 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003929 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000705 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.040815 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014653 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000705 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.040815 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014653 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74122.964315 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.362189 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77964.761140 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::total 7206335 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 735673 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 735673 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5170485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756696 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7927181 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5170485 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756696 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7927181 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000687 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053854 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015707 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003965 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003965 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000687 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.040809 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014640 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000687 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.040809 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73505.759640 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78090.323069 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77946.417547 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71806.752624 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71806.752624 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77795.214080 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77795.214080 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1074,143 +1081,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66326 # number of writebacks -system.cpu.l2cache.writebacks::total 66326 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1303 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1318 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1445 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1445 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2748 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2748 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 2763 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3628 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108380 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 112008 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202241 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 202241 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 109767 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 113395 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 109767 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202241 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 315636 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 238098541 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7611970750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7850069291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17087057356 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 219516 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 219516 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114561754 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114561754 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238098541 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7726532504 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7964631045 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238098541 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7726532504 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25051688401 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053236 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 66342 # number of writebacks +system.cpu.l2cache.writebacks::total 66342 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1287 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1301 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1460 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1460 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2747 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2761 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2747 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2761 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111891 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202242 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202242 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1398 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1398 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3539 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109750 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3539 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 109750 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202242 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 315531 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230067036 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609571000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839638036 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17078829649 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 248018 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 248018 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114010508 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114010508 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230067036 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723581508 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7953648544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230067036 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723581508 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25032478193 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053222 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014305 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039817 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.715074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7206252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7206251 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735277 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 248818 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720844 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340787 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16589486 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330904640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223486144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554390784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 248834 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8911208 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.027922 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.164749 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 7206353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7206352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16590090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330910976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554422592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 248905 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8911778 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.027928 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 8662390 97.21% 97.21% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 248818 2.79% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 8662891 97.21% 97.21% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 248887 2.79% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8911208 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5066472000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8911778 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5067118500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756152507 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756291499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4138701196 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4138722865 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 314173 # Transaction distribution -system.membus.trans_dist::ReadResp 314173 # Transaction distribution -system.membus.trans_dist::Writeback 66326 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 1387 # Transaction distribution -system.membus.trans_dist::ReadExResp 1387 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697478 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24440704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24440704 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 314057 # Transaction distribution +system.membus.trans_dist::ReadResp 314057 # Transaction distribution +system.membus.trans_dist::Writeback 66342 # Transaction distribution +system.membus.trans_dist::UpgradeReq 18 # Transaction distribution +system.membus.trans_dist::UpgradeResp 18 # Transaction distribution +system.membus.trans_dist::ReadExReq 1398 # Transaction distribution +system.membus.trans_dist::ReadExResp 1398 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697288 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24435008 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381902 # Request fanout histogram +system.membus.snoop_fanout::samples 381815 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381902 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381815 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381902 # Request fanout histogram -system.membus.reqLayer0.occupancy 746879857 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381815 # Request fanout histogram +system.membus.reqLayer0.occupancy 746604866 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648874306 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1648190996 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index ba52b772d..790f4a782 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.395727 # Number of seconds simulated -sim_ticks 395726778000 # Number of ticks simulated -final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 395726778500 # Number of ticks simulated +final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1601804 # Simulator instruction rate (inst/s) -host_op_rate 1972032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 989420456 # Simulator tick rate (ticks/s) -host_mem_usage 309588 # Number of bytes of host memory used -host_seconds 399.96 # Real time elapsed on the host -sim_insts 640654410 # Number of instructions simulated -sim_ops 788730069 # Number of ops (including micro ops) simulated +host_inst_rate 1109777 # Simulator instruction rate (inst/s) +host_op_rate 1366282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 685499869 # Simulator tick rate (ticks/s) +host_mem_usage 303676 # Number of bytes of host memory used +host_seconds 577.28 # Real time elapsed on the host +sim_insts 640654411 # Number of instructions simulated +sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 2573511592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory -system.physmem.bytes_read::total 3718230108 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2573511592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2573511592 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 643377898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory -system.physmem.num_reads::total 893713136 # Number of read requests responded to by this memory +system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6503253596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2892699154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9395952750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6503253596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6503253596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1322421029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1322421029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 791453557 # number of cpu cycles simulated +system.cpu.numCycles 791453558 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 640654410 # Number of instructions committed -system.cpu.committedOps 788730069 # Number of ops (including micro ops) committed +system.cpu.committedInsts 640654411 # Number of instructions committed +system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses system.cpu.num_func_calls 37261296 # number of times a function call or return occured @@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 1320162254 # nu system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 2369173291 # number of times the CC registers were read +system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written system.cpu.num_mem_refs 381221435 # number of memory refs system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 791453556.998000 # Number of busy cycles +system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364859 # Number of branches fetched +system.cpu.Branches 137364860 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Cl system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730743 # Class of executed instruction -system.membus.trans_dist::ReadReq 893703777 # Transaction distribution -system.membus.trans_dist::ReadResp 893709516 # Transaction distribution +system.cpu.op_class::total 788730744 # Class of executed instruction +system.membus.trans_dist::ReadReq 893703778 # Transaction distribution +system.membus.trans_dist::ReadResp 893709517 # Transaction distribution system.membus.trans_dist::WriteReq 128951477 # Transaction distribution system.membus.trans_dist::WriteResp 128951477 # Transaction distribution system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution @@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 3620 # Tr system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram +system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::3 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::3 643377899 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 1022670352 # Request fanout histogram +system.membus.snoop_fanout::total 1022670353 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e078716d2..e0c0a3846 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.043695 # Number of seconds simulated -sim_ticks 1043695077500 # Number of ticks simulated -final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1043695078500 # Number of ticks simulated +final_tick 1043695078500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 877071 # Simulator instruction rate (inst/s) -host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1431720298 # Simulator tick rate (ticks/s) -host_mem_usage 317788 # Number of bytes of host memory used -host_seconds 728.98 # Real time elapsed on the host -sim_insts 639366786 # Number of instructions simulated -sim_ops 785501034 # Number of ops (including micro ops) simulated +host_inst_rate 624059 # Simulator instruction rate (inst/s) +host_op_rate 766694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1018706197 # Simulator tick rate (ticks/s) +host_mem_usage 313408 # Number of bytes of host memory used +host_seconds 1024.53 # Real time elapsed on the host +sim_insts 639366787 # Number of instructions simulated +sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18428352 # Number of bytes read from this memory system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287943 # Number of read requests responded to by this memory system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17656835 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108476 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17656835 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -154,11 +154,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087390155 # number of cpu cycles simulated +system.cpu.numCycles 2087390157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 639366786 # Number of instructions committed -system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed +system.cpu.committedInsts 639366787 # Number of instructions committed +system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses system.cpu.num_func_calls 37261296 # number of times a function call or return occured @@ -169,18 +169,18 @@ system.cpu.num_int_register_reads 1323974869 # nu system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read +system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written system.cpu.num_mem_refs 381221435 # number of memory refs system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087390156.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364859 # Number of branches fetched +system.cpu.Branches 137364860 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction @@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Cl system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640584 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996415000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640584 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582740000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18582740000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22259892000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22259892000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22259892000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22259892000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.414780 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.414780 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.189436 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28465.189436 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.130692 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28460.130692 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513680000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513680000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086847500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21086847500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088530000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21088530000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.395241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.395241 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.174686 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.174686 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.533658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.533658 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1391.464501 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464501 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -367,44 +367,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 43 system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits -system.cpu.icache.overall_hits::total 643367691 # number of overall hits +system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits +system.cpu.icache.overall_hits::total 643367692 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207074000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207074000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207074000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207074000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20285.462382 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20285.462382 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20285.462382 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20285.462382 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,37 +419,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191762000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191762000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191762000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191762000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191762000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191762000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18785.462382 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18785.462382 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18785.462382 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18785.462382 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18785.462382 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18785.462382 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 256932 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32626.698157 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.076488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.116225 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.908970 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id @@ -460,40 +460,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7430286 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8438 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 490970 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 8439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 490969 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 499408 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91561 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8438 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 494200 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 494199 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 502638 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8438 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 494200 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 8439 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 494199 # number of overall hits system.cpu.l2cache.overall_hits::total 502638 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1770 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 221849 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 1769 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 221850 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 223619 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1770 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 287942 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 1769 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 287943 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 289712 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 1769 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 287943 # number of overall misses system.cpu.l2cache.overall_misses::total 289712 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92997000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647316500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92944500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647369000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 11740313500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469929500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3469929500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92997000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15117246000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 92944500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15117298500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92997000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15117246000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 92944500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15117298500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) @@ -508,27 +508,27 @@ system.cpu.l2cache.demand_accesses::total 792350 # n system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.173393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311228 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.173295 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311229 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.309282 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173393 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368145 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173295 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368147 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.365636 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173295 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.700961 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099842 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.700961 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010617 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.700961 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010617 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -540,48 +540,48 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1770 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221849 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1769 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221850 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 223619 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1770 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287942 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287943 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1769 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287943 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71648500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984925000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71648500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661691500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71648500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661691500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311229 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.261164 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |