diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/40.perlbmk/ref/arm | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm')
3 files changed, 1588 insertions, 1535 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 5b9278fb0..cc0a8b561 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541773 # Number of seconds simulated -sim_ticks 541773299500 # Number of ticks simulated -final_tick 541773299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541068 # Number of seconds simulated +sim_ticks 541067717500 # Number of ticks simulated +final_tick 541067717500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180126 # Simulator instruction rate (inst/s) -host_op_rate 221759 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152324877 # Simulator tick rate (ticks/s) -host_mem_usage 323140 # Number of bytes of host memory used -host_seconds 3556.70 # Real time elapsed on the host +host_inst_rate 180313 # Simulator instruction rate (inst/s) +host_op_rate 221989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152283805 # Simulator tick rate (ticks/s) +host_mem_usage 322972 # Number of bytes of host memory used +host_seconds 3553.02 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18429120 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164800 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470272 # Number of bytes read from this memory +system.physmem.bytes_read::total 18635008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164736 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2575 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287955 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2574 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288598 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291172 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 304186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34016294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34320481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 304186 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 304186 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808196 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808196 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 304186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34016294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42128676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290530 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 304465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34136710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34441175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 304465 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 304465 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7818378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7818378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7818378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 304465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34136710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42259553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291172 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290530 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291172 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593920 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18613824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18635008 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18136 # Per bank write bursts -system.physmem.perBankRdBursts::2 18223 # Per bank write bursts -system.physmem.perBankRdBursts::3 18182 # Per bank write bursts -system.physmem.perBankRdBursts::4 18272 # Per bank write bursts -system.physmem.perBankRdBursts::5 18313 # Per bank write bursts -system.physmem.perBankRdBursts::6 18098 # Per bank write bursts -system.physmem.perBankRdBursts::7 17913 # Per bank write bursts -system.physmem.perBankRdBursts::8 17942 # Per bank write bursts -system.physmem.perBankRdBursts::9 17963 # Per bank write bursts -system.physmem.perBankRdBursts::10 18020 # Per bank write bursts -system.physmem.perBankRdBursts::11 18117 # Per bank write bursts -system.physmem.perBankRdBursts::12 18146 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18079 # Per bank write bursts -system.physmem.perBankRdBursts::15 18260 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4100 # Per bank write bursts -system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts -system.physmem.perBankWrBursts::5 4225 # Per bank write bursts -system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankRdBursts::0 18282 # Per bank write bursts +system.physmem.perBankRdBursts::1 18127 # Per bank write bursts +system.physmem.perBankRdBursts::2 18214 # Per bank write bursts +system.physmem.perBankRdBursts::3 18173 # Per bank write bursts +system.physmem.perBankRdBursts::4 18274 # Per bank write bursts +system.physmem.perBankRdBursts::5 18402 # Per bank write bursts +system.physmem.perBankRdBursts::6 18180 # Per bank write bursts +system.physmem.perBankRdBursts::7 17989 # Per bank write bursts +system.physmem.perBankRdBursts::8 18022 # Per bank write bursts +system.physmem.perBankRdBursts::9 18061 # Per bank write bursts +system.physmem.perBankRdBursts::10 18102 # Per bank write bursts +system.physmem.perBankRdBursts::11 18198 # Per bank write bursts +system.physmem.perBankRdBursts::12 18215 # Per bank write bursts +system.physmem.perBankRdBursts::13 18265 # Per bank write bursts +system.physmem.perBankRdBursts::14 18078 # Per bank write bursts +system.physmem.perBankRdBursts::15 18259 # Per bank write bursts +system.physmem.perBankWrBursts::0 4171 # Per bank write bursts +system.physmem.perBankWrBursts::1 4098 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4223 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::7 4092 # Per bank write bursts system.physmem.perBankWrBursts::8 4093 # Per bank write bursts -system.physmem.perBankWrBursts::9 4092 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4095 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4096 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541773205000 # Total gap between requests +system.physmem.totGap 541067624000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290530 # Read request sizes (log2) +system.physmem.readPktSize::6 291172 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,96 +193,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 112123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 203.355529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.415015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 254.574164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47170 42.07% 42.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43612 38.90% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9039 8.06% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1917 1.71% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 483 0.43% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 738 0.66% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 730 0.65% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 502 0.45% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7932 7.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 112123 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.524570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.058155 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.570273 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 110882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.996862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.129754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.860056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45611 41.13% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43911 39.60% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9208 8.30% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1504 1.36% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 772 0.70% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 428 0.39% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 846 0.76% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 594 0.54% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8008 7.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 110882 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.509335 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.234035 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.719748 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.480918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.459590 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.855706 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3046 75.98% 75.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 961 23.97% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads -system.physmem.totQLat 2883248250 # Total ticks spent queuing -system.physmem.totMemAccLat 8324929500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9934.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.446602 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.426400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.833021 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3120 77.67% 77.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 897 22.33% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads +system.physmem.totQLat 3065169000 # Total ticks spent queuing +system.physmem.totMemAccLat 8518437750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10538.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28684.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29288.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.18 # Average write queue length when enqueuing -system.physmem.readRowHits 194064 # Number of row buffer hits during reads -system.physmem.writeRowHits 50094 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 1519154.99 # Average gap between requests -system.physmem.pageHitRate 68.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 423874080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 231280500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1134198000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215622000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107588305125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 230684814750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375663699255 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.403859 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383052702750 # Time in different power states -system.physmem_0.memoryStateTime::REF 18090800000 # Time in different power states +system.physmem.avgWrQLen 28.63 # Average write queue length when enqueuing +system.physmem.readRowHits 194425 # Number of row buffer hits during reads +system.physmem.writeRowHits 51597 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 1514450.20 # Average gap between requests +system.physmem.pageHitRate 68.93 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 420041160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229189125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1135976400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 108869403780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 229140586500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375350562645 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.723181 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 380482098250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18067400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140624192250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142518050750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 423692640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231181500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1129104600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212524560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35385604800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 107075040930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 231135046500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 375592195530 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.271876 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 383804077000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18090800000 # Time in different power states +system.physmem_1.actEnergy 418226760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228199125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132497600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212576400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 107776907010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230098917000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 375207158295 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.458141 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 382081982750 # Time in different power states +system.physmem_1.memoryStateTime::REF 18067400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 139874284500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 140917403500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 156119313 # Number of BP lookups -system.cpu.branchPred.condPredicted 106151666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12881666 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90098747 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82494804 # Number of BTB hits +system.cpu.branchPred.lookups 157565509 # Number of BP lookups +system.cpu.branchPred.condPredicted 107229273 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12892751 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 98103751 # Number of BTB lookups +system.cpu.branchPred.BTBHits 81778311 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.560434 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19276925 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1327 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.359005 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19318729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1315 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -401,69 +399,69 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083546599 # number of cpu cycles simulated +system.cpu.numCycles 1082135435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23911488 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23942424 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691310 # CPI: cycles per instruction -system.cpu.ipc 0.591258 # IPC: instructions per cycle -system.cpu.tickCycles 1025165387 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58381212 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778275 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.437677 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378454072 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782371 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.727122 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 802618250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.437677 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999130 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999130 # Average percentage of cache occupancy +system.cpu.cpi 1.689108 # CPI: cycles per instruction +system.cpu.ipc 0.592029 # IPC: instructions per cycle +system.cpu.tickCycles 1024380125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57755310 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778330 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.458630 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378454621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782426 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.693820 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 795587500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.458630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999135 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999135 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1345 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1346 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1586 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759393811 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759393811 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249625343 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249625343 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 759395078 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759395078 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249625893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249625893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378439109 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378439109 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378442594 # number of overall hits -system.cpu.dcache.overall_hits::total 378442594 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713796 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713796 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 378439658 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378439658 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378443143 # number of overall hits +system.cpu.dcache.overall_hits::total 378443143 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713852 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713852 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 851507 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851507 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851648 # number of overall misses -system.cpu.dcache.overall_misses::total 851648 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24839025218 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24839025218 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10202615750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10202615750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35041640968 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35041640968 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35041640968 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35041640968 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250339139 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250339139 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 851564 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851564 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851705 # number of overall misses +system.cpu.dcache.overall_misses::total 851705 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24973506500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24973506500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10064105500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10064105500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35037612000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35037612000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35037612000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35037612000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250339745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250339745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) @@ -472,12 +470,12 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379290616 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379290616 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379294242 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379294242 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 379291222 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379291222 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379294848 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379294848 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses @@ -486,14 +484,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34798.493152 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34798.493152 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74087.151716 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74087.151716 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41152.499002 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41152.499002 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41145.685739 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41145.685739 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34984.151477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34984.151477 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73080.817213 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73080.817213 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41145.013176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41145.013176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41138.201607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41138.201607 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,36 +500,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks -system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 886 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 886 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69275 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69275 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69275 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69275 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712910 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712910 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 88940 # number of writebacks +system.cpu.dcache.writebacks::total 88940 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 887 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 887 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69277 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69277 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69277 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69277 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712965 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712965 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782232 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782232 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782371 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782371 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23683196777 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23683196777 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5051765250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5051765250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28734962027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28734962027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28736681027 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28736681027 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782287 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782287 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782426 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782426 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24245308500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24245308500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5047418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5047418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29292727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29292727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29294515000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29294515000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -542,69 +540,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33220.458090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33220.458090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72873.910880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72873.910880 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36734.577500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36734.577500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36730.248216 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36730.248216 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34006.309566 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34006.309566 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72811.207120 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72811.207120 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37444.987581 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37444.987581 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37440.620583 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37440.620583 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23596 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.059457 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 290105857 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11445.372510 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23593 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.048816 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 288484492 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11382.752999 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.059457 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835967 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835967 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.048816 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1603 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 580287757 # Number of tag accesses -system.cpu.icache.tags.data_accesses 580287757 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 290105857 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 290105857 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 290105857 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 290105857 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 290105857 # number of overall hits -system.cpu.icache.overall_hits::total 290105857 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses -system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 499853745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 499853745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 499853745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 499853745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 499853745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 499853745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290131205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290131205 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290131205 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290131205 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290131205 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290131205 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19719.652241 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19719.652241 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19719.652241 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19719.652241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19719.652241 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19719.652241 # average overall miss latency +system.cpu.icache.tags.tag_accesses 577045018 # Number of tag accesses +system.cpu.icache.tags.data_accesses 577045018 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 288484492 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288484492 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288484492 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288484492 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288484492 # number of overall hits +system.cpu.icache.overall_hits::total 288484492 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25345 # number of overall misses +system.cpu.icache.overall_misses::total 25345 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499936000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499936000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499936000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499936000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499936000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499936000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288509837 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288509837 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288509837 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288509837 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288509837 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288509837 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19725.231801 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19725.231801 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19725.231801 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19725.231801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19725.231801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19725.231801 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,123 +611,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460727755 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 460727755 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460727755 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 460727755 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460727755 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 460727755 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18176.098903 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18176.098903 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18176.098903 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18176.098903 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18176.098903 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18176.098903 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25345 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25345 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25345 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25345 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25345 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25345 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 474592000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 474592000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 474592000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 474592000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 474592000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 474592000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000088 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000088 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000088 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18725.271257 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18725.271257 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18725.271257 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18725.271257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18725.271257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18725.271257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257750 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32572.840203 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 539129 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.855904 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258392 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32574.171271 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1245331 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291136 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.277489 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2880.993603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.456847 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29602.389753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087921 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002730 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.903393 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994044 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.797972 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.410409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29893.962890 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.079034 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.912291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994085 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2810 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2812 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29416 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7552928 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7552928 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 22767 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 491158 # 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mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359693 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368054 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359693 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63562.888199 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67777.834619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67729.457762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62340.897399 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62340.897399 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63562.888199 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66529.956938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66503.649352 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101598 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312026 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312026 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64284.062883 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64284.062883 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66615.728155 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66615.728155 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71005.527916 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71005.527916 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 901935 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656162 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706857 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55922624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57544832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899139 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 25345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 713104 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2414122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55767424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57389440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258392 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1868086 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 899139 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1609694 86.17% 86.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 258392 13.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899139 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 540989500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38573245 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1868086 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 893787000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 38017996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224491973 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173652972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224439 # Transaction distribution -system.membus.trans_dist::ReadResp 224439 # Transaction distribution +system.membus.trans_dist::ReadResp 225081 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190637 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647158 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824192 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225081 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839079 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839079 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22865280 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356628 # Request fanout histogram +system.membus.snoop_fanout::samples 547907 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356628 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 547907 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356628 # Request fanout histogram -system.membus.reqLayer0.occupancy 731800000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1550863750 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 547907 # Request fanout histogram +system.membus.reqLayer0.occupancy 916769500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1554235250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index bdaafd38c..95f0885fc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409388 # Number of seconds simulated -sim_ticks 409388416000 # Number of ticks simulated -final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410927 # Number of seconds simulated +sim_ticks 410926760000 # Number of ticks simulated +final_tick 410926760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93306 # Simulator instruction rate (inst/s) -host_op_rate 114872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59624294 # Simulator tick rate (ticks/s) -host_mem_usage 320320 # Number of bytes of host memory used -host_seconds 6866.13 # Real time elapsed on the host +host_inst_rate 92513 # Simulator instruction rate (inst/s) +host_op_rate 113896 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59339858 # Simulator tick rate (ticks/s) +host_mem_usage 320156 # Number of bytes of host memory used +host_seconds 6924.97 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315456 # Number of read requests accepted -system.physmem.writeReqs 66342 # Number of write requests accepted -system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19899 # Per bank write bursts -system.physmem.perBankRdBursts::1 19575 # Per bank write bursts -system.physmem.perBankRdBursts::2 19715 # Per bank write bursts -system.physmem.perBankRdBursts::3 19833 # Per bank write bursts -system.physmem.perBankRdBursts::4 19635 # Per bank write bursts -system.physmem.perBankRdBursts::5 20130 # Per bank write bursts -system.physmem.perBankRdBursts::6 19631 # Per bank write bursts -system.physmem.perBankRdBursts::7 19419 # Per bank write bursts -system.physmem.perBankRdBursts::8 19547 # Per bank write bursts -system.physmem.perBankRdBursts::9 19463 # Per bank write bursts -system.physmem.perBankRdBursts::10 19540 # Per bank write bursts -system.physmem.perBankRdBursts::11 19765 # Per bank write bursts -system.physmem.perBankRdBursts::12 19604 # Per bank write bursts -system.physmem.perBankRdBursts::13 19959 # Per bank write bursts -system.physmem.perBankRdBursts::14 19457 # Per bank write bursts -system.physmem.perBankRdBursts::15 19978 # Per bank write bursts -system.physmem.perBankWrBursts::0 4260 # Per bank write bursts -system.physmem.perBankWrBursts::1 4107 # Per bank write bursts -system.physmem.perBankWrBursts::2 4142 # Per bank write bursts -system.physmem.perBankWrBursts::3 4156 # Per bank write bursts -system.physmem.perBankWrBursts::4 4244 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 227008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7012480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12950080 # Number of bytes read from this memory +system.physmem.bytes_read::total 20189568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245632 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3547 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202345 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315462 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66338 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66338 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 552429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17065036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31514326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49131792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10331846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10331846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10331846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17065036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31514326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59463638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315462 # Number of read requests accepted +system.physmem.writeReqs 66338 # Number of write requests accepted +system.physmem.readBursts 315462 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66338 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20169664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4239360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20189568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 69 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19798 # Per bank write bursts +system.physmem.perBankRdBursts::1 19540 # Per bank write bursts +system.physmem.perBankRdBursts::2 19718 # Per bank write bursts +system.physmem.perBankRdBursts::3 19803 # Per bank write bursts +system.physmem.perBankRdBursts::4 19742 # Per bank write bursts +system.physmem.perBankRdBursts::5 20227 # Per bank write bursts +system.physmem.perBankRdBursts::6 19591 # Per bank write bursts +system.physmem.perBankRdBursts::7 19445 # Per bank write bursts +system.physmem.perBankRdBursts::8 19492 # Per bank write bursts +system.physmem.perBankRdBursts::9 19431 # Per bank write bursts +system.physmem.perBankRdBursts::10 19416 # Per bank write bursts +system.physmem.perBankRdBursts::11 19789 # Per bank write bursts +system.physmem.perBankRdBursts::12 19620 # Per bank write bursts +system.physmem.perBankRdBursts::13 20020 # Per bank write bursts +system.physmem.perBankRdBursts::14 19553 # Per bank write bursts +system.physmem.perBankRdBursts::15 19966 # Per bank write bursts +system.physmem.perBankWrBursts::0 4272 # Per bank write bursts +system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4154 # Per bank write bursts +system.physmem.perBankWrBursts::4 4243 # Per bank write bursts system.physmem.perBankWrBursts::5 4228 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4095 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts @@ -83,38 +83,38 @@ system.physmem.perBankWrBursts::11 4097 # Pe system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4150 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409388361500 # Total gap between requests +system.physmem.totGap 410926705500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315456 # Read request sizes (log2) +system.physmem.readPktSize::6 315462 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66342 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1340 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66338 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 125674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 115954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 985 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,165 +148,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 449.952316 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3996 98.96% 98.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 21 0.52% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 8 0.20% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 136743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.487469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.645908 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.261259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54158 39.61% 39.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57478 42.03% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14696 10.75% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1431 1.05% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1373 1.00% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1481 1.08% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1196 0.87% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1150 0.84% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3780 2.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136743 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 66.735038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.718214 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 464.978559 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3992 99.13% 99.13% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 4 0.10% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 3 0.07% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 4 0.10% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 2 0.05% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-5631 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4038 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.401932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.368431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.138933 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3429 84.92% 84.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.15% 85.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 436 10.80% 95.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 81 2.01% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 33 0.82% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 20 0.50% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 9 0.22% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads -system.physmem.totQLat 9474850817 # Total ticks spent queuing -system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::8192-8703 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 2 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4027 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.448969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.407245 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.299266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3382 83.98% 83.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 84.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 453 11.25% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 103 2.56% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.50% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.47% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.25% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.27% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.20% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.12% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4027 # Writes before turning the bus around for reads +system.physmem.totQLat 8985315314 # Total ticks spent queuing +system.physmem.totMemAccLat 14894396564 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1575755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28511.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47261.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.13 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.47 # Data bus utilization in percentage +system.physmem.busUtil 0.46 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 218195 # Number of row buffer hits during reads -system.physmem.writeRowHits 26465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes -system.physmem.avgGap 1072264.29 # Average gap between requests -system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ) +system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing +system.physmem.readRowHits 218304 # Number of row buffer hits during reads +system.physmem.writeRowHits 26331 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.73 # Row buffer hit rate for writes +system.physmem.avgGap 1076287.86 # Average gap between requests +system.physmem.pageHitRate 64.14 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 518260680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282781125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1231058400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216470880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96374211480 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.719632 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states -system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states +system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96516777600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161887922250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 287492576775 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.632177 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 268678979341 # Time in different power states +system.physmem_0.memoryStateTime::REF 13721500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128519138159 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.635519 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states -system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states +system.physmem_1.actEnergy 515334960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 281184750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1226448600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212712480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96027774030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 162316872750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 287419581570 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.454538 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 269400106911 # Time in different power states +system.physmem_1.memoryStateTime::REF 13721500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127799659089 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233960267 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits +system.cpu.branchPred.lookups 233961600 # Number of BP lookups +system.cpu.branchPred.condPredicted 161823435 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514478 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121576875 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108260850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.047239 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25036809 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300056 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,129 +427,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 818776833 # number of cpu cycles simulated +system.cpu.numCycles 821853521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85352108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200709266 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233961600 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133297659 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 720636600 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063377 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2846 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370706156 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652600 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 821526595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.826688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.166658 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 139803220 17.02% 17.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223204281 27.17% 44.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98088574 11.94% 56.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360430520 43.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 821526595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284676 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.460977 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121268240 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 161448420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484660246 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38631680 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518009 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25181996 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13829 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248138563 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966565 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518009 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178275276 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80711720 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 210548 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319817 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82491225 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190650018 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25545971 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24926226 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267555 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41530027 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1673344 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225393242 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812447453 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358179782 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 350615012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7270 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108779302 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366116842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236096763 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1776884 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5334939 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168558899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017090766 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18380245 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379846300 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032153355 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 821526595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.238050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084805 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 263868507 32.12% 32.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227113166 27.65% 59.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217783209 26.51% 86.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96635677 11.76% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16126029 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 821526595 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63875827 18.90% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 157407577 46.57% 65.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116033793 34.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456370958 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195826 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -569,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478993 1.13% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478994 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322082825 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215586812 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued -system.cpu.iq.rate 1.242264 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017090766 # Type of FU issued +system.cpu.iq.rate 1.237557 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337972229 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332293 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3150183586 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504870139 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934273978 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877015 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565815 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1321252671 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810324 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960626 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113875904 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18399 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065816 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 20694 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518009 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35327000 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41213 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168576814 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18393 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.iewDispLoadInsts 366116842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236096763 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 44806 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18399 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437241 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784654 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 974751722 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303298002 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42339044 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5554 # number of nop insts executed -system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613469 # Number of branches executed -system.cpu.iew.exec_stores 194467616 # Number of stores executed -system.cpu.iew.exec_rate 1.190497 # Inst execution rate -system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536680583 # num instructions producing a value -system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value +system.cpu.iew.exec_nop 5556 # number of nop insts executed +system.cpu.iew.exec_refs 497764632 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613642 # Number of branches executed +system.cpu.iew.exec_stores 194466630 # Number of stores executed +system.cpu.iew.exec_rate 1.186041 # Inst execution rate +system.cpu.iew.wb_sent 963724701 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960426422 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536047355 # num instructions producing a value +system.cpu.iew.wb_consumers 893284415 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back +system.cpu.iew.wb_rate 1.168610 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357420349 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500799 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770704967 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.023388 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.776993 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 432077450 56.06% 56.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174390434 22.63% 78.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72936884 9.46% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32898197 4.27% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538905 1.11% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14258273 1.85% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269904 0.94% 96.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5974492 0.78% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360428 2.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 767631497 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770704967 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,383 +700,389 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360345 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1891399680 # The number of ROB reads -system.cpu.rob.rob_writes 2343098733 # The number of ROB writes -system.cpu.timesIdled 647345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 325081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360428 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1894486207 # The number of ROB reads +system.cpu.rob.rob_writes 2343126387 # The number of ROB writes +system.cpu.timesIdled 647317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326926 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads -system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995806519 # number of integer regfile reads -system.cpu.int_regfile_writes 567906159 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794435468 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898950 # number of cc regfile writes -system.cpu.misc_regfile_reads 715817595 # number of misc regfile reads +system.cpu.cpi 1.282845 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282845 # CPI: Total CPI of All Threads +system.cpu.ipc 0.779518 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.779518 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995802121 # number of integer regfile reads +system.cpu.int_regfile_writes 567908278 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794438886 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898194 # number of cc regfile writes +system.cpu.misc_regfile_reads 715817246 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes system.cpu.dcache.tags.replacements 2756184 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.932971 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414226712 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.933712 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414215984 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.262021 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.932971 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 150.258129 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 256316000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.933712 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999871 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999871 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839343984 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839343984 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286295259 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286295259 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127916705 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127916705 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3174 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3174 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839346446 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839346446 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293586 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293586 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907704 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907704 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414211964 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414211964 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414215138 # number of overall hits -system.cpu.dcache.overall_hits::total 414215138 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031608 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031608 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1034772 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1034772 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414201290 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414201290 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414204447 # number of overall hits +system.cpu.dcache.overall_hits::total 414204447 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3034530 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3034530 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043773 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043773 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4066380 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4066380 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4067027 # number of overall misses -system.cpu.dcache.overall_misses::total 4067027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35305181420 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35305181420 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981703626 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9981703626 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 189500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45286885046 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45286885046 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45286885046 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45286885046 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289326867 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289326867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4078303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4078303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4078949 # number of overall misses +system.cpu.dcache.overall_misses::total 4078949 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35233063500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35233063500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9908998850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9908998850 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45142062350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45142062350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45142062350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45142062350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328116 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3821 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3821 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418278344 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418278344 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418282165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418282165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169327 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169327 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418279593 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279593 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283396 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283396 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008094 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008094 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.283071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.283071 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11136.904334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11135.132628 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009750 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009750 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009752 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009752 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11610.715168 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11610.715168 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9493.442396 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9493.442396 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11068.834844 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11068.834844 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11067.081827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11067.081827 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 343566 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 326278 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5188 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 66.223207 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 67.011296 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735673 # number of writebacks -system.cpu.dcache.writebacks::total 735673 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 996399 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313907 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 313907 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735190 # number of writebacks +system.cpu.dcache.writebacks::total 735190 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999322 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999322 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322910 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 322910 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1310306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1310306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1310306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1310306 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720865 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720865 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1322232 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1322232 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1322232 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1322232 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035208 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035208 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720863 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720863 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23118028700 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23118028700 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596519781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596519781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5770003 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5770003 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714548481 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28714548481 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720318484 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28720318484 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756071 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756712 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756712 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24098858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24098858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5945182850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5945182850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6199500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6199500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30044041350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30044041350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30050240850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30050240850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167757 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167757 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.617017 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.617017 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9001.564743 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9001.564743 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.980627 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.980627 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8247.313082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8247.313082 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9671.606864 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9671.606864 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10901.040412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10901.040412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10900.754540 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10900.754540 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169974 # number of replacements -system.cpu.icache.tags.tagsinuse 511.005918 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 365528009 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5170484 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.695124 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 247768250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.005918 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998058 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169094 # number of replacements +system.cpu.icache.tags.tagsinuse 511.159465 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 365531814 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169604 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.707894 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 246618500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.159465 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998358 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998358 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 746574831 # Number of tag accesses -system.cpu.icache.tags.data_accesses 746574831 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 365528032 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 365528032 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 365528032 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 365528032 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 365528032 # number of overall hits -system.cpu.icache.overall_hits::total 365528032 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174132 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174132 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174132 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174132 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174132 # number of overall misses -system.cpu.icache.overall_misses::total 5174132 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647443196 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41647443196 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41647443196 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41647443196 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41647443196 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41647443196 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370702164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370702164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370702164 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370702164 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370702164 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370702164 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 746581864 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746581864 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365531869 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365531869 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365531869 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 365531869 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 365531869 # number of overall hits +system.cpu.icache.overall_hits::total 365531869 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174253 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174253 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174253 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174253 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174253 # number of overall misses +system.cpu.icache.overall_misses::total 5174253 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41642635922 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41642635922 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41642635922 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41642635922 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41642635922 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41642635922 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370706122 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370706122 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370706122 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370706122 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370706122 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370706122 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013958 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8049.165193 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8049.165193 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8049.165193 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8049.165193 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8049.165193 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 75254 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3130 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.047887 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8048.047887 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.047887 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8048.047887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.047887 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8048.047887 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 80330 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3828 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.042812 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.984848 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3628 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3628 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3628 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3628 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3628 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3628 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170504 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170504 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170504 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170504 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170504 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170504 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36431387686 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36431387686 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36431387686 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36431387686 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36431387686 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36431387686 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013948 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013948 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013948 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013948 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7046.003192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7046.003192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7046.003192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7046.003192 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4632 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4632 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4632 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4632 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4632 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4632 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5169621 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169621 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5169621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5169621 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39011263436 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39011263436 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39011263436 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39011263436 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39011263436 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39011263436 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013945 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013945 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013945 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7546.252121 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7546.252121 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7546.252121 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7546.252121 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7546.252121 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7546.252121 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1347095 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1354943 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 6866 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 1349196 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355261 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 5306 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4789921 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 299165 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16361.556320 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7824806 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 315529 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.799007 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13406100000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 743.986923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.512620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8771.582614 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6718.474164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.045409 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.535375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410063 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6520 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9844 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1454 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4880 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2085 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7271 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.397949 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.600830 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139642360 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139642360 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5166932 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1926211 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7093143 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 735673 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 735673 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 717988 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 717988 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5166932 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2644199 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7811131 # 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number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3554 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 112497 # number of overall misses -system.cpu.l2cache.overall_misses::total 116051 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 260989714 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8561938681 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8822928395 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 205223699 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 205223699 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 260989714 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8767162380 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9028152094 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 260989714 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8767162380 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9028152094 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170486 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7206336 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 735673 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 735673 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 19 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 123342500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 123342500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 239801000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 239801000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7820358000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7820358000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 239801000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7943700500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8183501500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 239801000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7943700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17045778133 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25229279633 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001934 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001934 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053136 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053136 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039809 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84209.534253 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16781.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16781.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88480.989957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88480.989957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67606.709896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67606.709896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72292.911552 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72292.911552 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72345.460894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79956.390777 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340989 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330911040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 248905 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7205469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 801528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6778838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 266094 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035849 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15507443 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23133859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330854720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223480704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554335424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 565266 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 16416862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.034431 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.182334 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15851611 96.56% 96.56% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 565251 3.44% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 16416862 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8660995500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7754456946 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135063976 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 314058 # Transaction distribution -system.membus.trans_dist::ReadResp 314058 # Transaction distribution -system.membus.trans_dist::Writeback 66342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19 # Transaction distribution -system.membus.trans_dist::UpgradeResp 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 1398 # Transaction distribution -system.membus.trans_dist::ReadExResp 1398 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 314068 # Transaction distribution +system.membus.trans_dist::Writeback 66338 # Transaction distribution +system.membus.trans_dist::CleanEvict 232219 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1394 # Transaction distribution +system.membus.trans_dist::ReadExResp 1394 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 314068 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 929513 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 929513 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24435200 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381817 # Request fanout histogram +system.membus.snoop_fanout::samples 614035 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 614035 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381817 # Request fanout histogram -system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 614035 # Request fanout histogram +system.membus.reqLayer0.occupancy 967133123 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1648308021 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 4a7e6f230..627fd964a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.043695 # Number of seconds simulated -sim_ticks 1043695078500 # Number of ticks simulated -final_tick 1043695078500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043722 # Number of seconds simulated +sim_ticks 1043722398500 # Number of ticks simulated +final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 624059 # Simulator instruction rate (inst/s) -host_op_rate 766694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1018706197 # Simulator tick rate (ticks/s) -host_mem_usage 313408 # Number of bytes of host memory used -host_seconds 1024.53 # Real time elapsed on the host +host_inst_rate 921530 # Simulator instruction rate (inst/s) +host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1504334297 # Simulator tick rate (ticks/s) +host_mem_usage 320916 # Number of bytes of host memory used +host_seconds 693.81 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18428352 # Number of bytes read from this memory -system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18469760 # Number of bytes read from this memory +system.physmem.bytes_read::total 18582976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287943 # Number of read requests responded to by this memory -system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288590 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290359 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 108476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17656835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17656835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087390157 # number of cpu cycles simulated +system.cpu.numCycles 2087444797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087390156.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640584 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996415000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640584 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582740000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18582740000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22259892000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22259892000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22259892000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22259892000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.414780 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.414780 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.189436 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28465.189436 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.130692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28460.130692 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks -system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.writebacks::writebacks 89072 # number of writebacks +system.cpu.dcache.writebacks::total 89072 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513680000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513680000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086847500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21086847500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088530000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21088530000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.395241 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.395241 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.174686 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.174686 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.533658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.533658 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464501 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464501 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207074000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207074000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207074000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207074000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207074000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207074000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20285.462382 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20285.462382 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20285.462382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20285.462382 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,38 +419,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191762000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 191762000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191762000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 191762000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191762000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 191762000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18785.462382 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18785.462382 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18785.462382 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18785.462382 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18785.462382 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18785.462382 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 256932 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.698157 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257579 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505444 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.076488 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.116225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.908970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995689 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id @@ -458,78 +458,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7430286 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8439 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 490969 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 499408 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91561 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 12984085 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12984085 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 89072 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 89072 # 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number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92944500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15117298500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92944500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15117298500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 91561 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 91561 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 288590 # number of overall misses +system.cpu.l2cache.overall_misses::total 290359 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.173295 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.173295 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312137 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312137 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173295 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368147 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.365636 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368974 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.366453 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173295 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368147 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.700961 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099842 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.700961 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010617 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.700961 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010617 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368974 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.366453 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,103 +546,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1769 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221850 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 223619 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 184 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 184 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1769 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1769 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222497 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222497 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287943 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288590 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290359 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287943 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71648500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984925000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71648500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661691500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71648500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661691500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311229 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288590 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290359 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.173295 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312137 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312137 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366453 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.261164 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366453 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55757696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257579 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 223619 # Transaction distribution -system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 224266 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190085 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224266 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836901 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22813248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 355811 # Request fanout histogram +system.membus.snoop_fanout::samples 546599 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 546599 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 546599 # Request fanout histogram +system.membus.reqLayer0.occupancy 811365948 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1452169448 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |