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authorAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:54 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:54 -0500
commit9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch)
treefab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/se/40.perlbmk/ref/arm
parent009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff)
downloadgem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm')
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini42
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt462
3 files changed, 257 insertions, 253 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 2cb5b08f3..735e1f1d5 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,7 +31,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -56,7 +57,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -115,6 +116,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -131,21 +133,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -434,21 +431,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -477,21 +486,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -518,7 +522,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/gem5/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 220b82b27..638fa449a 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:20:14
-gem5 started Oct 30 2012 20:00:53
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 5 2013 00:23:14
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 2c9a2891f..4f910c5cd 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.624868 # Nu
sim_ticks 624867585500 # Number of ticks simulated
final_tick 624867585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 118271 # Simulator instruction rate (inst/s)
-host_op_rate 161069 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53384157 # Simulator tick rate (ticks/s)
-host_mem_usage 298364 # Number of bytes of host memory used
-host_seconds 11705.11 # Real time elapsed on the host
+host_inst_rate 53257 # Simulator instruction rate (inst/s)
+host_op_rate 72528 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24038469 # Simulator tick rate (ticks/s)
+host_mem_usage 255596 # Number of bytes of host memory used
+host_seconds 25994.48 # Real time elapsed on the host
sim_insts 1384379060 # Number of instructions simulated
sim_ops 1885333812 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155584 # Number of bytes read from this memory
@@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 4108 # Tr
system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 624867513500 # Total gap between requests
+system.physmem.totGap 624867514500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3316258619 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 18090208619 # Sum of mem lat for all requests
+system.physmem.totQLat 3316258119 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 18090208119 # Sum of mem lat for all requests
system.physmem.totBusLat 1899312000 # Total cycles spent in databus access
system.physmem.totBankLat 12874638000 # Total cycles spent in bank access
system.physmem.avgQLat 6984.13 # Average queueing delay per request
system.physmem.avgBankLat 27114.32 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 38098.45 # Average memory access latency
+system.physmem.avgMemAccLat 38098.44 # Average memory access latency
system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s
@@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 227490785 # Nu
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 52186990 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2806187 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 354123352 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 354123353 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2285928065 # Number of instructions fetch has processed
system.cpu.fetch.Branches 439117025 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 279677775 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 600707462 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 157912293 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 133000859 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.BlockedCycles 133000861 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 564 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11147 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 333825475 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10767149 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1215073364 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 333825476 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10767150 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1215073366 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.587868 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.187266 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 614410423 50.57% 50.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 614410425 50.57% 50.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42578199 3.50% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 95045800 7.82% 61.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 56224969 4.63% 66.52% # Number of instructions fetched each cycle (Total)
@@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 229019054 18.85% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1215073364 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1215073366 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.351368 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.829130 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 403820359 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105461627 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 105461629 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 561742218 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16831582 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 127217578 # Number of cycles decode is squashing
@@ -290,18 +290,18 @@ system.cpu.rename.SquashCycles 127217578 # Nu
system.cpu.rename.IdleCycles 439577665 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 35450988 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 444214 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 540789818 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71593101 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2966286071 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 540789819 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 71593102 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2966286080 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4807554 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 56267627 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2940514356 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14121260893 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13550785312 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 2940514359 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14121260922 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13550785341 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 570475581 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993153642 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 947360714 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 947360717 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 22542 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 20019 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 191397273 # count of insts added to the skid buffer
@@ -316,11 +316,11 @@ system.cpu.iq.iqSquashedInstsIssued 13311855 # Nu
system.cpu.iq.iqSquashedInstsExamined 906440094 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2354573703 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 7928 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1215073364 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 1215073366 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.005123 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.874281 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 379121475 31.20% 31.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 379121477 31.20% 31.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 183370974 15.09% 46.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 203148367 16.72% 63.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 169783138 13.97% 76.98% # Number of insts issued each cycle
@@ -332,7 +332,7 @@ system.cpu.iq.issued_per_cycle::8 3045427 0.25% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1215073364 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1215073366 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 714606 0.82% 0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24380 0.03% 0.84% # attempts to use FU when none available
@@ -405,7 +405,7 @@ system.cpu.iq.FU_type_0::total 2436370950 # Ty
system.cpu.iq.rate 1.949510 # Inst issue rate
system.cpu.iq.fu_busy_cnt 87664598 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.035982 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6066277406 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 6066277408 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3628118286 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2252998417 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 122514311 # Number of floating instruction queue reads
@@ -428,7 +428,7 @@ system.cpu.iew.iewSquashCycles 127217578 # Nu
system.cpu.iew.iewBlockCycles 13751124 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1562188 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2804340477 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1409393 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 1409402 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 972715984 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 490205592 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 19935 # Number of dispatched non-speculative instructions
@@ -490,7 +490,7 @@ system.cpu.commit.bw_limited 0 # nu
system.cpu.rob.rob_reads 3801294955 # The number of ROB reads
system.cpu.rob.rob_writes 5735909866 # The number of ROB writes
system.cpu.timesIdled 353133 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 34661808 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 34661806 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384379060 # Number of Instructions Simulated
system.cpu.committedOps 1885333812 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384379060 # Number of Instructions Simulated
@@ -519,36 +519,36 @@ system.cpu.icache.demand_hits::cpu.inst 333794637 # nu
system.cpu.icache.demand_hits::total 333794637 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 333794637 # number of overall hits
system.cpu.icache.overall_hits::total 333794637 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 30836 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 30836 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 30836 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 30836 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 30836 # number of overall misses
-system.cpu.icache.overall_misses::total 30836 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 469688998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 469688998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 469688998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 469688998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 469688998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 469688998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 333825473 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 333825473 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 333825473 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 333825473 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 333825473 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 333825473 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_misses::cpu.inst 30837 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 30837 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 30837 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 30837 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 30837 # number of overall misses
+system.cpu.icache.overall_misses::total 30837 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 469758998 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 469758998 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 469758998 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 469758998 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 469758998 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 469758998 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 333825474 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 333825474 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 333825474 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 333825474 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 333825474 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 333825474 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
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@@ -755,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 474998 # nu
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -838,18 +712,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2431
system.cpu.l2cache.overall_mshr_misses::cpu.data 472543 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97294812 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693796850 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791091662 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20693797350 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791092162 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43304330 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43304330 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390499504 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390499504 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2390498504 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2390498504 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97294812 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084296354 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 23181591166 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23084295854 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23181590666 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97294812 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084296354 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 23181591166 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23084295854 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23181590666 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100322 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277535 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274651 # mshr miss rate for ReadReq accesses
@@ -864,18 +738,144 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100322
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307428 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.304214 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.133075 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.398048 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.109847 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.109847 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.206883 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.020258 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1532987 # number of replacements
+system.cpu.dcache.tagsinuse 4094.606879 # Cycle average of tags in use
+system.cpu.dcache.total_refs 970022641 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1537083 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 631.080196 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 335185000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.606879 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999660 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999660 # Average percentage of cache occupancy
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+system.cpu.dcache.ReadReq_hits::total 693885026 # number of ReadReq hits
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+system.cpu.dcache.LoadLockedReq_hits::total 11981 # number of LoadLockedReq hits
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.508124 # average ReadReq miss latency
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+system.cpu.dcache.blocked_cycles::no_targets 681 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 55 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 87 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.636364 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 7.827586 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks
+system.cpu.dcache.writebacks::total 96322 # number of writebacks
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+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.142233 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.142233 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.693725 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.693725 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------