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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-06-06 17:16:44 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-06-06 17:16:44 +0100
commit85997e66a08b71d701e5b41462d1cfd42660b0c7 (patch)
treebc242f1a2bfc3a92b18da04805d9ebd8864b5320 /tests/long/se/40.perlbmk/ref/arm
parent21b66f45422bc449d4a8b86ab452d6b6ae5838bf (diff)
downloadgem5-85997e66a08b71d701e5b41462d1cfd42660b0c7.tar.xz
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm')
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt25
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt26
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt18
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt25
4 files changed, 74 insertions, 20 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 3ea3d5388..eb3e6af6a 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.489946 # Nu
sim_ticks 489945697500 # Number of ticks simulated
final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 152136 # Simulator instruction rate (inst/s)
-host_op_rate 187299 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 116346895 # Simulator tick rate (ticks/s)
-host_mem_usage 275904 # Number of bytes of host memory used
-host_seconds 4211.08 # Real time elapsed on the host
+host_inst_rate 287135 # Simulator instruction rate (inst/s)
+host_op_rate 353501 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 219588415 # Simulator tick rate (ticks/s)
+host_mem_usage 322476 # Number of bytes of host memory used
+host_seconds 2231.20 # Real time elapsed on the host
sim_insts 640655085 # Number of instructions simulated
sim_ops 788730744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory
system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory
@@ -272,6 +273,7 @@ system.physmem_1.memoryStateTime::REF 16360240000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 144591747 # Number of BP lookups
system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect
@@ -286,6 +288,7 @@ system.cpu.branchPred.indirectHits 15989167 # Nu
system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -315,6 +318,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -344,6 +348,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -373,6 +378,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -403,6 +409,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 979891395 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -449,6 +456,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl
system.cpu.op_class_0::total 788730744 # Class of committed instruction
system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked
system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 778302 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks.
@@ -467,6 +475,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
@@ -587,6 +596,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 24859 # number of replacements
system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks.
@@ -603,6 +613,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1599
system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses
system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits
@@ -671,6 +682,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395
system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 258808 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks.
@@ -693,6 +705,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits
@@ -845,6 +858,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314
system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution
@@ -877,6 +891,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 39920495 # La
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 225121 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190682 # Transaction distribution
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index a4f9b9a0f..77ad5d4bc 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.326731 # Nu
sim_ticks 326731324000 # Number of ticks simulated
final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 188423 # Simulator instruction rate (inst/s)
-host_op_rate 231974 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 96095829 # Simulator tick rate (ticks/s)
-host_mem_usage 319396 # Number of bytes of host memory used
-host_seconds 3400.06 # Real time elapsed on the host
+host_inst_rate 187465 # Simulator instruction rate (inst/s)
+host_op_rate 230795 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 95607340 # Simulator tick rate (ticks/s)
+host_mem_usage 320048 # Number of bytes of host memory used
+host_seconds 3417.43 # Real time elapsed on the host
sim_insts 640649299 # Number of instructions simulated
sim_ops 788724958 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory
@@ -295,6 +296,7 @@ system.physmem_1.memoryStateTime::REF 10910120000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 174663372 # Number of BP lookups
system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect
@@ -309,6 +311,7 @@ system.cpu.branchPred.indirectHits 16701520 # Nu
system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -338,6 +341,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -367,6 +371,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -396,6 +401,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -426,6 +432,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 653462649 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -716,6 +723,7 @@ system.cpu.cc_regfile_reads 3322370942 # nu
system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes
system.cpu.misc_regfile_reads 606830949 # number of misc regfile reads
system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 2756452 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks.
@@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 56
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits
@@ -863,6 +872,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1979880 # number of replacements
system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks.
@@ -880,6 +890,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 333
system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses
system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits
@@ -954,12 +965,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721
system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency
+system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 301370 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks.
@@ -986,6 +999,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits
@@ -1167,6 +1181,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707
system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution
@@ -1202,6 +1217,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # La
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 951856 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution
system.membus.trans_dist::CleanEvict 227102 # Transaction distribution
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 1251990c8..e2d47dff8 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.395727 # Nu
sim_ticks 395726778500 # Number of ticks simulated
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1843468 # Simulator instruction rate (inst/s)
-host_op_rate 2269552 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1138694237 # Simulator tick rate (ticks/s)
-host_mem_usage 309656 # Number of bytes of host memory used
-host_seconds 347.53 # Real time elapsed on the host
+host_inst_rate 1817115 # Simulator instruction rate (inst/s)
+host_op_rate 2237108 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1122416416 # Simulator tick rate (ticks/s)
+host_mem_usage 311336 # Number of bytes of host memory used
+host_seconds 352.57 # Real time elapsed on the host
sim_insts 640654411 # Number of instructions simulated
sim_ops 788730070 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
@@ -35,7 +36,9 @@ system.physmem.bw_write::total 1322421027 # Wr
system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 791453558 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730744 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 0aed4ec36..fc47d4b38 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 1.045756 # Nu
sim_ticks 1045756396500 # Number of ticks simulated
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1156934 # Simulator instruction rate (inst/s)
-host_op_rate 1421363 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1892295085 # Simulator tick rate (ticks/s)
-host_mem_usage 319640 # Number of bytes of host memory used
-host_seconds 552.64 # Real time elapsed on the host
+host_inst_rate 1150404 # Simulator instruction rate (inst/s)
+host_op_rate 1413341 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1881615398 # Simulator tick rate (ticks/s)
+host_mem_usage 320304 # Number of bytes of host memory used
+host_seconds 555.78 # Real time elapsed on the host
sim_insts 639366787 # Number of instructions simulated
sim_ops 785501035 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
@@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 4045179 # To
system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2091512793 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730744 # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 778046 # number of replacements
system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
@@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
@@ -350,6 +359,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 8769 # number of replacements
system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
@@ -366,6 +376,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1339
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits
@@ -434,6 +445,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878
system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 257772 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
@@ -456,6 +468,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits
@@ -598,6 +611,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110
system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution
@@ -630,6 +644,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 15312000 # La
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 224275 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190094 # Transaction distribution