diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/40.perlbmk/ref | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
8 files changed, 2920 insertions, 2866 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index f21f0115d..cfec5db38 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.508216 # Number of seconds simulated -sim_ticks 508215534000 # Number of ticks simulated -final_tick 508215534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.508441 # Number of seconds simulated +sim_ticks 508441445000 # Number of ticks simulated +final_tick 508441445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 266071 # Simulator instruction rate (inst/s) -host_op_rate 266071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145588775 # Simulator tick rate (ticks/s) -host_mem_usage 258712 # Number of bytes of host memory used -host_seconds 3490.76 # Real time elapsed on the host +host_inst_rate 272638 # Simulator instruction rate (inst/s) +host_op_rate 272638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149248503 # Simulator tick rate (ticks/s) +host_mem_usage 263860 # Number of bytes of host memory used +host_seconds 3406.68 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520192 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185920 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 185856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory +system.physmem.bytes_read::total 18706752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185856 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289378 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292293 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 365829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36441609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36807438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8397445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 365829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36441609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 45204883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292283 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 365541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36426802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36792343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8393714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 365541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36426802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 45186057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292293 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292283 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292293 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18687040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706112 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18685888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18706752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18032 # Per bank write bursts -system.physmem.perBankRdBursts::1 18362 # Per bank write bursts -system.physmem.perBankRdBursts::2 18398 # Per bank write bursts -system.physmem.perBankRdBursts::3 18335 # Per bank write bursts -system.physmem.perBankRdBursts::4 18250 # Per bank write bursts -system.physmem.perBankRdBursts::5 18255 # Per bank write bursts -system.physmem.perBankRdBursts::6 18321 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18236 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18379 # Per bank write bursts -system.physmem.perBankRdBursts::12 18271 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18060 # Per bank write bursts -system.physmem.perBankRdBursts::15 18193 # Per bank write bursts +system.physmem.perBankRdBursts::0 18028 # Per bank write bursts +system.physmem.perBankRdBursts::1 18361 # Per bank write bursts +system.physmem.perBankRdBursts::2 18399 # Per bank write bursts +system.physmem.perBankRdBursts::3 18347 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18247 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18291 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18239 # Per bank write bursts +system.physmem.perBankRdBursts::10 18229 # Per bank write bursts +system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::12 18268 # Per bank write bursts +system.physmem.perBankRdBursts::13 18136 # Per bank write bursts +system.physmem.perBankRdBursts::14 18057 # Per bank write bursts +system.physmem.perBankRdBursts::15 18190 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts +system.physmem.perBankWrBursts::9 4188 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 508215452500 # Total gap between requests +system.physmem.totGap 508441362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292283 # Read request sizes (log2) +system.physmem.readPktSize::6 292293 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 464 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,25 +145,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,97 +194,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 221.521925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.541969 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.372247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37864 36.55% 36.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43808 42.28% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9097 8.78% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 745 0.72% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1395 1.35% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1153 1.11% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 627 0.61% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 610 0.59% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8304 8.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.361324 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.573478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 739.455375 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 103424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 221.899134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.895688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.440022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37597 36.35% 36.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43798 42.35% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9078 8.78% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 804 0.78% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1585 1.53% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1026 0.99% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 543 0.53% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 0.64% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8333 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103424 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.164816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.696519 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 767.230213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.462336 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.441628 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.843264 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 936 23.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 2518388500 # Total ticks spent queuing -system.physmem.totMemAccLat 7993107250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8625.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.448063 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.427763 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.835172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3146 77.62% 77.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 906 22.35% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 2452616250 # Total ticks spent queuing +system.physmem.totMemAccLat 7926997500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8400.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27375.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27150.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 8.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.40 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 203026 # Number of row buffer hits during reads -system.physmem.writeRowHits 52001 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 1415776.01 # Average gap between requests -system.physmem.pageHitRate 71.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 390708360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 213184125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140250800 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing +system.physmem.readRowHits 203097 # Number of row buffer hits during reads +system.physmem.writeRowHits 52099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 1416365.89 # Average gap between requests +system.physmem.pageHitRate 71.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 390353040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 212990250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140196200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103572972045 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214071794250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 352799059260 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.201008 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355459552750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_0.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 103170345705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 214560479250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 352899262365 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.089734 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 356274409500 # Time in different power states +system.physmem_0.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 135779058500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 135182501000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 392424480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 214120500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136545800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103467236760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 214164544500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 352784075640 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.171524 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 355611467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_1.actEnergy 391426560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 213576000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136460000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 103438175310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 214325517750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 352929159300 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.148589 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 355878371250 # Time in different power states +system.physmem_1.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135627775750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 135579179250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851653 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 123851654 # Number of BP lookups system.cpu.branchPred.condPredicted 79872946 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 686743 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066131 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190141 # Number of BTB hits +system.cpu.branchPred.BTBLookups 102066133 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68190143 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 66.809764 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697400 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 18697398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 11224 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 14052177 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 14048616 # Number of indirect target hits. @@ -299,18 +299,18 @@ system.cpu.dtb.read_hits 237539296 # DT system.cpu.dtb.read_misses 195211 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305020 # DTB write hits +system.cpu.dtb.write_hits 98305021 # DTB write hits system.cpu.dtb.write_misses 7170 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312190 # DTB write accesses -system.cpu.dtb.data_hits 335844316 # DTB hits +system.cpu.dtb.write_accesses 98312191 # DTB write accesses +system.cpu.dtb.data_hits 335844317 # DTB hits system.cpu.dtb.data_misses 202381 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046697 # DTB accesses -system.cpu.itb.fetch_hits 286584409 # ITB hits +system.cpu.dtb.data_accesses 336046698 # DTB accesses +system.cpu.itb.fetch_hits 286584411 # ITB hits system.cpu.itb.fetch_misses 119 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584528 # ITB accesses +system.cpu.itb.fetch_accesses 286584530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,16 +324,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1016431068 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1016882890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319592 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 319599 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.094361 # CPI: cycles per instruction -system.cpu.ipc 0.913775 # IPC: instructions per cycle +system.cpu.cpi 1.094848 # CPI: cycles per instruction +system.cpu.ipc 0.913369 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction @@ -369,36 +369,36 @@ system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962815750 # Number of cycles that the object actually ticked -system.cpu.idleCycles 53615318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 962815783 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54067107 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.348104 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318733 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.323693 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320318732 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320478 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 905242500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.348104 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999108 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999108 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 410.320477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 911974500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.323693 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999102 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999102 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 955 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1491 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115729 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154684 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 643115727 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 643115727 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 222154683 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 222154683 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98164049 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164049 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318733 # number of overall hits -system.cpu.dcache.overall_hits::total 320318733 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 320318732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320318732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320318732 # number of overall hits +system.cpu.dcache.overall_hits::total 320318732 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137151 # number of WriteReq misses @@ -407,22 +407,22 @@ system.cpu.dcache.demand_misses::cpu.data 848804 # n system.cpu.dcache.demand_misses::total 848804 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 848804 # number of overall misses system.cpu.dcache.overall_misses::total 848804 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34517712500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34517712500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866337 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34770905000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34770905000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 222866336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 222866336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167537 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 321167536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 321167536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 321167536 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 321167536 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -431,22 +431,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34304.073755 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34304.073755 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73678.759178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73678.759178 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40666.293396 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34577.963558 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34577.963558 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74103.677698 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74103.677698 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40964.586642 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88481 # number of writebacks -system.cpu.dcache.writebacks::total 88481 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks +system.cpu.dcache.writebacks::total 88440 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68140 # number of WriteReq MSHR hits @@ -463,14 +463,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780655 system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28768272500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28768272500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993164500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28993164500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -479,24 +479,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10580 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.197843 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572082 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12326 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23249.398183 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 10578 # number of replacements +system.cpu.icache.tags.tagsinuse 1690.178313 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 286572086 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12324 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23253.171535 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.197843 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825292 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825292 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1690.178313 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.825282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.825282 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id @@ -504,181 +504,181 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181144 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181144 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572082 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572082 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572082 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572082 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572082 # number of overall hits -system.cpu.icache.overall_hits::total 286572082 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12327 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12327 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12327 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12327 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12327 # number of overall misses -system.cpu.icache.overall_misses::total 12327 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 353123500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 353123500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 353123500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 353123500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 353123500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 353123500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584409 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584409 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584409 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584409 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 573181146 # Number of tag accesses +system.cpu.icache.tags.data_accesses 573181146 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 286572086 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286572086 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286572086 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 286572086 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 286572086 # number of overall hits +system.cpu.icache.overall_hits::total 286572086 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12325 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12325 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12325 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12325 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12325 # number of overall misses +system.cpu.icache.overall_misses::total 12325 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354631500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354631500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354631500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354631500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354631500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354631500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 286584411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 286584411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 286584411 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 286584411 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 286584411 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 286584411 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28646.345421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28646.345421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28646.345421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28646.345421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28646.345421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28646.345421 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28773.346856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28773.346856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28773.346856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10580 # number of writebacks -system.cpu.icache.writebacks::total 10580 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12327 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12327 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12327 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12327 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12327 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12327 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340797500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 340797500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340797500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 340797500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340797500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 340797500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 10578 # number of writebacks +system.cpu.icache.writebacks::total 10578 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12325 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12325 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12325 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12325 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12325 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12325 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 342307500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 342307500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 342307500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 342307500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 342307500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 342307500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27646.426543 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27646.426543 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27646.426543 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27646.426543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27646.426543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27646.426543 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259960 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32580.630666 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218282 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292696 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.162278 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2624.989355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.480782 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29876.160528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.080108 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002426 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.911748 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994282 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27773.427992 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27773.427992 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27773.427992 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27773.427992 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27773.427992 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27773.427992 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 259981 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32663.117880 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1287366 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292749 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.397508 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 3599699000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 51.758593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.280290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32532.078996 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001580 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002419 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992800 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29055 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13002675 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13002675 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88481 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88481 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10580 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10580 # number of WritebackClean hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29072 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12933685 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12933685 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88440 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88440 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10578 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10578 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488911 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488911 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9421 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491277 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 500698 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9421 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491277 # number of overall hits -system.cpu.l2cache.overall_hits::total 500698 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9420 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 9420 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488900 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488900 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9420 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491266 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 500686 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9420 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491266 # number of overall hits +system.cpu.l2cache.overall_hits::total 500686 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2906 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2906 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222733 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222733 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2906 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289378 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292284 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2906 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289378 # number of overall misses -system.cpu.l2cache.overall_misses::total 292284 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4939623000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4939623000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223388000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 223388000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17499220000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17499220000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 223388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22438843000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22662231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 223388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22438843000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22662231000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88481 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88481 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10580 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10580 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2905 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2905 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222744 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222744 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2905 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289389 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 292294 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2905 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289389 # number of overall misses +system.cpu.l2cache.overall_misses::total 292294 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4969595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4969595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224911500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 224911500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17694256000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17694256000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 224911500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22663851000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22888762500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 224911500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22663851000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22888762500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88440 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88440 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10578 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10578 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12327 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12327 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12325 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 12325 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711644 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12327 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 12325 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 780655 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792982 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12327 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792980 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12325 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792982 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792980 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235743 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370686 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.368588 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235743 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370686 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.368588 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74118.433491 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74118.433491 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76871.300757 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76871.300757 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78565.906264 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78565.906264 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76871.300757 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77541.634126 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77534.969413 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76871.300757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77541.634126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77534.969413 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235700 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235700 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312999 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312999 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235700 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368602 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368602 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78307.329264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78307.329264 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,120 +691,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2906 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2906 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222733 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222733 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2906 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289378 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292284 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2906 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289378 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292284 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4273173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4273173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 194338000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 194338000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15271890000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15271890000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194338000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19545063000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19739401000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194338000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19545063000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19739401000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2905 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2905 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2905 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292294 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2905 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292294 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4303145000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4303145000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15466816000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15466816000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195871500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19769961000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19965832500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195871500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19769961000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19965832500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368588 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368588 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580121 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787139 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368602 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368602 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1580117 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2087 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2087 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2095 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10580 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881355 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 723968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881417 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12325 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35227 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55624704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57090688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259960 # Total snoops (count) +system.cpu.toL2Bus.pkt_count::total 2373096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259981 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001982 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044476 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1052961 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001990 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044561 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050855 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2087 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050866 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2095 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052942 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889121500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052961 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889076500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18489000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18486000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170982999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225638 # Transaction distribution +system.membus.snoop_filter.tot_requests 550179 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257886 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225648 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191190 # Transaction distribution +system.membus.trans_dist::CleanEvict 191203 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225638 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22973824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22973824 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22974464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 550156 # Request fanout histogram +system.membus.snoop_fanout::samples 292293 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292293 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550156 # Request fanout histogram -system.membus.reqLayer0.occupancy 925402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292293 # Request fanout histogram +system.membus.reqLayer0.occupancy 925378500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556718500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556878500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 577d97331..c74410070 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.174766 # Number of seconds simulated -sim_ticks 174766258500 # Number of ticks simulated -final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.175004 # Number of seconds simulated +sim_ticks 175004412500 # Number of ticks simulated +final_tick 175004412500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215097 # Simulator instruction rate (inst/s) -host_op_rate 215097 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44625570 # Simulator tick rate (ticks/s) -host_mem_usage 260248 # Number of bytes of host memory used -host_seconds 3916.28 # Real time elapsed on the host +host_inst_rate 244500 # Simulator instruction rate (inst/s) +host_op_rate 244500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50794673 # Simulator tick rate (ticks/s) +host_mem_usage 265392 # Number of bytes of host memory used +host_seconds 3445.33 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory -system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 174016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 174016 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18525120 # Number of bytes read from this memory +system.physmem.bytes_read::total 18699072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2719 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292173 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 995707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 105996479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106992186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24419176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 995707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 105996479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 131411362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292166 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 993986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 105855160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106849146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 993986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 993986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24385945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24385945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24385945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 993986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 105855160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 131235091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292173 # Number of read requests accepted system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292166 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292173 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18677824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265792 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18698624 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18679488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18699072 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18006 # Per bank write bursts -system.physmem.perBankRdBursts::1 18334 # Per bank write bursts -system.physmem.perBankRdBursts::2 18382 # Per bank write bursts -system.physmem.perBankRdBursts::3 18340 # Per bank write bursts -system.physmem.perBankRdBursts::4 18235 # Per bank write bursts -system.physmem.perBankRdBursts::5 18233 # Per bank write bursts -system.physmem.perBankRdBursts::6 18311 # Per bank write bursts -system.physmem.perBankRdBursts::7 18302 # Per bank write bursts -system.physmem.perBankRdBursts::8 18233 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::0 18012 # Per bank write bursts +system.physmem.perBankRdBursts::1 18337 # Per bank write bursts +system.physmem.perBankRdBursts::2 18383 # Per bank write bursts +system.physmem.perBankRdBursts::3 18348 # Per bank write bursts +system.physmem.perBankRdBursts::4 18239 # Per bank write bursts +system.physmem.perBankRdBursts::5 18237 # Per bank write bursts +system.physmem.perBankRdBursts::6 18320 # Per bank write bursts +system.physmem.perBankRdBursts::7 18308 # Per bank write bursts +system.physmem.perBankRdBursts::8 18229 # Per bank write bursts +system.physmem.perBankRdBursts::9 18225 # Per bank write bursts system.physmem.perBankRdBursts::10 18220 # Per bank write bursts -system.physmem.perBankRdBursts::11 18388 # Per bank write bursts -system.physmem.perBankRdBursts::12 18256 # Per bank write bursts -system.physmem.perBankRdBursts::13 18125 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18192 # Per bank write bursts +system.physmem.perBankRdBursts::11 18382 # Per bank write bursts +system.physmem.perBankRdBursts::12 18250 # Per bank write bursts +system.physmem.perBankRdBursts::13 18123 # Per bank write bursts +system.physmem.perBankRdBursts::14 18058 # Per bank write bursts +system.physmem.perBankRdBursts::15 18196 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,8 +74,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4261 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts -system.physmem.perBankWrBursts::10 4148 # Per bank write bursts +system.physmem.perBankWrBursts::9 4191 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 174766169000 # Total gap between requests +system.physmem.totGap 175004322000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292166 # Read request sizes (log2) +system.physmem.readPktSize::6 292173 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,12 +98,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -146,24 +146,24 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4144 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,125 +194,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.414911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.615169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 282.362382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 31544 32.64% 32.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41851 43.31% 75.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11279 11.67% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 407 0.42% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 349 0.36% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 422 0.44% 88.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 656 0.68% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1511 1.56% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8609 8.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96628 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.731557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.520071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 729.773377 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 96708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.268147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.455294 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.430006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31632 32.71% 32.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41779 43.20% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11320 11.71% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 443 0.46% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 357 0.37% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 304 0.31% 88.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 669 0.69% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1569 1.62% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8635 8.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96708 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.658609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.711074 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 765.890247 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.78% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.445349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.425120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.833815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3151 77.74% 77.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 77.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 896 22.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads -system.physmem.totQLat 3659606000 # Total ticks spent queuing -system.physmem.totMemAccLat 9131624750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12539.73 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.444499 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.424176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.836057 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3157 77.87% 77.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 892 22.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads +system.physmem.totQLat 3688779750 # Total ticks spent queuing +system.physmem.totMemAccLat 9161286000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12638.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31289.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 24.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 24.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31388.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 24.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 24.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.03 # Data bus utilization in percentage +system.physmem.busUtil 1.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 209802 # Number of row buffer hits during reads -system.physmem.writeRowHits 52054 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 487020.04 # Average gap between requests -system.physmem.pageHitRate 73.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 364626360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 198952875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139346000 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 209722 # Number of row buffer hits during reads +system.physmem.writeRowHits 52099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 487674.19 # Average gap between requests +system.physmem.pageHitRate 73.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 365095080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 199208625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140180600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63677219400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 49000374750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 126011580585 # Total energy per rank (pJ) -system.physmem_0.averagePower 721.044153 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81102514500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_0.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63710720865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 49115814750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 126177846480 # Total energy per rank (pJ) +system.physmem_0.averagePower 720.999703 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81290875500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5843760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87824440500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87869398250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 365752800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 199567500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136265000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215479440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 63630052470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49041749250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 126003495660 # Total energy per rank (pJ) -system.physmem_1.averagePower 720.997890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81165303250 # Time in different power states -system.physmem_1.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_1.actEnergy 366002280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 199703625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136311800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215563680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64026816075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48838535250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 126213327270 # Total energy per rank (pJ) +system.physmem_1.averagePower 721.202467 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 80826473000 # Time in different power states +system.physmem_1.memoryStateTime::REF 5843760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 88334018000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 129267026 # Number of BP lookups -system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93510959 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70602364 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 129267773 # Number of BP lookups +system.cpu.branchPred.condPredicted 83048997 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 145228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93512308 # Number of BTB lookups +system.cpu.branchPred.BTBHits 70602709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.501700 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428078 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1137 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846480 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14819636 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 26844 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 75.500980 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19428222 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1139 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14846516 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14819690 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 26826 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4927 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243602185 # DTB read hits -system.cpu.dtb.read_misses 267667 # DTB read misses +system.cpu.dtb.read_hits 243602594 # DTB read hits +system.cpu.dtb.read_misses 267810 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243869852 # DTB read accesses -system.cpu.dtb.write_hits 101634527 # DTB write hits -system.cpu.dtb.write_misses 39608 # DTB write misses +system.cpu.dtb.read_accesses 243870404 # DTB read accesses +system.cpu.dtb.write_hits 101634629 # DTB write hits +system.cpu.dtb.write_misses 39603 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101674135 # DTB write accesses -system.cpu.dtb.data_hits 345236712 # DTB hits -system.cpu.dtb.data_misses 307275 # DTB misses +system.cpu.dtb.write_accesses 101674232 # DTB write accesses +system.cpu.dtb.data_hits 345237223 # DTB hits +system.cpu.dtb.data_misses 307413 # DTB misses system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345543987 # DTB accesses -system.cpu.itb.fetch_hits 116217608 # ITB hits -system.cpu.itb.fetch_misses 1594 # ITB misses +system.cpu.dtb.data_accesses 345544636 # DTB accesses +system.cpu.itb.fetch_hits 116218491 # ITB hits +system.cpu.itb.fetch_misses 1583 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116219202 # ITB accesses +system.cpu.itb.fetch_accesses 116220074 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,138 +327,138 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 349532518 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 350008826 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116536228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973715519 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129267026 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104850078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 232359516 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756618 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13025 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 116537595 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 973721565 # Number of instructions fetch has processed +system.cpu.fetch.Branches 129267773 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 104850621 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 232833162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 756818 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12983 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116217608 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 170932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.787716 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.090069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 116218491 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 171000 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 349762998 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.783947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.089679 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 152570668 43.68% 43.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21852908 6.26% 49.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15618674 4.47% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569577 7.03% 61.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38589117 11.05% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690770 4.49% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12536709 3.59% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3990160 1.14% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63869355 18.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 153044218 43.76% 43.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21853200 6.25% 50.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15619262 4.47% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24569789 7.02% 61.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 38589030 11.03% 72.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15690779 4.49% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12536762 3.58% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3989777 1.14% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 63870181 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369828 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.785765 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85729217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85771889 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158922951 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18492364 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371517 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11932000 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7014 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968678626 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25475 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371517 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93246352 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12124008 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14162 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169252951 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 74278948 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966798475 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 812 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25198716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40147884 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7202949 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666569389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151537527 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114498375 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37039151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 349762998 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369327 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.781991 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85730052 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86245168 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158924333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18491829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371616 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11931982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7013 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 968682189 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25467 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371616 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93247100 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12146615 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14284 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 169253997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 74729386 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 966801753 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1559 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25162616 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40511587 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7290496 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 666571567 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1151541399 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114502328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 37039070 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27602231 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87958062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245057270 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102624029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35348443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4751860 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877942600 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871652294 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10599 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35560646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10943510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 349287938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.495512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.135180 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27604409 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 87953522 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 245057905 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 102624371 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35358842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4732178 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 877945283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 77 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 871653931 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 10631 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35563330 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10945081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 349762998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.492127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.135671 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75519507 21.62% 21.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61352705 17.57% 39.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57497159 16.46% 55.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51075272 14.62% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45041028 12.90% 83.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20641156 5.91% 89.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18147367 5.20% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10284591 2.94% 97.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9729153 2.79% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75990310 21.73% 21.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 61353138 17.54% 39.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 57501132 16.44% 55.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51071612 14.60% 70.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45054201 12.88% 83.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20633149 5.90% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18143842 5.19% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10286820 2.94% 97.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9728794 2.78% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 349287938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 349762998 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3589516 19.40% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11788826 63.72% 83.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3123532 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3589530 19.39% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11797020 63.73% 83.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3124042 16.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505111201 57.95% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 505112247 57.95% 57.95% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13300877 1.53% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826560 0.44% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339807 0.38% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13300875 1.53% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826555 0.44% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued @@ -481,82 +482,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 244259904 28.02% 88.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 101804815 11.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 244260355 28.02% 88.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 101804963 11.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871652294 # Type of FU issued -system.cpu.iq.rate 2.493766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18501874 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041816444 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876761594 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835992532 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69288555 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778587 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34169821 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855051836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35101056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597329 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 871653931 # Type of FU issued +system.cpu.iq.rate 2.490377 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18510592 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021236 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2042303381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 876767032 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 835994185 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 69288702 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36778589 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34169846 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 855062076 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35101171 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 65597395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7546673 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37094 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4322829 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7547308 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5161 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37165 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4323171 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4439 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4324 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371517 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4003286 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617757 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966013425 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245057270 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102624029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538427 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 92920 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37094 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15937 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144140 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871030251 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243869972 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 622043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 371616 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4020858 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 620837 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 966016228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16689 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 245057905 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 102624371 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 77 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 538553 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 95932 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37165 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 15953 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 144173 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 871032011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 243870521 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 621920 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88070749 # number of nop insts executed -system.cpu.iew.exec_refs 345544428 # number of memory reference insts executed -system.cpu.iew.exec_branches 127159642 # Number of branches executed -system.cpu.iew.exec_stores 101674456 # Number of stores executed -system.cpu.iew.exec_rate 2.491986 # Inst execution rate -system.cpu.iew.wb_sent 870623887 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870162353 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525000957 # num instructions producing a value -system.cpu.iew.wb_consumers 821946847 # num instructions consuming a value -system.cpu.iew.wb_rate 2.489503 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638729 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31811556 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 88070868 # number of nop insts executed +system.cpu.iew.exec_refs 345545074 # number of memory reference insts executed +system.cpu.iew.exec_branches 127159833 # Number of branches executed +system.cpu.iew.exec_stores 101674553 # Number of stores executed +system.cpu.iew.exec_rate 2.488600 # Inst execution rate +system.cpu.iew.wb_sent 870625746 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 870164031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 525002727 # num instructions producing a value +system.cpu.iew.wb_consumers 821961915 # num instructions consuming a value +system.cpu.iew.wb_rate 2.486120 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.638719 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 31814193 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138434 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 345159794 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.690312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.060061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 138436 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345634386 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.686618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.059575 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109423104 31.70% 31.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81928646 23.74% 55.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29947333 8.68% 64.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779535 5.73% 69.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17819278 5.16% 75.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7961935 2.31% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3040960 0.88% 78.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3978860 1.15% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71280143 20.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109896722 31.80% 31.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 81929003 23.70% 55.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29947850 8.66% 64.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19779542 5.72% 69.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17820096 5.16% 75.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7961930 2.30% 77.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3040428 0.88% 78.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3978823 1.15% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71279992 20.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 345159794 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 345634386 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -602,127 +603,127 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71280143 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1231657697 # The number of ROB reads -system.cpu.rob.rob_writes 1924928764 # The number of ROB writes -system.cpu.timesIdled 3152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 244580 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 71279992 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1232135077 # The number of ROB reads +system.cpu.rob.rob_writes 1924934508 # The number of ROB writes +system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.414933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.414933 # CPI: Total CPI of All Threads -system.cpu.ipc 2.410025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.410025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104176449 # number of integer regfile reads -system.cpu.int_regfile_writes 635594518 # number of integer regfile writes -system.cpu.fp_regfile_reads 36406853 # number of floating regfile reads -system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes +system.cpu.cpi 0.415499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.415499 # CPI: Total CPI of All Threads +system.cpu.ipc 2.406745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.406745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1104178752 # number of integer regfile reads +system.cpu.int_regfile_writes 635595888 # number of integer regfile writes +system.cpu.fp_regfile_reads 36406844 # number of floating regfile reads +system.cpu.fp_regfile_writes 24680552 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776668 # number of replacements -system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780764 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.748599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 371412500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4091.068449 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998796 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 776667 # number of replacements +system.cpu.dcache.tags.tagsinuse 4091.035125 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 273851714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 350.748837 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 374790500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4091.035125 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998788 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998788 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1013 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408623 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 553380005 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 553380005 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 176443372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176443372 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408329 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408329 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273851866 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273851866 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273851866 # number of overall hits -system.cpu.dcache.overall_hits::total 273851866 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 892577 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 892577 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2447284 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2447284 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2447284 # number of overall misses -system.cpu.dcache.overall_misses::total 2447284 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145623422831 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145623422831 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177997950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177997950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 273851701 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 273851701 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 273851701 # number of overall hits +system.cpu.dcache.overall_hits::total 273851701 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1555036 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1555036 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 892871 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 892871 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2447907 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2447907 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2447907 # number of overall misses +system.cpu.dcache.overall_misses::total 2447907 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84877374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84877374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62367572330 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62367572330 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 147244946330 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 147244946330 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 147244946330 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 147244946330 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177998408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177998408 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276299150 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276299150 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276299150 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276299150 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22333 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 68716 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks -system.cpu.dcache.writebacks::total 88604 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842561 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823959 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 823959 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1666520 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1666520 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712146 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712146 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68618 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68618 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780764 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29887724997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_accesses::cpu.data 276299608 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 276299608 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 276299608 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 276299608 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008736 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008736 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008860 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008860 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008860 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008860 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54582.256617 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54582.256617 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69850.596928 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69850.596928 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60151.364545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60151.364545 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 63758 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 349 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 520 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.358166 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 122.611538 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88567 # number of writebacks +system.cpu.dcache.writebacks::total 88567 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842892 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842892 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824252 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 824252 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1667144 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1667144 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1667144 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1667144 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712144 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712144 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780763 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780763 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780763 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780763 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24487996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24487996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5721430497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5721430497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30209426497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30209426497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30209426497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30209426497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses @@ -731,24 +732,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4617 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18381.739639 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34386.298277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34386.298277 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83379.683426 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83379.683426 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 4616 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.876124 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 116210243 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6321 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18384.787692 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.904441 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.876124 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804627 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id @@ -756,187 +757,187 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 1 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 116209358 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 116209358 # number of overall hits -system.cpu.icache.overall_hits::total 116209358 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8250 # number of overall misses -system.cpu.icache.overall_misses::total 8250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 354158499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 354158499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 354158499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 354158499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 354158499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 354158499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 116217608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 116217608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 116217608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 116217608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 116217608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 116217608 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 232443303 # Number of tag accesses +system.cpu.icache.tags.data_accesses 232443303 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 116210243 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 116210243 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 116210243 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 116210243 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 116210243 # number of overall hits +system.cpu.icache.overall_hits::total 116210243 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8248 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8248 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8248 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8248 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8248 # number of overall misses +system.cpu.icache.overall_misses::total 8248 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 355215499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 355215499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 355215499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 355215499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 355215499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 355215499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 116218491 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 116218491 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 116218491 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 116218491 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 116218491 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 116218491 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42928.302909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42928.302909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42928.302909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42928.302909 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 738 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43066.864573 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43066.864573 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43066.864573 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43066.864573 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43066.864573 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43066.864573 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 726 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 61.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4617 # number of writebacks -system.cpu.icache.writebacks::total 4617 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1927 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1927 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1927 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1927 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1927 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1927 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6323 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6323 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6323 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6323 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6323 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6323 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 263974500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 263974500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 263974500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 263974500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 263974500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 263974500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 4616 # number of writebacks +system.cpu.icache.writebacks::total 4616 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1926 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1926 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1926 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1926 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1926 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1926 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6322 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6322 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6322 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6322 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6322 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6322 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 265463000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 265463000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 265463000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 265463000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 265463000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 265463000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41748.299858 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41748.299858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259794 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292532 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.126188 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2634.083249 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.428877 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29874.113923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.080386 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002088 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.911686 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994160 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 859 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8617 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 22757 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12908126 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12908126 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88604 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88604 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4617 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4617 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1993 # number of ReadExReq hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41990.351155 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41990.351155 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41990.351155 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41990.351155 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41990.351155 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41990.351155 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 259809 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32656.861347 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1275789 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292577 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.360524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 1215633000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 43.546736 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.196705 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32545.117905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002081 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.993198 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996608 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 858 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8605 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 22785 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12839521 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12839521 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88567 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88567 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4616 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4616 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1994 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1994 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3603 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 3603 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489324 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 489324 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489314 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 489314 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 3603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491317 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 494920 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491308 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 494911 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3603 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491317 # number of overall hits -system.cpu.l2cache.overall_hits::total 494920 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491308 # number of overall hits +system.cpu.l2cache.overall_hits::total 494911 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66625 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66625 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2720 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2720 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222822 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222822 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2720 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289447 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292167 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2720 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289447 # number of overall misses -system.cpu.l2cache.overall_misses::total 292167 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5537092500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5537092500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 216561000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 216561000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18014278000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18014278000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 216561000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23551370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23767931500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 216561000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23551370500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23767931500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88604 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88604 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4617 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4617 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68618 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68618 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712146 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712146 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6323 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780764 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787087 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6323 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780764 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787087 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.970955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.970955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.430176 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.430176 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312888 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312888 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430176 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370723 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.371200 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430176 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370723 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.371200 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83108.330206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83108.330206 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79618.014706 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79618.014706 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80846.047518 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80846.047518 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79618.014706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81350.499885 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79618.014706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81350.499885 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2719 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2719 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222830 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222830 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2719 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289455 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 292174 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2719 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289455 # number of overall misses +system.cpu.l2cache.overall_misses::total 292174 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5597249000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5597249000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 218052500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 218052500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18275822500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18275822500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 218052500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23873071500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24091124000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 218052500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23873071500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24091124000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88567 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88567 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4616 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4616 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 68619 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 68619 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 6322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712144 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712144 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6322 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 780763 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 787085 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6322 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 780763 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 787085 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.970941 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.970941 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.430085 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.430085 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312900 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312900 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430085 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370734 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.371210 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430085 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370734 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.371210 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84011.242026 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84011.242026 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80195.844060 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80195.844060 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82016.885069 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82016.885069 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80195.844060 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82475.934083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82454.715341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80195.844060 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82475.934083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82454.715341 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -949,120 +950,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66625 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2720 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292167 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2720 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289447 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292167 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4870842500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4870842500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 189371000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 189371000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15786058000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15786058000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189371000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20656900500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20846271500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189371000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20656900500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20846271500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2719 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2719 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222830 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222830 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2719 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2719 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289455 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292174 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4930999000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4930999000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 190872500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 190872500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16047522500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16047522500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 190872500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20978521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21169394000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 190872500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20978521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21169394000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430176 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312888 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312888 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.371200 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.371200 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73108.330206 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73108.330206 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69621.691176 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69621.691176 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70846.047518 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70846.047518 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1568372 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781285 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970941 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970941 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430085 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430085 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312900 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312900 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430085 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370734 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.371210 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430085 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370734 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.371210 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74011.242026 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74011.242026 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70199.521883 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70199.521883 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72016.885069 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72016.885069 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70199.521883 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72475.934083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72454.749567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70199.521883 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72475.934083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72454.749567 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1568368 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781283 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2008 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338196 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259794 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 718465 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712144 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338193 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2355452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56337088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259809 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1046894 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001918 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043754 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044878 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2003 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1044886 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2008 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1046881 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877407000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1046894 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877367000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9481500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171144500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225541 # Transaction distribution +system.membus.snoop_filter.tot_requests 549975 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257802 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225548 # Transaction distribution system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191110 # Transaction distribution +system.membus.trans_dist::CleanEvict 191120 # Transaction distribution system.membus.trans_dist::ReadExReq 66625 # Transaction distribution system.membus.trans_dist::ReadExResp 66625 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225541 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842148 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22966720 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 549958 # Request fanout histogram +system.membus.snoop_fanout::samples 292173 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549958 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292173 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549958 # Request fanout histogram -system.membus.reqLayer0.occupancy 877671500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292173 # Request fanout histogram +system.membus.reqLayer0.occupancy 877549500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551270000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551106000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index b6b81e33b..efcf10ec9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2033284 # Simulator instruction rate (inst/s) -host_op_rate 2033284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1016862727 # Simulator tick rate (ticks/s) -host_mem_usage 248468 # Number of bytes of host memory used -host_seconds 456.69 # Real time elapsed on the host +host_inst_rate 1533629 # Simulator instruction rate (inst/s) +host_op_rate 1533629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 766980884 # Simulator tick rate (ticks/s) +host_mem_usage 251816 # Number of bytes of host memory used +host_seconds 605.48 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 6109961839 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram -system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1264600947 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f13a4ce2b..7031d8335 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.288319 # Number of seconds simulated -sim_ticks 1288319411500 # Number of ticks simulated -final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.288611 # Number of seconds simulated +sim_ticks 1288611150500 # Number of ticks simulated +final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112167 # Simulator instruction rate (inst/s) -host_op_rate 1112167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1543016447 # Simulator tick rate (ticks/s) -host_mem_usage 257436 # Number of bytes of host memory used -host_seconds 834.94 # Real time elapsed on the host +host_inst_rate 1122029 # Simulator instruction rate (inst/s) +host_op_rate 1122029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1557051854 # Simulator tick rate (ticks/s) +host_mem_usage 262324 # Number of bytes of host memory used +host_seconds 827.60 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory -system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory +system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2576638823 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2577222301 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -92,7 +92,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2576638823 # Number of busy cycles +system.cpu.num_busy_cycles 2577222301 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -131,16 +131,16 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id @@ -150,7 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits @@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) @@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks -system.cpu.dcache.writebacks::total 88866 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks +system.cpu.dcache.writebacks::total 88841 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses @@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528 system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id @@ -257,7 +257,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits @@ -270,12 +270,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -288,12 +288,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,90 +308,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258847 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258865 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits -system.cpu.l2cache.overall_hits::total 495307 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits +system.cpu.l2cache.overall_hits::total 495300 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses -system.cpu.l2cache.overall_misses::total 291389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses +system.cpu.l2cache.overall_misses::total 291396 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) @@ -410,26 +410,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,63 +444,63 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14607390000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution @@ -509,53 +509,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258847 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258865 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224741 # Transaction distribution +system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 224748 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190447 # Transaction distribution +system.membus.trans_dist::CleanEvict 190457 # Transaction distribution system.membus.trans_dist::ReadExReq 66648 # Transaction distribution system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 548519 # Request fanout histogram +system.membus.snoop_fanout::samples 291396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548519 # Request fanout histogram -system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291396 # Request fanout histogram +system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 031a11fd6..228ad0113 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,96 +1,96 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.512589 # Number of seconds simulated -sim_ticks 512588680500 # Number of ticks simulated -final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.512877 # Number of seconds simulated +sim_ticks 512876814500 # Number of ticks simulated +final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180394 # Simulator instruction rate (inst/s) -host_op_rate 222088 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144333179 # Simulator tick rate (ticks/s) -host_mem_usage 275860 # Number of bytes of host memory used -host_seconds 3551.43 # Real time elapsed on the host +host_inst_rate 169706 # Simulator instruction rate (inst/s) +host_op_rate 208931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 135858559 # Simulator tick rate (ticks/s) +host_mem_usage 281524 # Number of bytes of host memory used +host_seconds 3775.08 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory -system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory +system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291222 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291229 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts -system.physmem.perBankRdBursts::2 18220 # Per bank write bursts -system.physmem.perBankRdBursts::3 18178 # Per bank write bursts -system.physmem.perBankRdBursts::4 18281 # Per bank write bursts -system.physmem.perBankRdBursts::5 18410 # Per bank write bursts -system.physmem.perBankRdBursts::6 18174 # Per bank write bursts -system.physmem.perBankRdBursts::7 17993 # Per bank write bursts -system.physmem.perBankRdBursts::8 18029 # Per bank write bursts -system.physmem.perBankRdBursts::9 18057 # Per bank write bursts -system.physmem.perBankRdBursts::10 18103 # Per bank write bursts -system.physmem.perBankRdBursts::11 18205 # Per bank write bursts -system.physmem.perBankRdBursts::12 18223 # Per bank write bursts -system.physmem.perBankRdBursts::13 18272 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18257 # Per bank write bursts +system.physmem.perBankRdBursts::0 18285 # Per bank write bursts +system.physmem.perBankRdBursts::1 18130 # Per bank write bursts +system.physmem.perBankRdBursts::2 18219 # Per bank write bursts +system.physmem.perBankRdBursts::3 18177 # Per bank write bursts +system.physmem.perBankRdBursts::4 18285 # Per bank write bursts +system.physmem.perBankRdBursts::5 18413 # Per bank write bursts +system.physmem.perBankRdBursts::6 18173 # Per bank write bursts +system.physmem.perBankRdBursts::7 17985 # Per bank write bursts +system.physmem.perBankRdBursts::8 18026 # Per bank write bursts +system.physmem.perBankRdBursts::9 18055 # Per bank write bursts +system.physmem.perBankRdBursts::10 18102 # Per bank write bursts +system.physmem.perBankRdBursts::11 18206 # Per bank write bursts +system.physmem.perBankRdBursts::12 18220 # Per bank write bursts +system.physmem.perBankRdBursts::13 18274 # Per bank write bursts +system.physmem.perBankRdBursts::14 18073 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4135 # Per bank write bursts +system.physmem.perBankWrBursts::1 4098 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4223 # Per bank write bursts -system.physmem.perBankWrBursts::5 4222 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4092 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 512588586500 # Total gap between requests +system.physmem.totGap 512876719500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291222 # Read request sizes (log2) +system.physmem.readPktSize::6 291229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,7 +98,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,87 +194,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads -system.physmem.totQLat 2758807250 # Total ticks spent queuing -system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads +system.physmem.totQLat 2756382250 # Total ticks spent queuing +system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 195021 # Number of row buffer hits during reads -system.physmem.writeRowHits 51610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes -system.physmem.avgGap 1434536.51 # Average gap between requests -system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.106023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states -system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states +system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing +system.physmem.readRowHits 194946 # Number of row buffer hits during reads +system.physmem.writeRowHits 51576 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes +system.physmem.avgGap 1435314.77 # Average gap between requests +system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.111511 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states +system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.023062 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states -system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states +system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.035798 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states +system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 147261658 # Number of BP lookups system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect @@ -289,7 +288,7 @@ system.cpu.branchPred.indirectHits 15988941 # Nu system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -319,7 +318,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -349,7 +348,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,7 +378,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,16 +409,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1025177361 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1025753629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.600202 # CPI: cycles per instruction -system.cpu.ipc 0.624921 # IPC: instructions per cycle +system.cpu.cpi 1.601101 # CPI: cycles per instruction +system.cpu.ipc 0.624570 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -455,28 +454,28 @@ system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked +system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits @@ -501,14 +500,14 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -533,22 +532,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88716 # number of writebacks -system.cpu.dcache.writebacks::total 88716 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks +system.cpu.dcache.writebacks::total 88688 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -567,16 +566,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -587,70 +586,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659204 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits -system.cpu.icache.overall_hits::total 257789647 # number of overall hits +system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits +system.cpu.icache.overall_hits::total 257789646 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 257816284 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 257816284 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 257816284 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 257816284 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,90 +664,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 26637 system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258816 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258837 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits -system.cpu.l2cache.overall_hits::total 517580 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits +system.cpu.l2cache.overall_hits::total 517573 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses -system.cpu.l2cache.overall_misses::total 291253 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses +system.cpu.l2cache.overall_misses::total 291260 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) @@ -767,26 +766,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,61 +808,61 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution @@ -872,53 +871,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258816 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258837 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225131 # Transaction distribution +system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225138 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190690 # Transaction distribution +system.membus.trans_dist::CleanEvict 190702 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 548010 # Request fanout histogram +system.membus.snoop_fanout::samples 291229 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548010 # Request fanout histogram -system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291229 # Request fanout histogram +system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index c91bb3ccb..2975218ad 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.326731 # Number of seconds simulated -sim_ticks 326731324000 # Number of ticks simulated -final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.327896 # Number of seconds simulated +sim_ticks 327895638000 # Number of ticks simulated +final_tick 327895638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165193 # Simulator instruction rate (inst/s) -host_op_rate 203374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84248396 # Simulator tick rate (ticks/s) -host_mem_usage 272920 # Number of bytes of host memory used -host_seconds 3878.19 # Real time elapsed on the host +host_inst_rate 125299 # Simulator instruction rate (inst/s) +host_op_rate 154259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64130088 # Simulator tick rate (ticks/s) +host_mem_usage 277300 # Number of bytes of host memory used +host_seconds 5112.98 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory -system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 953240 # Number of read requests accepted -system.physmem.writeReqs 66334 # Number of write requests accepted -system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 266368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48003200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12980224 # Number of bytes read from this memory +system.physmem.bytes_read::total 61249792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 266368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 266368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244096 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 957028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66314 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66314 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 812356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146397800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 39586449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186796605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12943435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12943435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12943435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146397800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 39586449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 199740040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 957029 # Number of read requests accepted +system.physmem.writeReqs 66314 # Number of write requests accepted +system.physmem.readBursts 957029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66314 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61231232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue +system.physmem.bytesWritten 4237440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61249856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 72 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19685 # Per bank write bursts -system.physmem.perBankRdBursts::1 19287 # Per bank write bursts -system.physmem.perBankRdBursts::2 657567 # Per bank write bursts -system.physmem.perBankRdBursts::3 20052 # Per bank write bursts -system.physmem.perBankRdBursts::4 19480 # Per bank write bursts -system.physmem.perBankRdBursts::5 20770 # Per bank write bursts -system.physmem.perBankRdBursts::6 19386 # Per bank write bursts -system.physmem.perBankRdBursts::7 19760 # Per bank write bursts -system.physmem.perBankRdBursts::8 19321 # Per bank write bursts -system.physmem.perBankRdBursts::9 19768 # Per bank write bursts -system.physmem.perBankRdBursts::10 19303 # Per bank write bursts -system.physmem.perBankRdBursts::11 19444 # Per bank write bursts -system.physmem.perBankRdBursts::12 19433 # Per bank write bursts -system.physmem.perBankRdBursts::13 20871 # Per bank write bursts -system.physmem.perBankRdBursts::14 19269 # Per bank write bursts -system.physmem.perBankRdBursts::15 19527 # Per bank write bursts -system.physmem.perBankWrBursts::0 4288 # Per bank write bursts -system.physmem.perBankWrBursts::1 4110 # Per bank write bursts -system.physmem.perBankWrBursts::2 4140 # Per bank write bursts -system.physmem.perBankWrBursts::3 4154 # Per bank write bursts -system.physmem.perBankWrBursts::4 4242 # Per bank write bursts -system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankRdBursts::0 19913 # Per bank write bursts +system.physmem.perBankRdBursts::1 19609 # Per bank write bursts +system.physmem.perBankRdBursts::2 657177 # Per bank write bursts +system.physmem.perBankRdBursts::3 20974 # Per bank write bursts +system.physmem.perBankRdBursts::4 19738 # Per bank write bursts +system.physmem.perBankRdBursts::5 20841 # Per bank write bursts +system.physmem.perBankRdBursts::6 19544 # Per bank write bursts +system.physmem.perBankRdBursts::7 20056 # Per bank write bursts +system.physmem.perBankRdBursts::8 19527 # Per bank write bursts +system.physmem.perBankRdBursts::9 20071 # Per bank write bursts +system.physmem.perBankRdBursts::10 19467 # Per bank write bursts +system.physmem.perBankRdBursts::11 19786 # Per bank write bursts +system.physmem.perBankRdBursts::12 19618 # Per bank write bursts +system.physmem.perBankRdBursts::13 21115 # Per bank write bursts +system.physmem.perBankRdBursts::14 19501 # Per bank write bursts +system.physmem.perBankRdBursts::15 19801 # Per bank write bursts +system.physmem.perBankWrBursts::0 4241 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts +system.physmem.perBankWrBursts::2 4141 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::5 4233 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4146 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 326731313500 # Total gap between requests +system.physmem.totGap 327895627500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 953240 # Read request sizes (log2) +system.physmem.readPktSize::6 957029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66334 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66314 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 765529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 621 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,48 +149,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -198,120 +198,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads -system.physmem.totQLat 12733277648 # Total ticks spent queuing -system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 194181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.148207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.280987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 364.158297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 64676 33.31% 33.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60636 31.23% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15729 8.10% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3217 1.66% 74.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3574 1.84% 76.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2317 1.19% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2364 1.22% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21831 11.24% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19837 10.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 194181 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 177.226065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.842577 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1813.556545 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3969 99.47% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 4 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 2 0.05% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-32767 2 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::86016-90111 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.593985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.513577 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.886226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3332 83.51% 83.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 5 0.13% 83.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 452 11.33% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 50 1.25% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 19 0.48% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.43% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.25% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.48% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.30% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.38% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.40% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.38% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 9 0.23% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.13% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.08% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.08% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3990 # Writes before turning the bus around for reads +system.physmem.totQLat 12587538724 # Total ticks spent queuing +system.physmem.totMemAccLat 30526376224 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4783690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13156.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31906.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 186.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 186.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.56 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing -system.physmem.readRowHits 805882 # Number of row buffer hits during reads -system.physmem.writeRowHits 26140 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes -system.physmem.avgGap 320458.66 # Average gap between requests -system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) -system.physmem_0.averagePower 771.975754 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states -system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 805843 # Number of row buffer hits during reads +system.physmem.writeRowHits 22921 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.60 # Row buffer hit rate for writes +system.physmem.avgGap 320416.15 # Average gap between requests +system.physmem.pageHitRate 81.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 934317720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 509796375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6223237800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216334800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 220944760020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2925699000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 253170624435 # Total energy per rank (pJ) +system.physmem_0.averagePower 772.109253 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3595093339 # Time in different power states +system.physmem_0.memoryStateTime::REF 10949120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states +system.physmem_0.memoryStateTime::ACT 313351421161 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) -system.physmem_1.averagePower 704.579541 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states -system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem_1.actEnergy 533690640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 291200250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1239209400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88116969465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 119441319000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 231251573475 # Total energy per rank (pJ) +system.physmem_1.averagePower 705.261391 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 198129163855 # Time in different power states +system.physmem_1.memoryStateTime::REF 10949120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states +system.physmem_1.memoryStateTime::ACT 118816573145 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174663372 # Number of BP lookups -system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174659739 # Number of BP lookups +system.cpu.branchPred.condPredicted 119113225 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015668 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720974 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67755362 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.052398 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785155 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 16716286 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16701799 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14487 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279501 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +347,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -371,7 +377,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,7 +407,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -432,85 +438,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 653462649 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 655791277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 34353189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824276690 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174659739 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103242316 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 616975428 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3170 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247740649 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12515 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 655368010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.551156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.253828 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 193301276 29.50% 29.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148337850 22.63% 52.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72946568 11.13% 63.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240782316 36.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4317999600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 655368010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.266334 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.256919 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75112130 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 236493276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277761287 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61980307 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021010 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20809608 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13112 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924575224 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804312 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021010 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118055519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 135785787 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 212608 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294557237 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102735849 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906541412 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891100 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27959034 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218150 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49337765 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 468731 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980926815 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318009248 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001835221 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457086 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244402361 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106148585 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6844 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6835 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138814111 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271882035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160585921 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6159068 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12159693 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899827224 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12580 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860029296 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216848 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114846 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244387313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 655368010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.312285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.094624 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 192710599 29.40% 29.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182406257 27.83% 57.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175554116 26.79% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92275656 14.08% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12419071 1.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -518,9 +524,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 655368010 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66605310 24.62% 24.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available @@ -549,13 +555,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134121363 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69112589 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413090005 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187656 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -577,88 +583,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550150 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478194 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665504 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157232585 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued -system.cpu.iq.rate 1.316105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860029296 # Type of FU issued +system.cpu.iq.rate 1.311438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270494293 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314518 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2597595667 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980331886 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820082893 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57542076 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878673 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098503163 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020426 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13986768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 19641097 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18820 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31605425 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 17201 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021010 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10590461 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849934 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271882035 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160585921 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6840 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 959 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3423 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18820 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290187 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585316 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850173752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263373804 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855544 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10252 # number of nop insts executed -system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed -system.cpu.iew.exec_branches 143379422 # Number of branches executed -system.cpu.iew.exec_stores 152688943 # Number of stores executed -system.cpu.iew.exec_rate 1.301023 # Inst execution rate -system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487338276 # num instructions producing a value -system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value -system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10130 # number of nop insts executed +system.cpu.iew.exec_refs 416063188 # number of memory reference insts executed +system.cpu.iew.exec_branches 143381327 # Number of branches executed +system.cpu.iew.exec_stores 152689384 # Number of stores executed +system.cpu.iew.exec_rate 1.296409 # Inst execution rate +system.cpu.iew.wb_sent 846297655 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844961566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487343298 # num instructions producing a value +system.cpu.iew.wb_consumers 808106626 # num instructions consuming a value +system.cpu.iew.wb_rate 1.288461 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603068 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103169122 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002654 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 640787345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.230876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.070419 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 350447626 54.69% 54.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137241088 21.42% 76.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51341072 8.01% 84.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28220230 4.40% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14380949 2.24% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774505 2.31% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871971 1.23% 94.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561231 1.02% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29948673 4.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 640787345 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,82 +710,82 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1500478116 # The number of ROB reads -system.cpu.rob.rob_writes 1798380886 # The number of ROB writes -system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29948673 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1502729113 # The number of ROB reads +system.cpu.rob.rob_writes 1798382436 # The number of ROB writes +system.cpu.timesIdled 10485 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 423267 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868460109 # number of integer regfile reads -system.cpu.int_regfile_writes 500697086 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads -system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes -system.cpu.misc_regfile_reads 606830951 # number of misc regfile reads +system.cpu.cpi 1.023635 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.023635 # CPI: Total CPI of All Threads +system.cpu.ipc 0.976910 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.976910 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868461212 # number of integer regfile reads +system.cpu.int_regfile_writes 500699124 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616064 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959493 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322386264 # number of cc regfile reads +system.cpu.cc_regfile_writes 369207629 # number of cc regfile writes +system.cpu.misc_regfile_reads 606832888 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756452 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756458 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.912011 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371050492 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756970 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.586336 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 274880000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.912011 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999828 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999828 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751746846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751746846 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243126867 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243126867 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907624 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907624 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits -system.cpu.dcache.overall_hits::total 371035352 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371034491 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371034491 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371037648 # number of overall hits +system.cpu.dcache.overall_hits::total 371037648 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043853 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043853 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses -system.cpu.dcache.overall_misses::total 3447085 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3445163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3445163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3445810 # number of overall misses +system.cpu.dcache.overall_misses::total 3445810 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69278020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69278020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9882341350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9882341350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 168500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 168500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 79160361350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 79160361350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 79160361350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 79160361350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245528177 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245528177 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -788,70 +794,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374479654 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374479654 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374483458 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374483458 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9467.177227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9467.177227 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22977.247042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22972.932736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22972.932736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 322646 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4628 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks -system.cpu.dcache.writebacks::total 2756452 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 69.716076 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756458 # number of writebacks +system.cpu.dcache.writebacks::total 2756458 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365828 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 365828 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322833 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 322833 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 688661 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 688661 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 688661 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 688661 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035482 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035482 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721020 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721020 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756502 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756502 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64102936000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64102936000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5940509850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5940509850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5561000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5561000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 70043445850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 70043445850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 70049006850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 70049006850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses @@ -862,389 +868,395 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1979880 # number of replacements -system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31492.755033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31492.755033 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8239.036157 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8239.036157 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8661.993769 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8661.993769 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25410.264839 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25410.264839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25406.365010 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25406.365010 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1979522 # number of replacements +system.cpu.icache.tags.tagsinuse 510.874726 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245757404 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.117895 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 264413500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.874726 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997802 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits -system.cpu.icache.overall_hits::total 245759426 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses -system.cpu.icache.overall_misses::total 1983591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16128682925 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16128682925 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16128682925 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16128682925 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16128682925 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16128682925 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247743017 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247743017 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247743017 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247743017 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247743017 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247743017 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8131.052684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8131.052684 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8131.052684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 497461440 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497461440 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245757408 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245757408 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245757408 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245757408 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245757408 # number of overall hits +system.cpu.icache.overall_hits::total 245757408 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1983209 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1983209 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1983209 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1983209 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1983209 # number of overall misses +system.cpu.icache.overall_misses::total 1983209 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16177953926 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16177953926 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16177953926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16177953926 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16177953926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16177953926 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247740617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247740617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247740617 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247740617 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247740617 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247740617 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8157.462943 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8157.462943 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8157.462943 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8157.462943 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75964 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2856 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks -system.cpu.icache.writebacks::total 1979880 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980577 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1980577 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1980577 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1980577 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1980577 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1980577 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15098139938 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15098139938 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15098139938 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15098139938 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15098139938 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15098139938 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007994 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007994 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 26.598039 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 24.400000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks +system.cpu.icache.writebacks::total 1979522 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3001 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3001 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3001 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3001 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3001 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3001 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980208 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1980208 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1980208 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1980208 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1980208 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1980208 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15149087440 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15149087440 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15149087440 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15149087440 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15149087440 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15149087440 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7650.250600 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7650.250600 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350340 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355050 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 4121 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 301370 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.600812 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997951 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6334 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 10030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1704 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1287256 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1287256 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1976843 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2005757 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3982600 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1976843 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2005757 # number of overall hits -system.cpu.l2cache.overall_hits::total 3982600 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 185 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 185 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2346 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2346 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3550 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3550 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 748861 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 748861 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3550 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 751207 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 754757 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3550 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 751207 # number of overall misses -system.cpu.l2cache.overall_misses::total 754757 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195074000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 195074000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261372000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 261372000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 51585571000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 51585571000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 261372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 51780645000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 52042017000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 261372000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 51780645000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 52042017000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 736314 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 736314 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3356496 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3356496 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980393 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1980393 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036117 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2036117 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1980393 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756964 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4737357 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1980393 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756964 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4737357 # number of overall (read+write) accesses +system.cpu.l2cache.prefetcher.pfSpanPage 4790102 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 297234 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16098.063865 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3815891 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 313429 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.174658 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15670.505298 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 427.558566 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.956452 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.026096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 418 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15777 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1577 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3842 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9849 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025513 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962952 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145585225 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145585225 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 735545 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 735545 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3357840 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3357840 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718742 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718742 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975871 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1975871 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286733 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1286733 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1975871 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2005475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3981346 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1975871 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2005475 # number of overall hits +system.cpu.l2cache.overall_hits::total 3981346 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 174 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 174 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2104 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2104 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4164 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4164 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749391 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 749391 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4164 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 751495 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 755659 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4164 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 751495 # number of overall misses +system.cpu.l2cache.overall_misses::total 755659 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 179065000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 179065000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 319741500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 319741500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 52681851500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 52681851500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 319741500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 52860916500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 53180658000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 319741500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 52860916500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 53180658000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 735545 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 735545 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3357840 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3357840 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 174 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 174 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980035 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1980035 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036124 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2036124 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756970 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4737005 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756970 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4737005 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003255 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003255 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.001793 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.001793 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.367789 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.367789 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.001793 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.272476 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159320 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.001793 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.272476 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159320 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68952.016344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002919 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002919 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002103 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002103 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368048 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368048 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002103 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.272580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159523 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002103 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.272580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159523 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85106.939163 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85106.939163 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76787.103746 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76787.103746 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70299.551903 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70299.551903 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70376.529625 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70376.529625 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks -system.cpu.l2cache.writebacks::total 66334 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 3678 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 66314 # number of writebacks +system.cpu.l2cache.writebacks::total 66314 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 742 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 742 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 903 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 703 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 703 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1866 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1867 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1445 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1446 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1866 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1867 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200438 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 200438 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 185 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 185 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1383 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1383 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3549 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3549 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 747958 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 747958 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3549 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 749341 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 752890 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3549 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 749341 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 953328 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16667426112 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2605000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2605000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 137246500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 137246500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240029500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240029500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 47054888500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 47054888500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240029500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47192135000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 47432164500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240029500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47192135000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 1445 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1446 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202914 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202914 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1362 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1362 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748688 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748688 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 750050 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 754213 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 750050 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202914 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 957127 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16536801285 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2630000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2630000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133214500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133214500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 294714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 294714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 48154340500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 48154340500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 294714000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48287555000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 48582269000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294714000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48287555000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 65119070285 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002102 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159217 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4257152 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202053 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9473332 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736180 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 642769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4016330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 230920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 258553 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036124 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270746 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14210509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606270912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 555960 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4255168 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5293139 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121491 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.326697 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4650072 87.85% 87.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 643066 12.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5293139 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9472646000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2970310996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135552978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 951856 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution -system.membus.trans_dist::CleanEvict 227102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 185 # Transaction distribution -system.membus.trans_dist::ReadExReq 1383 # Transaction distribution -system.membus.trans_dist::ReadExResp 1383 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 1254437 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 940010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 955666 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66314 # Transaction distribution +system.membus.trans_dist::CleanEvict 230920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 1362 # Transaction distribution +system.membus.trans_dist::ReadExResp 1362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 955667 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2211465 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65493888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65493888 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1246861 # Request fanout histogram +system.membus.snoop_fanout::samples 957203 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1246861 # Request fanout histogram -system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 957203 # Request fanout histogram +system.membus.reqLayer0.occupancy 1755655982 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5035261795 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 889d833d4..e76db2752 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 860032 # Simulator instruction rate (inst/s) -host_op_rate 1058813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 531234389 # Simulator tick rate (ticks/s) -host_mem_usage 264584 # Number of bytes of host memory used -host_seconds 744.92 # Real time elapsed on the host +host_inst_rate 969638 # Simulator instruction rate (inst/s) +host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 598936996 # Simulator tick rate (ticks/s) +host_mem_usage 268708 # Number of bytes of host memory used +host_seconds 660.72 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 893703778 # Transaction distribution system.membus.trans_dist::ReadResp 893709517 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 4241547525 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1022670353 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 3a062984a..c71a30606 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.045756 # Number of seconds simulated -sim_ticks 1045756396500 # Number of ticks simulated -final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.046047 # Number of seconds simulated +sim_ticks 1046047111500 # Number of ticks simulated +final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 546786 # Simulator instruction rate (inst/s) -host_op_rate 671760 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 894330624 # Simulator tick rate (ticks/s) -host_mem_usage 273552 # Number of bytes of host memory used -host_seconds 1169.32 # Real time elapsed on the host +host_inst_rate 666714 # Simulator instruction rate (inst/s) +host_op_rate 819099 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1090788712 # Simulator tick rate (ticks/s) +host_mem_usage 278188 # Number of bytes of host memory used +host_seconds 958.98 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory -system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory +system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2091512793 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2092094223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks -system.cpu.dcache.writebacks::total 88995 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks +system.cpu.dcache.writebacks::total 88967 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits @@ -329,16 +329,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -349,26 +349,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id @@ -376,7 +376,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits @@ -389,12 +389,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -407,12 +407,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,90 +427,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 257772 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 257791 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits -system.cpu.l2cache.overall_hits::total 501982 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits +system.cpu.l2cache.overall_hits::total 501975 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses -system.cpu.l2cache.overall_misses::total 290368 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses +system.cpu.l2cache.overall_misses::total 290375 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) @@ -529,26 +529,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,61 +561,61 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution @@ -624,53 +624,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257772 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257791 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224275 # Transaction distribution +system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 224282 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190094 # Transaction distribution +system.membus.trans_dist::CleanEvict 190103 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 546561 # Request fanout histogram +system.membus.snoop_fanout::samples 290376 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 546561 # Request fanout histogram -system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 290376 # Request fanout histogram +system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |