diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/long/se/40.perlbmk/ref | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
6 files changed, 1239 insertions, 1205 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 0cd2c8d2d..dc4595f22 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.560940 # Nu sim_ticks 560939659000 # Number of ticks simulated final_tick 560939659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234960 # Simulator instruction rate (inst/s) -host_op_rate 234960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 141903449 # Simulator tick rate (ticks/s) -host_mem_usage 300504 # Number of bytes of host memory used -host_seconds 3952.97 # Real time elapsed on the host +host_inst_rate 314051 # Simulator instruction rate (inst/s) +host_op_rate 314051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189670339 # Simulator tick rate (ticks/s) +host_mem_usage 308244 # Number of bytes of host memory used +host_seconds 2957.45 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -693,6 +693,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1580028 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2077 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723921 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155535 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 890983 # Transaction distribution @@ -708,15 +714,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56434176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 259423 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1839451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141033 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001129 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.033584 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1580028 85.90% 85.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259423 14.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1837374 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2077 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1839451 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 878866000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4ab8a79d0..4dbf3fd00 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.276406 # Nu sim_ticks 276406029500 # Number of ticks simulated final_tick 276406029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130885 # Simulator instruction rate (inst/s) -host_op_rate 130885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42946592 # Simulator tick rate (ticks/s) -host_mem_usage 301528 # Number of bytes of host memory used -host_seconds 6436.04 # Real time elapsed on the host +host_inst_rate 172081 # Simulator instruction rate (inst/s) +host_op_rate 172081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56464121 # Simulator tick rate (ticks/s) +host_mem_usage 308248 # Number of bytes of host memory used +host_seconds 4895.25 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1000,6 +1000,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1569303 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1986 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1986 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 718745 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155563 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 885494 # Transaction distribution @@ -1015,15 +1021,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56091520 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 259305 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1828608 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1569303 85.82% 85.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259305 14.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1826622 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1986 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1828608 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 873531500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 07561ac8e..f1fff22ed 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.286279 # Nu sim_ticks 1286278511500 # Number of ticks simulated final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1355944 # Simulator instruction rate (inst/s) -host_op_rate 1355944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1878251411 # Simulator tick rate (ticks/s) -host_mem_usage 303804 # Number of bytes of host memory used -host_seconds 684.83 # Real time elapsed on the host +host_inst_rate 1389844 # Simulator instruction rate (inst/s) +host_op_rate 1389844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1925210162 # Simulator tick rate (ticks/s) +host_mem_usage 305148 # Number of bytes of host memory used +host_seconds 668.12 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -484,6 +484,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution @@ -499,15 +505,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258580 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141585 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348624 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000941 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030656 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1567746 85.84% 85.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 258580 14.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1824608 99.91% 99.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1718 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 53f1e9393..ca22b895a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.542258 # Number of seconds simulated -sim_ticks 542257602500 # Number of ticks simulated -final_tick 542257602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 542257676500 # Number of ticks simulated +final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121737 # Simulator instruction rate (inst/s) -host_op_rate 149875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103039759 # Simulator tick rate (ticks/s) -host_mem_usage 317376 # Number of bytes of host memory used -host_seconds 5262.61 # Real time elapsed on the host +host_inst_rate 169610 # Simulator instruction rate (inst/s) +host_op_rate 208813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 143560034 # Simulator tick rate (ticks/s) +host_mem_usage 325880 # Number of bytes of host memory used +host_seconds 3777.22 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288602 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34062276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34365954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7801222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7801222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7801222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34062276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42167176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291175 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18614208 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18282 # Per bank write bursts -system.physmem.perBankRdBursts::1 18134 # Per bank write bursts -system.physmem.perBankRdBursts::2 18219 # Per bank write bursts -system.physmem.perBankRdBursts::3 18172 # Per bank write bursts -system.physmem.perBankRdBursts::4 18271 # Per bank write bursts -system.physmem.perBankRdBursts::5 18399 # Per bank write bursts +system.physmem.perBankRdBursts::1 18135 # Per bank write bursts +system.physmem.perBankRdBursts::2 18220 # Per bank write bursts +system.physmem.perBankRdBursts::3 18173 # Per bank write bursts +system.physmem.perBankRdBursts::4 18273 # Per bank write bursts +system.physmem.perBankRdBursts::5 18400 # Per bank write bursts system.physmem.perBankRdBursts::6 18176 # Per bank write bursts -system.physmem.perBankRdBursts::7 17991 # Per bank write bursts -system.physmem.perBankRdBursts::8 18028 # Per bank write bursts +system.physmem.perBankRdBursts::7 17989 # Per bank write bursts +system.physmem.perBankRdBursts::8 18030 # Per bank write bursts system.physmem.perBankRdBursts::9 18057 # Per bank write bursts system.physmem.perBankRdBursts::10 18104 # Per bank write bursts system.physmem.perBankRdBursts::11 18195 # Per bank write bursts -system.physmem.perBankRdBursts::12 18215 # Per bank write bursts -system.physmem.perBankRdBursts::13 18268 # Per bank write bursts -system.physmem.perBankRdBursts::14 18078 # Per bank write bursts -system.physmem.perBankRdBursts::15 18258 # Per bank write bursts +system.physmem.perBankRdBursts::12 18214 # Per bank write bursts +system.physmem.perBankRdBursts::13 18267 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18257 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4098 # Per bank write bursts system.physmem.perBankWrBursts::2 4134 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542257509000 # Total gap between requests +system.physmem.totGap 542257582000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 205.695554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.912944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.637901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45880 41.32% 41.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43577 39.24% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9434 8.50% 89.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1633 1.47% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.509833 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.246439 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.588678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes @@ -224,12 +224,12 @@ system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Wr system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 2871354000 # Total ticks spent queuing -system.physmem.totMemAccLat 8324735250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9872.39 # Average queueing delay per DRAM burst +system.physmem.totQLat 2868100000 # Total ticks spent queuing +system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28622.39 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s @@ -240,47 +240,47 @@ system.physmem.busUtilRead 0.27 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing -system.physmem.readRowHits 194229 # Number of row buffer hits during reads -system.physmem.writeRowHits 51633 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.12 # Row buffer hit rate for writes -system.physmem.avgGap 1517767.95 # Average gap between requests -system.physmem.pageHitRate 68.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 420124320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 229234500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1135836000 # Energy for read commands per rank (pJ) +system.physmem.readRowHits 194250 # Number of row buffer hits during reads +system.physmem.writeRowHits 51642 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 1517768.15 # Average gap between requests +system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107502461415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231049769250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375970079325 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.351550 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383670371250 # Time in different power states +system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.324021 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140473012000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 419247360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 228756000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132271400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 108055650690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230564511000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 376030187250 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.462409 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 382864555750 # Time in different power states +system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.447269 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141281958750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 154805772 # Number of BP lookups +system.cpu.branchPred.lookups 154805770 # Number of BP lookups system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90693369 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.615651 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -401,24 +401,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1084515205 # number of cpu cycles simulated +system.cpu.numCycles 1084515353 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23906785 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.692822 # CPI: cycles per instruction +system.cpu.cpi 1.692823 # CPI: cycles per instruction system.cpu.ipc 0.590729 # IPC: instructions per cycle -system.cpu.tickCycles 1025899032 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58616173 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778339 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.484062 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484062 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -454,14 +454,14 @@ system.cpu.dcache.demand_misses::cpu.data 851588 # n system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses system.cpu.dcache.overall_misses::total 851729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762813000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24762813000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105718500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105718500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34868531500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34868531500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34868531500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34868531500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -486,14 +486,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40945.306298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40938.527982 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,16 +522,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782296 system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24034165000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24034165000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29102077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29102077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29103932500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29103932500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -542,24 +542,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33709.735558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33709.735558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73106.841984 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73106.841984 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37200.851724 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37200.851724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37196.613776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23591 # number of replacements -system.cpu.icache.tags.tagsinuse 1713.095623 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 291576498 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11505.662458 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095623 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -567,44 +567,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 58 system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 583229024 # Number of tag accesses -system.cpu.icache.tags.data_accesses 583229024 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 291576498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 291576498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 291576498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 291576498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 291576498 # number of overall hits -system.cpu.icache.overall_hits::total 291576498 # number of overall hits +system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits +system.cpu.icache.overall_hits::total 291576499 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses system.cpu.icache.overall_misses::total 25343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 498098000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 498098000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 498098000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 498098000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 498098000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 498098000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 291601841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 291601841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 291601841 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 291601841 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 291601841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 291601841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19654.263505 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19654.263505 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,37 +619,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25343 system.cpu.icache.demand_mshr_misses::total 25343 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25343 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 472756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 472756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 472756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 472756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 472756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 472756000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18654.302963 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18654.302963 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258395 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32574.709364 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1245326 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291139 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.277428 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156166 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.700113 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29894.853085 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.079015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002768 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.912319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994101 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id @@ -686,18 +686,18 @@ system.cpu.l2cache.demand_misses::total 291208 # nu system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288630 # number of overall misses system.cpu.l2cache.overall_misses::total 291208 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4930001500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4930001500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195708000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 195708000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17815243000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17815243000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 195708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22745244500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22940952500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 195708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22745244500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22940952500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 88920 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 88920 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) @@ -724,18 +724,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.360505 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101724 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.368887 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.360505 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74594.142924 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74594.142924 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75914.662529 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75914.662529 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80054.475845 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80054.475845 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78778.579229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78778.579229 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,69 +746,75 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # 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number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2574 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2574 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222511 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222511 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288603 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291176 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4269091500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4269091500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169723000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169723000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15588307500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15588307500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169723000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19857399000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20027122000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169723000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19857399000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20027122000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268970500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268970500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169583000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169583000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15585424500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15585424500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169583000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19854395000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20023978000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169583000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19854395000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20023978000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312028 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312028 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312029 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312029 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64594.142924 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64594.142924 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3351 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution @@ -824,21 +830,21 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258395 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1609708 86.17% 86.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 258395 13.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38014996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173666472 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 225084 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution @@ -861,9 +867,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 547917 # Request fanout histogram -system.membus.reqLayer0.occupancy 917948500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554418250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 85998f5be..8ea31b650 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410670 # Number of seconds simulated -sim_ticks 410669815000 # Number of ticks simulated -final_tick 410669815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410968 # Number of seconds simulated +sim_ticks 410968419000 # Number of ticks simulated +final_tick 410968419000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94058 # Simulator instruction rate (inst/s) -host_op_rate 115798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60293323 # Simulator tick rate (ticks/s) -host_mem_usage 320128 # Number of bytes of host memory used -host_seconds 6811.20 # Real time elapsed on the host +host_inst_rate 85599 # Simulator instruction rate (inst/s) +host_op_rate 105384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54910730 # Simulator tick rate (ticks/s) +host_mem_usage 322152 # Number of bytes of host memory used +host_seconds 7484.30 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 232448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7026304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12953152 # Number of bytes read from this memory -system.physmem.bytes_read::total 20211904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244928 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244928 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109786 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202393 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66327 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66327 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 566022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17109375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31541524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49216921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 566022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 566022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10336596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10336596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10336596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 566022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17109375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31541524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59553517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315811 # Number of read requests accepted -system.physmem.writeReqs 66327 # Number of write requests accepted -system.physmem.readBursts 315811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66327 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20192576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 4239424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20211904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244928 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 58 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19865 # Per bank write bursts -system.physmem.perBankRdBursts::1 19533 # Per bank write bursts -system.physmem.perBankRdBursts::2 19787 # Per bank write bursts -system.physmem.perBankRdBursts::3 19881 # Per bank write bursts -system.physmem.perBankRdBursts::4 19767 # Per bank write bursts -system.physmem.perBankRdBursts::5 20312 # Per bank write bursts -system.physmem.perBankRdBursts::6 19558 # Per bank write bursts -system.physmem.perBankRdBursts::7 19499 # Per bank write bursts -system.physmem.perBankRdBursts::8 19473 # Per bank write bursts -system.physmem.perBankRdBursts::9 19475 # Per bank write bursts -system.physmem.perBankRdBursts::10 19453 # Per bank write bursts -system.physmem.perBankRdBursts::11 19704 # Per bank write bursts -system.physmem.perBankRdBursts::12 19596 # Per bank write bursts -system.physmem.perBankRdBursts::13 20052 # Per bank write bursts -system.physmem.perBankRdBursts::14 19574 # Per bank write bursts -system.physmem.perBankRdBursts::15 19980 # Per bank write bursts -system.physmem.perBankWrBursts::0 4265 # Per bank write bursts -system.physmem.perBankWrBursts::1 4106 # Per bank write bursts -system.physmem.perBankWrBursts::2 4140 # Per bank write bursts -system.physmem.perBankWrBursts::3 4153 # Per bank write bursts -system.physmem.perBankWrBursts::4 4250 # Per bank write bursts -system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 226432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7007424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12927040 # Number of bytes read from this memory +system.physmem.bytes_read::total 20160896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 226432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244672 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 201985 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315014 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66323 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66323 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 550972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17051004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31455069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49057044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 550972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 550972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10328463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10328463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10328463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 550972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17051004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31455069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59385507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315014 # Number of read requests accepted +system.physmem.writeReqs 66323 # Number of write requests accepted +system.physmem.readBursts 315014 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66323 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20141440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19456 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20160896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 304 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 67 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19880 # Per bank write bursts +system.physmem.perBankRdBursts::1 19436 # Per bank write bursts +system.physmem.perBankRdBursts::2 19769 # Per bank write bursts +system.physmem.perBankRdBursts::3 19866 # Per bank write bursts +system.physmem.perBankRdBursts::4 19687 # Per bank write bursts +system.physmem.perBankRdBursts::5 20154 # Per bank write bursts +system.physmem.perBankRdBursts::6 19548 # Per bank write bursts +system.physmem.perBankRdBursts::7 19410 # Per bank write bursts +system.physmem.perBankRdBursts::8 19409 # Per bank write bursts +system.physmem.perBankRdBursts::9 19464 # Per bank write bursts +system.physmem.perBankRdBursts::10 19401 # Per bank write bursts +system.physmem.perBankRdBursts::11 19757 # Per bank write bursts +system.physmem.perBankRdBursts::12 19512 # Per bank write bursts +system.physmem.perBankRdBursts::13 19953 # Per bank write bursts +system.physmem.perBankRdBursts::14 19499 # Per bank write bursts +system.physmem.perBankRdBursts::15 19965 # Per bank write bursts +system.physmem.perBankWrBursts::0 4261 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4243 # Per bank write bursts +system.physmem.perBankWrBursts::5 4228 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::9 4094 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4093 # Per bank write bursts -system.physmem.perBankWrBursts::15 4156 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4153 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410669760500 # Total gap between requests +system.physmem.totGap 410968364500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315811 # Read request sizes (log2) +system.physmem.readPktSize::6 315014 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66327 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9282 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66323 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 121710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1023 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,165 +148,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.756150 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.878617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.405742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53923 39.46% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57606 42.15% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14740 10.79% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1412 1.03% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1397 1.02% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1387 1.01% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1267 0.93% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1142 0.84% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3792 2.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136666 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.293227 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.720611 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 661.085009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4010 99.48% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 10 0.25% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.05% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11264-12287 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4031 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4031 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.432895 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.394232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.238105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3399 84.32% 84.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 84.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 453 11.24% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 84 2.08% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 29 0.72% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.42% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 13 0.32% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.25% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.07% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 136515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.576479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.708862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.239774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54117 39.64% 39.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57190 41.89% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14847 10.88% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1353 0.99% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1460 1.07% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1428 1.05% 95.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1211 0.89% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1099 0.81% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3810 2.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136515 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.350768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.698276 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 557.584511 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4013 99.48% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.22% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 4 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.07% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11264-12287 2 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.416708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.380496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.197000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3413 84.61% 84.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 10 0.25% 84.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 440 10.91% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 77 1.91% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.45% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.35% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.25% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.10% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4031 # Writes before turning the bus around for reads -system.physmem.totQLat 8703208249 # Total ticks spent queuing -system.physmem.totMemAccLat 14619001999 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1577545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27584.66 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads +system.physmem.totQLat 8815753021 # Total ticks spent queuing +system.physmem.totMemAccLat 14716565521 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1573550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28012.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46334.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46762.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.46 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.17 # Average write queue length when enqueuing -system.physmem.readRowHits 218486 # Number of row buffer hits during reads -system.physmem.writeRowHits 26585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.12 # Row buffer hit rate for writes -system.physmem.avgGap 1074663.50 # Average gap between requests -system.physmem.pageHitRate 64.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 519334200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 283366875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1233694800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96824469870 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161463849000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 287363708985 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.756123 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267972811336 # Time in different power states -system.physmem_0.memoryStateTime::REF 13712920000 # Time in different power states +system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing +system.physmem.readRowHits 218109 # Number of row buffer hits during reads +system.physmem.writeRowHits 26303 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.70 # Row buffer hit rate for writes +system.physmem.avgGap 1077703.88 # Average gap between requests +system.physmem.pageHitRate 64.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 518041440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282661500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1230403200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96374724480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 162040566750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 287505134730 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.583184 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 268934392735 # Time in different power states +system.physmem_0.memoryStateTime::REF 13723060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128976939914 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128308892015 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 513679320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280281375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1226604600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212718960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96486689295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 161760147750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 287302592820 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.607300 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 268468666587 # Time in different power states -system.physmem_1.memoryStateTime::REF 13712920000 # Time in different power states +system.physmem_1.actEnergy 513943920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280425750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1224030600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96023770920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 162348426750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 287445609300 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.438325 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 269449023468 # Time in different power states +system.physmem_1.memoryStateTime::REF 13723060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 128482733413 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127794271282 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234660907 # Number of BP lookups -system.cpu.branchPred.condPredicted 161885632 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514558 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122787051 # Number of BTB lookups -system.cpu.branchPred.BTBHits 109471469 # Number of BTB hits +system.cpu.branchPred.lookups 234596987 # Number of BP lookups +system.cpu.branchPred.condPredicted 161823961 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514568 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 122849584 # Number of BTB lookups +system.cpu.branchPred.BTBHits 109536151 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.155549 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25674321 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300177 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.162818 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25674290 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -425,95 +421,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 821339631 # number of cpu cycles simulated +system.cpu.numCycles 821936839 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85359172 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200831144 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234660907 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135145790 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 720108706 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063537 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85359069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200718249 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234596987 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135210441 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 720713354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063509 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3327 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 371279487 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652622 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 821005776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.826136 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.165203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3414 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 371348285 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652804 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 821609958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.824964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.165392 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 139284134 16.97% 16.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223266821 27.19% 44.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 99362992 12.10% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359091829 43.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 139667844 17.00% 17.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223418217 27.19% 44.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 99581089 12.12% 56.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 358942808 43.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 821005776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285705 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.462040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121274951 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 160921163 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484660075 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38631496 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518091 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25119096 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248135517 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967011 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518091 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178281745 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80150846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 211317 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82524216 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190646555 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25420306 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24957441 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267221 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41531798 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1705173 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225452951 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812557102 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358174955 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876459 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 821609958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285420 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.460840 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121271680 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 161528221 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484660379 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38631604 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518074 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25181978 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13827 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248136929 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39965779 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518074 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178276857 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80769172 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209944 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464321622 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82514289 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190649625 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25545503 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24955076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2266892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41524383 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1701930 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225389846 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812446196 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358179405 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350674721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 350611616 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7266 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108777970 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366242931 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095379 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1613389 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5371796 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168681315 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017114082 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18565562 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379968716 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032836656 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 821005776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.238863 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084756 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108773290 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366116518 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236097454 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1660812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5332652 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168559259 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12361 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017121345 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18467813 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379846662 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032147150 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 821609958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.237961 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084868 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263349245 32.08% 32.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227125536 27.66% 59.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217733280 26.52% 86.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96668881 11.77% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16128827 1.96% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 263952395 32.13% 32.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227112360 27.64% 59.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217754382 26.50% 86.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96663071 11.77% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16127742 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 821005776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 821609958 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63875016 18.90% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18146 0.01% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63877670 18.90% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.90% # attempts to use FU when none available @@ -541,13 +537,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 157510134 46.60% 65.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 115986364 34.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 157438093 46.58% 65.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116037067 34.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370249 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195831 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456371832 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195828 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -571,88 +567,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322123387 31.67% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215570268 21.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322111232 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215588105 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017114082 # Type of FU issued -system.cpu.iq.rate 1.238360 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338026549 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332339 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3149949023 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1505114950 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934262178 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877028 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565833 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321330304 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960611 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017121345 # Type of FU issued +system.cpu.iq.rate 1.237469 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338007862 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332318 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3150451328 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504870795 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934275536 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876995 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565857 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1321318894 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810313 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960669 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 114001993 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18396 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114883 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113875580 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1094 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18373 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116958 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065819 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19975 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 20149 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518091 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35326945 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 43224 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168699230 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518074 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35327155 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46316 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168577176 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366242931 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46833 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18396 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437302 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221855 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974739392 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42374690 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 366116518 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236097454 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6621 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 106 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 49932 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18373 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437332 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784565 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221897 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974752675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42368670 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497752889 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613606 # Number of branches executed -system.cpu.iew.exec_stores 194455377 # Number of stores executed -system.cpu.iew.exec_rate 1.186768 # Inst execution rate -system.cpu.iew.wb_sent 963712681 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960414622 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536046271 # num instructions producing a value -system.cpu.iew.wb_consumers 893280305 # num instructions consuming a value +system.cpu.iew.exec_refs 497765117 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613949 # Number of branches executed +system.cpu.iew.exec_stores 194467406 # Number of stores executed +system.cpu.iew.exec_rate 1.185922 # Inst execution rate +system.cpu.iew.wb_sent 963726327 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960427986 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536047777 # num instructions producing a value +system.cpu.iew.wb_consumers 893284950 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.169327 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600087 # average fanout of values written-back +system.cpu.iew.wb_rate 1.168494 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357416983 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357420302 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770184473 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.024079 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.777435 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500888 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770788105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.023277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.776928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 431571304 56.03% 56.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174376243 22.64% 78.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72936565 9.47% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32893073 4.27% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8539337 1.11% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14258396 1.85% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7274917 0.94% 96.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5974456 0.78% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360182 2.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 432159906 56.07% 56.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174391468 22.63% 78.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72936790 9.46% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32897876 4.27% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538896 1.11% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14258442 1.85% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269703 0.94% 96.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5974810 0.78% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360214 2.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770184473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770788105 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,80 +694,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360182 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1893962593 # The number of ROB reads -system.cpu.rob.rob_writes 2343119332 # The number of ROB writes -system.cpu.timesIdled 647411 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 333855 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360214 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1894569512 # The number of ROB reads +system.cpu.rob.rob_writes 2343126520 # The number of ROB writes +system.cpu.timesIdled 647387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326881 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.282043 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282043 # CPI: Total CPI of All Threads -system.cpu.ipc 0.780005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.780005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995778090 # number of integer regfile reads -system.cpu.int_regfile_writes 567907785 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads +system.cpu.cpi 1.282975 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282975 # CPI: Total CPI of All Threads +system.cpu.ipc 0.779439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.779439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995803218 # number of integer regfile reads +system.cpu.int_regfile_writes 567908989 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889842 # number of floating regfile reads system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794401386 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898061 # number of cc regfile writes -system.cpu.misc_regfile_reads 715805814 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794442903 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898512 # number of cc regfile writes +system.cpu.misc_regfile_reads 715818410 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756185 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.933524 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216512 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 256787000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.933524 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999870 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756184 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.933181 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258467 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 257783000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.933181 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839346679 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839346679 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293684 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127908123 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127908123 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839346712 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839346712 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286294274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286294274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907939 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907939 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414201807 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414201807 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414204964 # number of overall hits -system.cpu.dcache.overall_hits::total 414204964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3034548 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3034548 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043354 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043354 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414202213 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414202213 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414205370 # number of overall hits +system.cpu.dcache.overall_hits::total 414205370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3033975 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3033975 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043538 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043538 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4077902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4077902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4078548 # number of overall misses -system.cpu.dcache.overall_misses::total 4078548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35018337000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35018337000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10025314350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10025314350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45043651350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45043651350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45043651350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45043651350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328232 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4077513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4077513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4078159 # number of overall misses +system.cpu.dcache.overall_misses::total 4078159 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35335718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35335718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45356506350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45356506350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45356506350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45356506350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328249 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -780,72 +776,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283512 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283512 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008091 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008091 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418279726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283529 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283529 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010486 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008092 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009749 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009749 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009751 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11539.885677 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11539.885677 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9608.737159 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9608.737159 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11045.790544 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11045.790544 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11044.041004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11044.041004 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009748 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009748 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009750 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009750 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11646.674083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11646.674083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9602.705747 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9602.705747 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11123.571243 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11123.571243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11121.809216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11121.809216 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 356457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 355417 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4730 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4792 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.360888 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 74.168823 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735102 # number of writebacks -system.cpu.dcache.writebacks::total 735102 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999338 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999338 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322490 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322490 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735485 # number of writebacks +system.cpu.dcache.writebacks::total 735485 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 998769 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 998769 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322672 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 322672 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1321828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1321828 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1321828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1321828 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035210 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035210 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1321441 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1321441 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1321441 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1321441 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035206 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035206 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720866 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720866 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23819094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23819094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959479350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959479350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6004500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6004500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29778573350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29778573350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29784577850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29784577850 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756072 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756072 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756713 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756713 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24128110500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24128110500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5958496350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5958496350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5922000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5922000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30086606850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30086606850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30092528850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30092528850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses @@ -856,231 +852,233 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11703.506763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11703.506763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8267.134092 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8267.134092 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9367.394696 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9367.394696 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10804.707475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10804.707475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10804.373267 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10804.373267 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11855.365255 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11855.365255 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8265.747518 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8265.747518 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9238.689548 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9238.689548 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10916.480720 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10916.480720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10916.090594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10916.090594 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169482 # number of replacements -system.cpu.icache.tags.tagsinuse 510.670586 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 366104789 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169992 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.813415 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 247000500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.670586 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997403 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169351 # number of replacements +system.cpu.icache.tags.tagsinuse 510.555311 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 366173734 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169861 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.828545 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 247765500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.555311 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 326 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 747728920 # Number of tag accesses -system.cpu.icache.tags.data_accesses 747728920 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 366104823 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 366104823 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 366104823 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 366104823 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 366104823 # number of overall hits -system.cpu.icache.overall_hits::total 366104823 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174632 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174632 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174632 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174632 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174632 # number of overall misses -system.cpu.icache.overall_misses::total 5174632 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647292422 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41647292422 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41647292422 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41647292422 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41647292422 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41647292422 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 371279455 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 371279455 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 371279455 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 371279455 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 371279455 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 371279455 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013937 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013937 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013937 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013937 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013937 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013937 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.358303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8048.358303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.358303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8048.358303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.358303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8048.358303 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 80051 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 126 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3834 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 747866384 # Number of tag accesses +system.cpu.icache.tags.data_accesses 747866384 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 366173762 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 366173762 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 366173762 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 366173762 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 366173762 # number of overall hits +system.cpu.icache.overall_hits::total 366173762 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174491 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174491 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174491 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174491 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174491 # number of overall misses +system.cpu.icache.overall_misses::total 5174491 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41645043922 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41645043922 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41645043922 # 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miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.143078 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8048.143078 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.143078 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8048.143078 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.143078 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8048.143078 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 82369 # 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mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000684 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053105 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053105 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039851 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83502.777137 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16777.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16777.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 103645.757796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 103645.757796 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67311.949339 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67311.949339 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69621.362089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69621.362089 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69961.095241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78640.704259 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039751 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84133.974542 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17187.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17187.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 101015.976761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 101015.976761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68048.756360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68048.756360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69667.055145 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69667.055145 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69998.314592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79063.250502 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7205861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6779490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 246291 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035851 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23134825 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330879552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554354688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 545836 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 16398212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.033285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179381 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 15852127 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925581 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644320 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 9549 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 9495 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 54 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 801808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6778141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 245737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508216 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23134399 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330871168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223499584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554370752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 544470 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 16396581 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.079179 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15852393 96.67% 96.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 545819 3.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 15098363 92.08% 92.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1298164 7.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 54 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 16398212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8661298500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 16396581 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8661548500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755038952 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7754847439 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135066975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135063977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 314432 # Transaction distribution -system.membus.trans_dist::Writeback 66327 # Transaction distribution -system.membus.trans_dist::CleanEvict 232586 # Transaction distribution -system.membus.trans_dist::UpgradeReq 18 # Transaction distribution -system.membus.trans_dist::UpgradeResp 18 # Transaction distribution -system.membus.trans_dist::ReadExReq 1379 # Transaction distribution -system.membus.trans_dist::ReadExResp 1379 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 314432 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 930571 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 930571 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24456832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24456832 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 313637 # Transaction distribution +system.membus.trans_dist::Writeback 66323 # Transaction distribution +system.membus.trans_dist::CleanEvict 231789 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 313637 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 928172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 928172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24405568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24405568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 614742 # Request fanout histogram +system.membus.snoop_fanout::samples 613142 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 614742 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 613142 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 614742 # Request fanout histogram -system.membus.reqLayer0.occupancy 978145707 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 613142 # Request fanout histogram +system.membus.reqLayer0.occupancy 975944720 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1654146686 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1649749525 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 627fd964a..24851d5c1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.043722 # Number of seconds simulated -sim_ticks 1043722398500 # Number of ticks simulated -final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.043724 # Number of seconds simulated +sim_ticks 1043723537500 # Number of ticks simulated +final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 921530 # Simulator instruction rate (inst/s) -host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504334297 # Simulator tick rate (ticks/s) -host_mem_usage 320916 # Number of bytes of host memory used -host_seconds 693.81 # Real time elapsed on the host +host_inst_rate 832063 # Simulator instruction rate (inst/s) +host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1358287943 # Simulator tick rate (ticks/s) +host_mem_usage 323064 # Number of bytes of host memory used +host_seconds 768.41 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 290359 # Nu system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087444797 # number of cpu cycles simulated +system.cpu.numCycles 2087447075 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257579 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy @@ -490,14 +490,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) @@ -528,14 +528,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,14 +564,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses @@ -590,15 +590,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution @@ -614,14 +620,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 257579 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks) |