diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/long/se/40.perlbmk/ref | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 322 | ||||
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1162 |
2 files changed, 742 insertions, 742 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 95e13097c..0912a812f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.646278 # Number of seconds simulated -sim_ticks 646278131000 # Number of ticks simulated -final_tick 646278131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 646278143000 # Number of ticks simulated +final_tick 646278143000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212773 # Simulator instruction rate (inst/s) -host_op_rate 212773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75429257 # Simulator tick rate (ticks/s) -host_mem_usage 229040 # Number of bytes of host memory used -host_seconds 8568.00 # Real time elapsed on the host +host_inst_rate 208687 # Simulator instruction rate (inst/s) +host_op_rate 208687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73980757 # Simulator tick rate (ticks/s) +host_mem_usage 229204 # Number of bytes of host memory used +host_seconds 8735.76 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 191680 # Number of bytes read from this memory @@ -24,16 +24,16 @@ system.physmem.num_reads::total 1479012 # Nu system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 296591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146167855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146464445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146167852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146464443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 296591 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 296591 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 6624813 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 6624813 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 6624813 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 296591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146167855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153089259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146167852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153089256 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1292556263 # number of cpu cycles simulated +system.cpu.numCycles 1292556287 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 394747270 # Number of BP lookups @@ -78,22 +78,22 @@ system.cpu.BPredUnit.BTBHits 262010178 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 57787448 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 7273 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421195056 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 421195062 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 3322341707 # Number of instructions fetch has processed system.cpu.fetch.Branches 394747270 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 319797626 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 638354680 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162914777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 98034183 # Number of cycles fetch has spent blocked +system.cpu.fetch.SquashCycles 162914776 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 98034186 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9273 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 9284 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 401438115 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 8412038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 1292428872 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.570619 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.140035 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 654074173 50.61% 50.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 654074192 50.61% 50.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 60911661 4.71% 55.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 43750931 3.39% 58.71% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 72637907 5.62% 64.33% # Number of instructions fetched each cycle (Total) @@ -105,65 +105,65 @@ system.cpu.fetch.rateDist::8 240462043 18.61% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1292428872 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.305400 # Number of branch fetches per cycle system.cpu.fetch.rate 2.570365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 452871359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80658875 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 614115226 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9960098 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134823295 # Number of cycles decode is squashing +system.cpu.decode.IdleCycles 452871377 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80658879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 614115225 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9960097 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134823294 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 34649231 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12312 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3231646724 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3231646719 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 46688 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134823295 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 482927881 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33597057 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 134823294 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 482927898 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33597059 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 26321 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 592678256 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48376043 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3142025534 # Number of instructions processed by rename +system.cpu.rename.RunCycles 592678255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48376045 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3142025529 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 359 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 11387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42577596 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2088048295 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3654580538 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3537192552 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 42577598 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2088048291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3654580534 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3537192548 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 117387986 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 703079225 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 703079221 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4247 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 139 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 143016933 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 739120184 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 143016934 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 739120183 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 360450433 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 67842482 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 9359459 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2647443518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2647443516 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 119 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2196739038 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2196739037 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17945817 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 824288888 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 711675230 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 824288886 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 711675229 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1292428853 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1292428872 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.699698 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.805222 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470829214 36.43% 36.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470829232 36.43% 36.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 219635474 16.99% 53.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252835920 19.56% 72.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120249082 9.30% 82.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106312850 8.23% 90.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 252835921 19.56% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120249084 9.30% 82.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106312849 8.23% 90.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 78591497 6.08% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21017975 1.63% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17286985 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21017973 1.63% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17286986 1.34% 99.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 5669856 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1292428853 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1292428872 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 1140834 3.16% 3.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available @@ -199,7 +199,7 @@ system.cpu.iq.fu_full::MemWrite 10866173 30.12% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1257954368 57.26% 57.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1257954367 57.26% 57.26% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 29223285 1.33% 58.60% # Type of FU issued @@ -232,21 +232,21 @@ system.cpu.iq.FU_type_0::MemRead 590393009 26.88% 86.18% # Ty system.cpu.iq.FU_type_0::MemWrite 303689578 13.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2196739038 # Type of FU issued +system.cpu.iq.FU_type_0::total 2196739037 # Type of FU issued system.cpu.iq.rate 1.699531 # Inst issue rate system.cpu.iq.fu_busy_cnt 36075558 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5585448848 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3387972541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 5585448865 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3387972537 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 2024033733 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 154479456 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 83833082 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 75371142 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2153745376 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2153745375 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 79066468 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69378492 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 228050158 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 228050157 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2255425 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 75959 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 149655537 # Number of stores squashed @@ -255,12 +255,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 4423 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134823295 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4267154 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 134823294 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4267155 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 460832 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3006059050 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2702145 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 739120184 # Number of dispatched load instructions +system.cpu.iew.iewDispatchedInsts 3006059047 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2702146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 739120183 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 360450433 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 119 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 451591 # Number of times the IQ has become full, causing a stall @@ -271,41 +271,41 @@ system.cpu.iew.predictedNotTakenIncorrect 31610 # N system.cpu.iew.branchMispredicts 27624768 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 2105923301 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 528979869 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90815737 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 90815736 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358615413 # number of nop insts executed +system.cpu.iew.exec_nop 358615412 # number of nop insts executed system.cpu.iew.exec_refs 821261997 # number of memory reference insts executed system.cpu.iew.exec_branches 282350798 # Number of branches executed system.cpu.iew.exec_stores 292282128 # Number of stores executed system.cpu.iew.exec_rate 1.629270 # Inst execution rate system.cpu.iew.wb_sent 2102194150 # cumulative count of insts sent to commit system.cpu.iew.wb_count 2099404875 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185212781 # num instructions producing a value -system.cpu.iew.wb_consumers 1754721969 # num instructions consuming a value +system.cpu.iew.wb_producers 1185212780 # num instructions producing a value +system.cpu.iew.wb_consumers 1754721967 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.624227 # insts written-back per cycle system.cpu.iew.wb_fanout 0.675442 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 980398498 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 980398495 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 27578641 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1157605558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1157605578 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.735468 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.494432 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 541345046 46.76% 46.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227581474 19.66% 66.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119272187 10.30% 76.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56742029 4.90% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 51019589 4.41% 86.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24162951 2.09% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18255182 1.58% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 541345066 46.76% 46.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227581476 19.66% 66.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119272186 10.30% 76.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56742028 4.90% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 51019590 4.41% 86.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24162950 2.09% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18255180 1.58% 89.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 15605334 1.35% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103621766 8.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103621768 8.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1157605558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1157605578 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,12 +316,12 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103621766 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103621768 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4037733484 # The number of ROB reads -system.cpu.rob.rob_writes 6113598013 # The number of ROB writes -system.cpu.timesIdled 3574 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 127410 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4037733499 # The number of ROB reads +system.cpu.rob.rob_writes 6113598006 # The number of ROB writes +system.cpu.timesIdled 3575 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 127415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated @@ -356,12 +356,12 @@ system.cpu.icache.demand_misses::cpu.inst 11347 # n system.cpu.icache.demand_misses::total 11347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11347 # number of overall misses system.cpu.icache.overall_misses::total 11347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204563500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204563500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204563500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204563500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204563500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204563500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 204562000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 204562000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 204562000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 204562000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 204562000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 204562000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 401438115 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 401438115 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 401438115 # number of demand (read+write) accesses @@ -374,12 +374,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.980964 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18027.980964 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18027.980964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18027.980964 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.848771 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18027.848771 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18027.848771 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18027.848771 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,14 +446,14 @@ system.cpu.dcache.demand_misses::cpu.data 2543931 # n system.cpu.dcache.demand_misses::total 2543931 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2543931 # number of overall misses system.cpu.dcache.overall_misses::total 2543931 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609230000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76609230000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362374985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30362374985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106971604985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106971604985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106971604985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106971604985 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609210500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76609210500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362476485 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30362476485 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106971686985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106971686985 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106971686985 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106971686985 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 458970336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 458970336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -472,14 +472,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003798 system.cpu.dcache.demand_miss_rate::total 0.003798 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003798 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003798 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.875316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.875316 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.193322 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.193322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42049.727365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42049.727365 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.865203 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.865203 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.358194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.358194 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42049.759598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42049.759598 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 174500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -506,14 +506,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1532162 system.cpu.dcache.demand_mshr_misses::total 1532162 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1532162 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1532162 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266374000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266374000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176553000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176553000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 53442927000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 53442927000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176578500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176578500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 53442927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 53442927500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses @@ -522,24 +522,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.940516 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.940516 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44360.928401 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44360.928401 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.923399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.923399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.284511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.284511 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480672 # number of replacements -system.cpu.l2cache.tagsinuse 32700.801266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32700.801233 # Cycle average of tags in use system.cpu.l2cache.total_refs 66336 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.043832 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3222.422706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 46.121130 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29432.257430 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 3222.422931 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 46.121134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29432.257169 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.098341 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001408 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.898201 # Average percentage of cache occupancy @@ -569,16 +569,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2995 # system.cpu.l2cache.overall_misses::cpu.data 1476017 # number of overall misses system.cpu.l2cache.overall_misses::total 1479012 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399950500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48506918500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813587500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2813587500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399927000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48506895000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813613000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2813613000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 106968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 51213538000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 51320506000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 51213540000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 51320508000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 106968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 51213538000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 51320506000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 51213540000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 51320508000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10134 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460549 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1470683 # number of ReadReq accesses(hits+misses) @@ -604,16 +604,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295540 system.cpu.l2cache.overall_miss_rate::cpu.data 0.963356 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.958968 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35715.525876 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.594752 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.498073 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.552099 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.552099 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.578075 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.481432 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.933527 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.933527 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34699.181616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34699.182968 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34699.181616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34699.182968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 107500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked @@ -636,16 +636,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995 system.cpu.l2cache.overall_mshr_misses::cpu.data 1476017 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1479012 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717529000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814894000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612258000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612258000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717505000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814870000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612284000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612284000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46427152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329789000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46427154000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329787000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46427152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329789000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46427154000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964817 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960206 # mshr miss rate for ReadReq accesses @@ -658,16 +658,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295540 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963356 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.958968 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32509.181970 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.755946 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.906338 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.071858 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.071858 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.738915 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.889342 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.460765 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.460765 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 639c0707a..6cef7cd16 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.735463 # Number of seconds simulated -sim_ticks 735462942500 # Number of ticks simulated -final_tick 735462942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.737495 # Number of seconds simulated +sim_ticks 737494828500 # Number of ticks simulated +final_tick 737494828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115593 # Simulator instruction rate (inst/s) -host_op_rate 157422 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61409842 # Simulator tick rate (ticks/s) -host_mem_usage 243732 # Number of bytes of host memory used -host_seconds 11976.30 # Real time elapsed on the host -sim_insts 1384378705 # Number of instructions simulated -sim_ops 1885333457 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 209152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94513152 # Number of bytes read from this memory -system.physmem.bytes_read::total 94722304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 209152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 209152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3268 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476768 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1480036 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 284381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 128508381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128792762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 284381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 284381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5751849 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5751849 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5751849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 284381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 128508381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134544612 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 117861 # Simulator instruction rate (inst/s) +host_op_rate 160511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62787760 # Simulator tick rate (ticks/s) +host_mem_usage 243784 # Number of bytes of host memory used +host_seconds 11745.84 # Real time elapsed on the host +sim_insts 1384378545 # Number of instructions simulated +sim_ops 1885333297 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 209536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94516480 # Number of bytes read from this memory +system.physmem.bytes_read::total 94726016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 209536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 209536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1480094 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 284119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128158838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128442956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 284119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 284119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5736089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5736089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5736089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 284119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128158838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134179045 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1470925886 # number of cpu cycles simulated +system.cpu.numCycles 1474989658 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 526944807 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 400998639 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 36103831 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 389912593 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 290078755 # Number of BTB hits +system.cpu.BPredUnit.lookups 524417855 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 399374260 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 35885746 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 373085909 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 286974367 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59371448 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2810327 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 451184041 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2630280787 # Number of instructions fetch has processed -system.cpu.fetch.Branches 526944807 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 349450203 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 714901139 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 225817309 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 101657894 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20337 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 420935290 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11687737 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1451892883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.541647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.159630 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 58521049 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2814397 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 448543327 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2629766387 # Number of instructions fetch has processed +system.cpu.fetch.Branches 524417855 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 345495416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 712413372 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 224871613 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 101150257 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2305 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27764 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 417868916 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11061583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1445533834 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166303 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 737052267 50.76% 50.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 55648987 3.83% 54.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113021811 7.78% 62.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71058557 4.89% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 83474414 5.75% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 55105836 3.80% 76.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35245314 2.43% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 35853884 2.47% 81.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 265431813 18.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 733184926 50.72% 50.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55708468 3.85% 54.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 112020823 7.75% 62.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 70937824 4.91% 67.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82697525 5.72% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53946539 3.73% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34097920 2.36% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36269848 2.51% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 266669961 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1451892883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.358240 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.788180 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 498609504 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80967892 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 677644967 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10558484 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 184112036 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 82169847 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15539 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3562988403 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 34450 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 184112036 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 537763866 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 32181538 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 530906 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 647549947 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49754590 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3439334544 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 1445533834 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355540 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.782905 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 495848393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80424598 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 675057973 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10827570 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 183375300 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 81502199 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 23236 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3555990026 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 53741 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 183375300 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 535002639 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31838463 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 561864 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 645033334 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49722234 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3433849661 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4507727 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40704108 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1637 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3357877059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16273276362 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15612337004 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 660939358 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153074 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1364723985 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45755 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138448530 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1057693537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 579697033 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32301976 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40224751 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3204253855 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55204 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2728539607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 26296633 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1318520975 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3049786617 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 32197 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1451892883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.879298 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.913242 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 4442600 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40377333 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1619 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3343633011 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16242490520 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15601606149 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 640884371 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993152818 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1350480193 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 55128 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 50419 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136573484 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1056851261 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 578467186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33770671 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40675012 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3200649154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 58384 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2726502260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 25388775 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1314914344 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3030342592 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 35409 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1445533834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.886156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.918040 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 529391229 36.46% 36.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201881649 13.90% 50.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217086646 14.95% 65.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 180698536 12.45% 77.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 155303824 10.70% 88.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 101627119 7.00% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47687061 3.28% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10818751 0.75% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7398068 0.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 525278081 36.34% 36.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201262430 13.92% 50.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215918123 14.94% 65.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180162301 12.46% 77.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 154926049 10.72% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101550700 7.03% 95.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47554041 3.29% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10922133 0.76% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7959976 0.55% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1451892883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1445533834 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1769730 1.85% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23897 0.03% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57017691 59.74% 61.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36624161 38.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1492509 1.56% 1.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23896 0.02% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56884483 59.48% 61.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37239793 38.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1267852875 46.47% 46.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11249841 0.41% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876502 0.25% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5509242 0.20% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 10 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23422716 0.86% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 900241539 32.99% 81.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 512011592 18.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1265251443 46.41% 46.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11240550 0.41% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876520 0.25% 47.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5507594 0.20% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 50 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23397304 0.86% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 900321510 33.02% 81.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 512531999 18.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2728539607 # Type of FU issued -system.cpu.iq.rate 1.854981 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95435479 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034977 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6896111029 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4417455828 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2500265065 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 134593180 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 105438972 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60061785 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2754719800 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 69255286 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 70868561 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2726502260 # Type of FU issued +system.cpu.iq.rate 1.848489 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95640681 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6886689526 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4415187143 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2498660773 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 132878284 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 100500200 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59720745 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2753616267 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68526674 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 71560936 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 426304733 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264948 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1116073 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 302700113 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 425462489 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 295662 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1252623 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 301470298 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 184112036 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17217570 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2222077 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3204383976 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3801477 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1057693537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 579697033 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 44065 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2220604 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1116073 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 37419443 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9018722 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 46438165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2627591050 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 846492275 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100948557 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 183375300 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17460814 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1976242 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3200787719 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6982578 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1056851261 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 578467186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 47271 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1974574 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 647 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1252623 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36804150 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9241017 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46045167 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2625801566 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 846122172 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 100700694 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 74917 # number of nop insts executed -system.cpu.iew.exec_refs 1329282286 # number of memory reference insts executed -system.cpu.iew.exec_branches 361424797 # Number of branches executed -system.cpu.iew.exec_stores 482790011 # Number of stores executed -system.cpu.iew.exec_rate 1.786352 # Inst execution rate -system.cpu.iew.wb_sent 2588656133 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2560326850 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1477151291 # num instructions producing a value -system.cpu.iew.wb_consumers 2761912490 # num instructions consuming a value +system.cpu.iew.exec_nop 80181 # number of nop insts executed +system.cpu.iew.exec_refs 1330053445 # number of memory reference insts executed +system.cpu.iew.exec_branches 359055744 # Number of branches executed +system.cpu.iew.exec_stores 483931273 # Number of stores executed +system.cpu.iew.exec_rate 1.780217 # Inst execution rate +system.cpu.iew.wb_sent 2586917302 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2558381518 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1475385900 # num instructions producing a value +system.cpu.iew.wb_consumers 2766219416 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.740623 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534829 # average fanout of values written-back +system.cpu.iew.wb_rate 1.734508 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533358 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1319039983 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23007 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41626374 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1267780849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.487122 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.205349 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 1315443833 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22975 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41404056 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1262158536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.493746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.206193 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 586908423 46.29% 46.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 318188211 25.10% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 101915381 8.04% 79.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79184752 6.25% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52930899 4.18% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24002778 1.89% 91.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17056118 1.35% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9057246 0.71% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78537041 6.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 581725846 46.09% 46.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 316852279 25.10% 71.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 102044776 8.08% 79.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79824424 6.32% 85.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 53115957 4.21% 89.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24396464 1.93% 91.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17091653 1.35% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8923952 0.71% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78183185 6.19% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1267780849 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384389721 # Number of instructions committed -system.cpu.commit.committedOps 1885344473 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1262158536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384389561 # Number of instructions committed +system.cpu.commit.committedOps 1885344313 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385724 # Number of memory references committed -system.cpu.commit.loads 631388804 # Number of loads committed +system.cpu.commit.refs 908385660 # Number of memory references committed +system.cpu.commit.loads 631388772 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350167 # Number of branches committed +system.cpu.commit.branches 291350135 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705359 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705231 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78537041 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78183185 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4393609919 # The number of ROB reads -system.cpu.rob.rob_writes 6592898385 # The number of ROB writes -system.cpu.timesIdled 1319009 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19033003 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384378705 # Number of Instructions Simulated -system.cpu.committedOps 1885333457 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384378705 # Number of Instructions Simulated -system.cpu.cpi 1.062517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.062517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941161 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.941161 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12954963873 # number of integer regfile reads -system.cpu.int_regfile_writes 2433899431 # number of integer regfile writes -system.cpu.fp_regfile_reads 71453474 # number of floating regfile reads -system.cpu.fp_regfile_writes 51512029 # number of floating regfile writes -system.cpu.misc_regfile_reads 4110345957 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776148 # number of misc regfile writes -system.cpu.icache.replacements 27727 # number of replacements -system.cpu.icache.tagsinuse 1657.357291 # Cycle average of tags in use -system.cpu.icache.total_refs 420895339 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 29422 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14305.463225 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4384745152 # The number of ROB reads +system.cpu.rob.rob_writes 6584968170 # The number of ROB writes +system.cpu.timesIdled 1343543 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29455824 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384378545 # Number of Instructions Simulated +system.cpu.committedOps 1885333297 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384378545 # Number of Instructions Simulated +system.cpu.cpi 1.065453 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.065453 # CPI: Total CPI of All Threads +system.cpu.ipc 0.938568 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.938568 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12950426831 # number of integer regfile reads +system.cpu.int_regfile_writes 2427369394 # number of integer regfile writes +system.cpu.fp_regfile_reads 71525918 # number of floating regfile reads +system.cpu.fp_regfile_writes 50683175 # number of floating regfile writes +system.cpu.misc_regfile_reads 4109052133 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776084 # number of misc regfile writes +system.cpu.icache.replacements 27555 # number of replacements +system.cpu.icache.tagsinuse 1659.051734 # Cycle average of tags in use +system.cpu.icache.total_refs 417829104 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 29252 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14283.779024 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1657.357291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.809256 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.809256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 420900012 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420900012 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420900012 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420900012 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420900012 # number of overall hits -system.cpu.icache.overall_hits::total 420900012 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35278 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35278 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35278 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35278 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35278 # number of overall misses -system.cpu.icache.overall_misses::total 35278 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 347510000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 347510000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 347510000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 347510000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 347510000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 347510000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420935290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420935290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420935290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420935290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420935290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420935290 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1659.051734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.810084 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.810084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 417833790 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 417833790 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 417833790 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 417833790 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 417833790 # number of overall hits +system.cpu.icache.overall_hits::total 417833790 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35126 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35126 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35126 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35126 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35126 # number of overall misses +system.cpu.icache.overall_misses::total 35126 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 348458500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 348458500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 348458500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 348458500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 348458500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 348458500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 417868916 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 417868916 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 417868916 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 417868916 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 417868916 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 417868916 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9850.615114 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9850.615114 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9850.615114 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9850.615114 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9920.244264 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 9920.244264 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 9920.244264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 9920.244264 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,110 +399,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 933 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 933 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 933 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 933 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 933 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 933 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34345 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 34345 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 34345 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 34345 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 34345 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 34345 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 217293500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 217293500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 217293500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 217293500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 217293500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 217293500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 940 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 940 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 940 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 940 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 940 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 940 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34186 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 34186 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 34186 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 34186 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 34186 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 34186 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218551000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 218551000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218551000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 218551000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218551000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 218551000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6326.787014 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6326.787014 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6392.997133 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6392.997133 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532802 # number of replacements -system.cpu.dcache.tagsinuse 4094.906416 # Cycle average of tags in use -system.cpu.dcache.total_refs 1033702432 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536898 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 672.590134 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1533020 # number of replacements +system.cpu.dcache.tagsinuse 4094.909429 # Cycle average of tags in use +system.cpu.dcache.total_refs 1033013851 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537116 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 672.046775 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.906416 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 757546654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 757546654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276115180 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276115180 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11970 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11970 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11608 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11608 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1033661834 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1033661834 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1033661834 # number of overall hits -system.cpu.dcache.overall_hits::total 1033661834 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2867388 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2867388 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 820498 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 820498 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3687886 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3687886 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3687886 # number of overall misses -system.cpu.dcache.overall_misses::total 3687886 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 99520769500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 99520769500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963338500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33963338500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 216500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133484108000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133484108000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133484108000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133484108000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 760414042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 760414042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4094.909429 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999734 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999734 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 756858216 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 756858216 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276115103 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276115103 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11921 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11921 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11576 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11576 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1032973319 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1032973319 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1032973319 # number of overall hits +system.cpu.dcache.overall_hits::total 1032973319 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2483728 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2483728 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 820575 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 820575 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3304303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3304303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3304303 # number of overall misses +system.cpu.dcache.overall_misses::total 3304303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 90046240500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 90046240500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963890000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33963890000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124010130500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124010130500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124010130500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124010130500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 759341944 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 759341944 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11976 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11976 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11608 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11608 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1037349720 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1037349720 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1037349720 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1037349720 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003771 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003771 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11576 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11576 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1036277622 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1036277622 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1036277622 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1036277622 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003271 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003271 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000501 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000501 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003555 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003555 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003555 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003555 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34707.814045 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34707.814045 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41393.566468 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41393.566468 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 36083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36195.291286 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36195.291286 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000335 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000335 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003189 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003189 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003189 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003189 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36254.469290 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36254.469290 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41390.354325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41390.354325 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37529.890721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37529.890721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,142 +511,142 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108638 # number of writebacks -system.cpu.dcache.writebacks::total 108638 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1403027 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1403027 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2146065 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2146065 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2146065 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2146065 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464361 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464361 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77460 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77460 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541821 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541821 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541821 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541821 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50337065001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50337065001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525124500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525124500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52862189501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52862189501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52862189501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52862189501 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001926 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001926 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 108316 # number of writebacks +system.cpu.dcache.writebacks::total 108316 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1019154 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1019154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743098 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743098 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1762252 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1762252 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1762252 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1762252 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464574 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464574 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77477 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77477 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1542051 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1542051 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1542051 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1542051 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50338229502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50338229502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52864087002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52864087002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52864087002 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52864087002 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001929 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001486 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001486 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34374.764830 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34374.764830 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32599.076943 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32599.076943 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34370.560656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34370.560656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32601.384927 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32601.384927 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480261 # number of replacements -system.cpu.l2cache.tagsinuse 32698.232813 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88469 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.058472 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480259 # number of replacements +system.cpu.l2cache.tagsinuse 32698.440647 # Cycle average of tags in use +system.cpu.l2cache.total_refs 88180 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513003 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.058281 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3127.449947 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 61.048059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29509.734807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.095442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001863 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.900566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997871 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 53654 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 79798 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108638 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108638 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 3112.320696 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 61.394609 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29524.725342 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.094980 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001874 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.901023 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997877 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25967 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53813 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999392 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999392 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.944921 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.944921 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32293.219304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.167012 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.348237 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.547661 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.547661 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.381199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.381199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |