diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/se/40.perlbmk/ref | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
6 files changed, 2341 insertions, 2200 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 3373b2092..896e43907 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.559967 # Number of seconds simulated -sim_ticks 559966999500 # Number of ticks simulated -final_tick 559966999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.559962 # Number of seconds simulated +sim_ticks 559961514500 # Number of ticks simulated +final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 393705 # Simulator instruction rate (inst/s) -host_op_rate 393705 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237364888 # Simulator tick rate (ticks/s) -host_mem_usage 245892 # Number of bytes of host memory used -host_seconds 2359.10 # Real time elapsed on the host +host_inst_rate 343254 # Simulator instruction rate (inst/s) +host_op_rate 343254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206945650 # Simulator tick rate (ticks/s) +host_mem_usage 305268 # Number of bytes of host memory used +host_seconds 2705.84 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,33 +23,33 @@ system.physmem.num_reads::cpu.inst 291519 # Nu system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7621363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33318421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40939784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33318747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17280 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 270 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 17935 # Per bank write bursts system.physmem.perBankRdBursts::1 18289 # Per bank write bursts system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18248 # Per bank write bursts -system.physmem.perBankRdBursts::4 18163 # Per bank write bursts -system.physmem.perBankRdBursts::5 18239 # Per bank write bursts +system.physmem.perBankRdBursts::3 18250 # Per bank write bursts +system.physmem.perBankRdBursts::4 18167 # Per bank write bursts +system.physmem.perBankRdBursts::5 18240 # Per bank write bursts system.physmem.perBankRdBursts::6 18320 # Per bank write bursts system.physmem.perBankRdBursts::7 18299 # Per bank write bursts system.physmem.perBankRdBursts::8 18230 # Per bank write bursts @@ -59,7 +59,7 @@ system.physmem.perBankRdBursts::11 18391 # Pe system.physmem.perBankRdBursts::12 18259 # Per bank write bursts system.physmem.perBankRdBursts::13 18042 # Per bank write bursts system.physmem.perBankRdBursts::14 17977 # Per bank write bursts -system.physmem.perBankRdBursts::15 18106 # Per bank write bursts +system.physmem.perBankRdBursts::15 18101 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 559966923500 # Total gap between requests +system.physmem.totGap 559961438500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.912664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.833166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 269.609760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39535 37.79% 37.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43904 41.96% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8672 8.29% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 695 0.66% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 728 0.70% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 763 0.73% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1332 1.27% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 808 0.77% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8193 7.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.196437 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.192949 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.958027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes @@ -221,12 +221,12 @@ system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Wr system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2990654250 # Total ticks spent queuing -system.physmem.totMemAccLat 8451573000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10268.38 # Average queueing delay per DRAM burst +system.physmem.totQLat 2985206750 # Total ticks spent queuing +system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29018.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s @@ -237,35 +237,40 @@ system.physmem.busUtilRead 0.26 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 202814 # Number of row buffer hits during reads -system.physmem.writeRowHits 50461 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 1563271.35 # Average gap between requests -system.physmem.pageHitRate 70.76 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275670988500 # Time in different power states -system.physmem.memoryStateTime::REF 18698420000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 265594606500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 393989400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 396952920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 214974375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 216591375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136974800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1134400800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215550720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 108415975050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 108760602465 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 240876668250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 240574363500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 387829129875 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 387872571300 # Total energy per rank (pJ) -system.physmem.averagePower::0 692.596540 # Core power per rank (mW) -system.physmem.averagePower::1 692.674119 # Core power per rank (mW) +system.physmem.readRowHits 202789 # Number of row buffer hits during reads +system.physmem.writeRowHits 50437 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgGap 1563256.04 # Average gap between requests +system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.597962 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states +system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.677886 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 125749069 # Number of BP lookups system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect @@ -309,24 +314,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1119933999 # number of cpu cycles simulated +system.cpu.numCycles 1119923029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.205800 # CPI: cycles per instruction -system.cpu.ipc 0.829325 # IPC: instructions per cycle -system.cpu.tickCycles 1060170405 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59763594 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.205788 # CPI: cycles per instruction +system.cpu.ipc 0.829333 # IPC: instructions per cycle +system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.890193 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890165 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -354,14 +359,14 @@ system.cpu.dcache.demand_misses::cpu.inst 849082 # n system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32458547250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32458547250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32445902750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) @@ -378,14 +383,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32892.515616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65829.890706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,14 +417,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26366993750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses @@ -428,22 +433,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10606 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.447542 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447542 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id @@ -467,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst 12350 # n system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses system.cpu.icache.overall_misses::total 12350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333735500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333735500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333735500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333735500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses @@ -485,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27023.117409 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27038.380567 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,41 +510,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12350 system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307779500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 307779500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307968000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 307968000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258740 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.453126 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32601.451844 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2865.906217 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.517639 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2657 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses @@ -562,14 +567,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 291520 # system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 291520 # number of overall misses system.cpu.l2cache.overall_misses::total 291520 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20867174750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20867174750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20861762750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) @@ -588,14 +593,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367627 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71580.593956 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,14 +619,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 291520 system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 291520 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17195446750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17190059750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses @@ -630,14 +635,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution @@ -666,7 +671,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # La system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222199250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution @@ -688,9 +693,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 975509000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2745284750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index ce136ba27..8cb1b2d37 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278139 # Number of seconds simulated -sim_ticks 278139424500 # Number of ticks simulated -final_tick 278139424500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278180 # Number of seconds simulated +sim_ticks 278180234500 # Number of ticks simulated +final_tick 278180234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197644 # Simulator instruction rate (inst/s) -host_op_rate 197644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65258345 # Simulator tick rate (ticks/s) -host_mem_usage 248388 # Number of bytes of host memory used -host_seconds 4262.13 # Real time elapsed on the host +host_inst_rate 185742 # Simulator instruction rate (inst/s) +host_op_rate 185742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61337566 # Simulator tick rate (ticks/s) +host_mem_usage 305284 # Number of bytes of host memory used +host_seconds 4535.23 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 175680 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18653120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18652864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 175680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 175680 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2745 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291451 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 632546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66431374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67063920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 632546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 632546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15343787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15343787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15343787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 632546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66431374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82407706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291455 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 631533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66421628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67053161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15341536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15341536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15341536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66421628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82394697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291451 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291451 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18634176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18944 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18653120 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18633536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652864 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 296 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17915 # Per bank write bursts -system.physmem.perBankRdBursts::1 18264 # Per bank write bursts -system.physmem.perBankRdBursts::2 18305 # Per bank write bursts -system.physmem.perBankRdBursts::3 18245 # Per bank write bursts -system.physmem.perBankRdBursts::4 18154 # Per bank write bursts -system.physmem.perBankRdBursts::5 18231 # Per bank write bursts -system.physmem.perBankRdBursts::6 18323 # Per bank write bursts -system.physmem.perBankRdBursts::7 18314 # Per bank write bursts -system.physmem.perBankRdBursts::8 18231 # Per bank write bursts -system.physmem.perBankRdBursts::9 18221 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18383 # Per bank write bursts -system.physmem.perBankRdBursts::12 18244 # Per bank write bursts -system.physmem.perBankRdBursts::13 18043 # Per bank write bursts -system.physmem.perBankRdBursts::14 17967 # Per bank write bursts -system.physmem.perBankRdBursts::15 18104 # Per bank write bursts +system.physmem.perBankRdBursts::0 17916 # Per bank write bursts +system.physmem.perBankRdBursts::1 18271 # Per bank write bursts +system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::3 18248 # Per bank write bursts +system.physmem.perBankRdBursts::4 18157 # Per bank write bursts +system.physmem.perBankRdBursts::5 18220 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18312 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::9 18223 # Per bank write bursts +system.physmem.perBankRdBursts::10 18210 # Per bank write bursts +system.physmem.perBankRdBursts::11 18385 # Per bank write bursts +system.physmem.perBankRdBursts::12 18240 # Per bank write bursts +system.physmem.perBankRdBursts::13 18040 # Per bank write bursts +system.physmem.perBankRdBursts::14 17965 # Per bank write bursts +system.physmem.perBankRdBursts::15 18111 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::9 4187 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278139341500 # Total gap between requests +system.physmem.totGap 278180151500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291455 # Read request sizes (log2) +system.physmem.readPktSize::6 291451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 211494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 211637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,137 +193,118 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.952415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.081554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 279.010577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36030 35.87% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42282 42.09% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10217 10.17% 88.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 414 0.41% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 384 0.38% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 317 0.32% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 757 0.75% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1270 1.26% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8780 8.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 100542 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.760100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.180809 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.034024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36066 35.87% 35.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42234 42.01% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10234 10.18% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 483 0.48% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 471 0.47% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 384 0.38% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 767 0.76% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1163 1.16% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8740 8.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100542 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.301854 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.144651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 769.722850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.840049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.159268 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 778.757650 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.458498 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.856350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3077 76.07% 76.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 963 23.81% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.480346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.459004 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3075 76.02% 76.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 23.86% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 3340616250 # Total ticks spent queuing -system.physmem.totMemAccLat 8799847500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11473.51 # Average queueing delay per DRAM burst +system.physmem.totQLat 3369536750 # Total ticks spent queuing +system.physmem.totMemAccLat 8828580500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11573.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30223.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 67.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30323.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing -system.physmem.readRowHits 206977 # Number of row buffer hits during reads -system.physmem.writeRowHits 50379 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.55 # Row buffer hit rate for writes -system.physmem.avgGap 776626.17 # Average gap between requests -system.physmem.pageHitRate 71.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 74109656250 # Time in different power states -system.physmem.memoryStateTime::REF 9287460000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 194735825750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 377969760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 381175200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 206233500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 207982500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136124600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1133831400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215524800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 18166271760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 18166271760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 79684218180 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79920417060 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 96981320250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 96774128250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 196768576530 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 196799330970 # Total energy per rank (pJ) -system.physmem.averagePower::0 707.462354 # Core power per rank (mW) -system.physmem.averagePower::1 707.572929 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 224829 # Transaction distribution -system.membus.trans_dist::ReadResp 224829 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649593 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649593 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920832 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358138 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358138 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358138 # Request fanout histogram -system.membus.reqLayer0.occupancy 956225500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2708510750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 192497192 # Number of BP lookups -system.cpu.branchPred.condPredicted 125506208 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11891081 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155386216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126898467 # Number of BTB hits +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 206912 # Number of row buffer hits during reads +system.physmem.writeRowHits 50353 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.51 # Row buffer hit rate for writes +system.physmem.avgGap 776748.79 # Average gap between requests +system.physmem.pageHitRate 71.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378604800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206580000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136756400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79832621385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96879153000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 196819477185 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.526603 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 160651755000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108238852500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 381470040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 208143375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79968075615 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 96760333500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 196836972210 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.589494 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 160452636750 # Time in different power states +system.physmem_1.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108437970750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 192516083 # Number of BP lookups +system.cpu.branchPred.condPredicted 125602202 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11889251 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155393318 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126938973 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.666489 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 29014222 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.688823 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28938957 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244546246 # DTB read hits -system.cpu.dtb.read_misses 309763 # DTB read misses +system.cpu.dtb.read_hits 244535558 # DTB read hits +system.cpu.dtb.read_misses 309848 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244856009 # DTB read accesses -system.cpu.dtb.write_hits 135693142 # DTB write hits -system.cpu.dtb.write_misses 31331 # DTB write misses +system.cpu.dtb.read_accesses 244845406 # DTB read accesses +system.cpu.dtb.write_hits 135688740 # DTB write hits +system.cpu.dtb.write_misses 31438 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135724473 # DTB write accesses -system.cpu.dtb.data_hits 380239388 # DTB hits -system.cpu.dtb.data_misses 341094 # DTB misses +system.cpu.dtb.write_accesses 135720178 # DTB write accesses +system.cpu.dtb.data_hits 380224298 # DTB hits +system.cpu.dtb.data_misses 341286 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380580482 # DTB accesses -system.cpu.itb.fetch_hits 197059053 # ITB hits -system.cpu.itb.fetch_misses 278 # ITB misses +system.cpu.dtb.data_accesses 380565584 # DTB accesses +system.cpu.itb.fetch_hits 196974389 # ITB hits +system.cpu.itb.fetch_misses 282 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 197059331 # ITB accesses +system.cpu.itb.fetch_accesses 196974671 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -337,99 +318,99 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556278850 # number of cpu cycles simulated +system.cpu.numCycles 556360470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202390061 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648021471 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192497192 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155912689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341534414 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24250324 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 202471372 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648161036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192516083 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155877930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341537101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24247434 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6722 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 6713 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 197059053 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6903560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556056617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 196974389 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6735628 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556139161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176192 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236849124 42.59% 42.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30318987 5.45% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22124224 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36449383 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67846603 12.20% 70.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21659642 3.90% 74.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19297725 3.47% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3452517 0.62% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118058412 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236974879 42.61% 42.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30241040 5.44% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22122460 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36446378 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67887841 12.21% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21615986 3.89% 74.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19300231 3.47% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3499506 0.63% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118050840 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556056617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346044 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962582 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168903349 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 88724490 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273566111 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12744273 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12118394 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15366279 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1583865955 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 556139161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346028 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962398 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168673381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88906441 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273702922 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12739464 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12116953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15366288 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7026 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1584564231 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12118394 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176795678 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61743317 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13930 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278397423 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26987875 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1537838720 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2373790 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17873362 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6849052 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1027019192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1768562187 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728780266 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39781920 # Number of floating rename lookups +system.cpu.rename.SquashCycles 12116953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176662049 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61884123 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13864 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278433046 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27029126 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538057639 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6904 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2373775 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17934465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6832008 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1026949046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1768413823 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728631636 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39782186 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 388052034 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9574141 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372265088 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175432833 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40642740 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11166161 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304456084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 387981888 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 99 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9559876 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372392006 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175420299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40717360 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11158065 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304772774 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015678873 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8790246 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462050270 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427374200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1015651643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8789932 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462366805 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427709940 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556056617 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.903970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 556139161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.901646 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197073815 35.44% 35.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93100278 16.74% 52.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91275539 16.41% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59807751 10.76% 79.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56767795 10.21% 89.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29817356 5.36% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17038926 3.06% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7188508 1.29% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3986649 0.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 196811929 35.39% 35.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93156725 16.75% 52.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91633615 16.48% 68.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59891442 10.77% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56837976 10.22% 89.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29662833 5.33% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17038989 3.06% 98.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7191857 1.29% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3913795 0.70% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556056617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556139161 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2463855 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464081 10.47% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available @@ -458,118 +439,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15566694 66.15% 76.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5500530 23.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15568992 66.16% 76.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5500305 23.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579447507 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579437623 57.05% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181923 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181925 1.30% 58.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276926005 27.27% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138947884 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276912765 27.26% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138943776 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015678873 # Type of FU issued -system.cpu.iq.rate 1.825845 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23531079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548927232 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1725239923 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940039301 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808456 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41311588 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425282 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002846638 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36362038 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50462240 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015651643 # Type of FU issued +system.cpu.iq.rate 1.825528 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23533378 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023171 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548957351 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1725871307 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940019268 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808406 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41313833 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425264 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002821720 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36362025 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50456367 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 134754491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1146539 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45582 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77131633 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 134881409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1145791 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45978 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77119099 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2126 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4422 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2647 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4470 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12118394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60795579 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 183960 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1478937167 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16099 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372265088 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175432833 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 12116953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60932529 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 189663 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479247252 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16168 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372392006 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175420299 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26971 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 168750 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45582 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11885427 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16182 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11901609 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976191371 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244856188 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39487502 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 26629 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 174749 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45978 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11882583 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16645 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11899228 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976172370 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244845576 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39479273 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174481002 # number of nop insts executed -system.cpu.iew.exec_refs 380581036 # number of memory reference insts executed -system.cpu.iew.exec_branches 129104728 # Number of branches executed -system.cpu.iew.exec_stores 135724848 # Number of stores executed -system.cpu.iew.exec_rate 1.754860 # Inst execution rate -system.cpu.iew.wb_sent 974983742 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974464583 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556223277 # num instructions producing a value -system.cpu.iew.wb_consumers 832224680 # num instructions consuming a value +system.cpu.iew.exec_nop 174474397 # number of nop insts executed +system.cpu.iew.exec_refs 380566182 # number of memory reference insts executed +system.cpu.iew.exec_branches 129102826 # Number of branches executed +system.cpu.iew.exec_stores 135720606 # Number of stores executed +system.cpu.iew.exec_rate 1.754568 # Inst execution rate +system.cpu.iew.wb_sent 974964146 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974444532 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556292557 # num instructions producing a value +system.cpu.iew.wb_consumers 832443785 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751756 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668357 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751463 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668264 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543106202 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543416365 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11884314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483349873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.921150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.600543 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11882488 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483294798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.921369 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.600805 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205286712 42.47% 42.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102225167 21.15% 63.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51816081 10.72% 74.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25666887 5.31% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21541208 4.46% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9141976 1.89% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10432211 2.16% 88.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6655388 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50584243 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205311965 42.48% 42.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102147195 21.14% 63.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51748026 10.71% 74.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25735966 5.33% 79.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21537447 4.46% 84.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9139527 1.89% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10425967 2.16% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6656382 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50592323 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483349873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 483294798 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -615,238 +596,330 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50584243 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50592323 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1901838322 # The number of ROB reads -system.cpu.rob.rob_writes 3016095658 # The number of ROB writes -system.cpu.timesIdled 3295 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 222233 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1902085330 # The number of ROB reads +system.cpu.rob.rob_writes 3016853590 # The number of ROB writes +system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 221309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660364 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514316 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514316 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237260763 # number of integer regfile reads -system.cpu.int_regfile_writes 705832198 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691509 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411335 # number of floating regfile writes +system.cpu.cpi 0.660461 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660461 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514094 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237238749 # number of integer regfile reads +system.cpu.int_regfile_writes 705818584 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691517 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411333 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 718899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68835 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 408320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56270144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879222 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879222 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879222 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531099000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10065500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1207435500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4667 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.176031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 197050731 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6380 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30885.694514 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 777239 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.040110 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289873961 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781335 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 370.998305 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.040110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 585528663 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585528663 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192492893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192492893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97381046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97381046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289873939 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289873939 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289873939 # number of overall hits +system.cpu.dcache.overall_hits::total 289873939 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1579549 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1579549 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 920154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 920154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2499703 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2499703 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2499703 # number of overall misses +system.cpu.dcache.overall_misses::total 2499703 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79817656500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79817656500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57409075211 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57409075211 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137226731711 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137226731711 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137226731711 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137226731711 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194072442 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194072442 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292373642 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292373642 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292373642 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292373642 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008139 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008139 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009361 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009361 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008550 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008550 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008550 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008550 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50531.928101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50531.928101 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62390.725043 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62390.725043 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54897.214473 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54897.214473 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21908 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 55699 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 467 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.912206 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107.943798 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks +system.cpu.dcache.writebacks::total 91488 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867045 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 867045 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851323 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 851323 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1718368 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1718368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1718368 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1718368 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712504 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712504 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68831 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68831 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781335 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781335 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781335 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781335 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21874292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21874292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5221022246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5221022246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27095314246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27095314246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27095314246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27095314246 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30700.588348 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30700.588348 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75852.773402 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75852.773402 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 4662 # number of replacements +system.cpu.icache.tags.tagsinuse 1655.102487 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 196966072 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6374 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30901.486037 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.176031 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808191 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808191 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1655.102487 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.808156 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.808156 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1712 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1559 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 394124484 # Number of tag accesses -system.cpu.icache.tags.data_accesses 394124484 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 197050731 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 197050731 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 197050731 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 197050731 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 197050731 # number of overall hits -system.cpu.icache.overall_hits::total 197050731 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8321 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8321 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8321 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8321 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8321 # number of overall misses -system.cpu.icache.overall_misses::total 8321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333298749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333298749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333298749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333298749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333298749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333298749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 197059052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 197059052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 197059052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 197059052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 197059052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 197059052 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.835938 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 393955150 # Number of tag accesses +system.cpu.icache.tags.data_accesses 393955150 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 196966072 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 196966072 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 196966072 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 196966072 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 196966072 # number of overall hits +system.cpu.icache.overall_hits::total 196966072 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8316 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8316 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8316 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8316 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8316 # number of overall misses +system.cpu.icache.overall_misses::total 8316 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 334444749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 334444749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 334444749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 334444749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 334444749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 334444749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 196974388 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 196974388 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 196974388 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 196974388 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 196974388 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 196974388 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40055.131475 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40055.131475 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40055.131475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40055.131475 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 711 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40217.021284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40217.021284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40217.021284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40217.021284 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.636364 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 64.545455 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1940 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1940 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1940 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1940 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1940 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1940 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6381 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6381 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6381 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6381 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6381 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242585749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242585749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242585749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242585749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242585749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242585749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1941 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1941 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1941 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1941 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1941 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1941 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6375 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6375 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6375 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6375 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6375 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6375 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242697999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 242697999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242697999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242697999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242697999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242697999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38016.885911 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38016.885911 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38070.274353 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38070.274353 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38070.274353 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38070.274353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38070.274353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38070.274353 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258677 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32635.114541 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 518852 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291414 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.780464 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258673 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32635.253710 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518833 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291412 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.780411 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2797.134842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.663964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29769.315735 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.085362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002095 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.908487 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995945 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32737 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26521 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999054 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7394025 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7394025 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 490438 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 494069 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 2796.039745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.590417 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29770.623548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.085328 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.908527 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995949 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32739 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26528 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999115 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7393827 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7393827 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 3629 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 490422 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 494051 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91488 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91488 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2209 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2209 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492647 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 496278 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492647 # number of overall hits -system.cpu.l2cache.overall_hits::total 496278 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2750 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 222080 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224830 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66626 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2750 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 2207 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 2207 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3629 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 492629 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 496258 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3629 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 492629 # number of overall hits +system.cpu.l2cache.overall_hits::total 496258 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 222082 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224828 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66624 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66624 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2746 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 288706 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291456 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2750 # number of overall misses +system.cpu.l2cache.demand_misses::total 291452 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2746 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288706 # number of overall misses -system.cpu.l2cache.overall_misses::total 291456 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 199870250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16237138000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16437008250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5126307000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5126307000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 199870250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21363445000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21563315250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 199870250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21363445000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21563315250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6381 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712518 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 718899 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 291452 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200009500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16257189500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16457199000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5129902750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5129902750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200009500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 21387092250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21587101750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200009500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 21387092250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21587101750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6375 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712504 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 718879 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91488 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91488 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68835 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68835 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6381 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 781353 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787734 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6381 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 781353 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787734 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.430967 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311683 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.312742 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.967909 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.967909 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430967 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369495 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.369993 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430967 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369495 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.369993 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72680.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73113.913905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73108.607615 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76941.539339 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76941.539339 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72680.090909 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73997.232479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73984.804739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72680.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73997.232479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73984.804739 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 68831 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 68831 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6375 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 781335 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 787710 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6375 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 781335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 787710 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.430745 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311692 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.312748 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.967936 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.967936 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430745 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369503 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.369999 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430745 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369503 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.369999 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72836.671522 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73203.544186 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73199.063284 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76997.819855 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76997.819855 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72836.671522 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74079.140198 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74067.433917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72836.671522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74079.140198 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74067.433917 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,171 +930,103 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2750 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222080 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2750 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222082 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224828 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66624 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66624 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2746 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 288706 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291456 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2750 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2746 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288706 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291456 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 165177750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13468674500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13633852250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4310685500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4310685500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165177750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17779360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17944537750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165177750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17779360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17944537750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430967 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311683 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312742 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967909 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967909 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369495 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.369993 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369495 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.369993 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60064.636364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60647.849874 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60640.716319 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64699.749347 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64699.749347 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60064.636364 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61582.925190 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61568.599548 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60064.636364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61582.925190 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61568.599548 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 291452 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 165368000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13488499500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13653867500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4314074750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4314074750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17802574250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17967942250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17802574250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17967942250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.369999 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.369999 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60221.412964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60736.572527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60730.280481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64752.562890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64752.562890 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 777257 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.039658 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289884062 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781353 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 371.002686 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354263250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.039658 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2500 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 242 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585539447 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585539447 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192500682 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192500682 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97383359 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97383359 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 21 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 21 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289884041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289884041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289884041 # number of overall hits -system.cpu.dcache.overall_hits::total 289884041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1577144 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1577144 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 917841 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 917841 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2494985 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2494985 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2494985 # number of overall misses -system.cpu.dcache.overall_misses::total 2494985 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79985151750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79985151750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57294656713 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57294656713 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137279808463 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137279808463 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137279808463 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137279808463 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194077826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194077826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292379026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292379026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292379026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292379026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008126 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008126 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009337 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009337 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008533 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008533 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008533 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008533 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50715.186280 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50715.186280 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62423.291957 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62423.291957 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55022.298115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55022.298115 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21941 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 56666 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 465 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.184946 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 109.605416 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks -system.cpu.dcache.writebacks::total 91488 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 864626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 849006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 849006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1713632 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1713632 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1713632 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1713632 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712518 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712518 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68835 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68835 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781353 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781353 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781353 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781353 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21854414000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21854414000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5217448748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5217448748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27071862748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27071862748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27071862748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27071862748 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30672.086881 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30672.086881 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75796.451631 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75796.451631 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 718879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68831 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55860672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56268608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 879198 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879198 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 879198 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531087000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10054750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1207495250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224827 # Transaction distribution +system.membus.trans_dist::ReadResp 224827 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66624 # Transaction distribution +system.membus.trans_dist::ReadExResp 66624 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649585 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649585 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358134 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358134 # Request fanout histogram +system.membus.reqLayer0.occupancy 959207000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2708819750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 531c5ebad..11060cf95 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541781 # Number of seconds simulated -sim_ticks 541781076000 # Number of ticks simulated -final_tick 541781076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541786 # Number of seconds simulated +sim_ticks 541786101000 # Number of ticks simulated +final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140173 # Simulator instruction rate (inst/s) -host_op_rate 172571 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118539448 # Simulator tick rate (ticks/s) -host_mem_usage 261676 # Number of bytes of host memory used -host_seconds 4570.47 # Real time elapsed on the host +host_inst_rate 183531 # Simulator instruction rate (inst/s) +host_op_rate 225950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155207340 # Simulator tick rate (ticks/s) +host_mem_usage 320704 # Number of bytes of host memory used +host_seconds 3490.72 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,43 +23,43 @@ system.physmem.num_reads::cpu.inst 290529 # Nu system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34319870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34319870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34319870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42127954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34319552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18573248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18139 # Per bank write bursts -system.physmem.perBankRdBursts::2 18224 # Per bank write bursts -system.physmem.perBankRdBursts::3 18182 # Per bank write bursts -system.physmem.perBankRdBursts::4 18264 # Per bank write bursts -system.physmem.perBankRdBursts::5 18315 # Per bank write bursts -system.physmem.perBankRdBursts::6 18098 # Per bank write bursts +system.physmem.perBankRdBursts::0 18289 # Per bank write bursts +system.physmem.perBankRdBursts::1 18137 # Per bank write bursts +system.physmem.perBankRdBursts::2 18222 # Per bank write bursts +system.physmem.perBankRdBursts::3 18184 # Per bank write bursts +system.physmem.perBankRdBursts::4 18266 # Per bank write bursts +system.physmem.perBankRdBursts::5 18308 # Per bank write bursts +system.physmem.perBankRdBursts::6 18094 # Per bank write bursts system.physmem.perBankRdBursts::7 17914 # Per bank write bursts -system.physmem.perBankRdBursts::8 17936 # Per bank write bursts -system.physmem.perBankRdBursts::9 17963 # Per bank write bursts -system.physmem.perBankRdBursts::10 18015 # Per bank write bursts +system.physmem.perBankRdBursts::8 17939 # Per bank write bursts +system.physmem.perBankRdBursts::9 17962 # Per bank write bursts +system.physmem.perBankRdBursts::10 18018 # Per bank write bursts system.physmem.perBankRdBursts::11 18110 # Per bank write bursts -system.physmem.perBankRdBursts::12 18146 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18075 # Per bank write bursts -system.physmem.perBankRdBursts::15 18267 # Per bank write bursts +system.physmem.perBankRdBursts::12 18143 # Per bank write bursts +system.physmem.perBankRdBursts::13 18270 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18266 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4101 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541780987500 # Total gap between requests +system.physmem.totGap 541786012500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,42 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.445337 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.546078 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.289579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46919 42.07% 42.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43694 39.18% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8696 7.80% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 722 0.65% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1258 1.13% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1255 1.13% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 576 0.52% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 502 0.45% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7898 7.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111520 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.543798 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.072613 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.664819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.488645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.467122 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3028 75.57% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 2702187250 # Total ticks spent queuing -system.physmem.totMemAccLat 8143568500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9311.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads +system.physmem.totQLat 2707676000 # Total ticks spent queuing +system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28061.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s @@ -235,35 +237,40 @@ system.physmem.busUtilRead 0.27 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing -system.physmem.readRowHits 194639 # Number of row buffer hits during reads -system.physmem.writeRowHits 50105 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.80 # Row buffer hit rate for writes -system.physmem.avgGap 1519181.07 # Average gap between requests -system.physmem.pageHitRate 68.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 263887343000 # Time in different power states -system.physmem.memoryStateTime::REF 18091060000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 259796939500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 421530480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 421462440 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 230001750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 229964625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1134174600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1128987600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 215628480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212505120 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 35386113360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 35386113360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 105979651695 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 105556941405 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 232100586000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 232471384500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 375467686365 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 375407359050 # Total energy per rank (pJ) -system.physmem.averagePower::0 693.032096 # Core power per rank (mW) -system.physmem.averagePower::1 692.920745 # Core power per rank (mW) +system.physmem.readRowHits 194608 # Number of row buffer hits during reads +system.physmem.writeRowHits 50098 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes +system.physmem.avgGap 1519195.16 # Average gap between requests +system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.117148 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.890615 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 156937341 # Number of BP lookups system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect @@ -274,6 +281,14 @@ system.cpu.branchPred.BTBHitPct 83.942615 # BT system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -295,6 +310,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -316,6 +339,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +368,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -359,24 +398,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083562152 # number of cpu cycles simulated +system.cpu.numCycles 1083572202 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691335 # CPI: cycles per instruction -system.cpu.ipc 0.591249 # IPC: instructions per cycle -system.cpu.tickCycles 1029140125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54422027 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.691350 # CPI: cycles per instruction +system.cpu.ipc 0.591244 # IPC: instructions per cycle +system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778221 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.644165 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 752182250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.644165 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.645412 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -408,14 +447,14 @@ system.cpu.dcache.demand_misses::cpu.inst 851460 # n system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23050728217 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23050728217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9196889000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9196889000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32247617217 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32247617217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32247617217 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32247617217 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32255064217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) @@ -436,14 +475,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37873.320199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37873.320199 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +509,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21540338778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21540338778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529678750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529678750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26070017528 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26070017528 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26070017528 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26070017528 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses @@ -486,22 +525,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23590 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.180354 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289921724 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11440.816227 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180354 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -509,44 +548,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 57 system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579919473 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579919473 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289921724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289921724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289921724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289921724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289921724 # number of overall hits -system.cpu.icache.overall_hits::total 289921724 # number of overall hits +system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits +system.cpu.icache.overall_hits::total 289921723 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses system.cpu.icache.overall_misses::total 25342 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 481750746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 481750746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 481750746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 481750746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 481750746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 481750746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289947066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289947066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289947066 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289947066 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289947066 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289947066 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19009.973404 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19009.973404 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25342 system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429966254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 429966254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429966254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 429966254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429966254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 429966254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16966.547786 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16966.547786 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32583.074549 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2860.585859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.488690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087298 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907058 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994357 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id @@ -618,14 +657,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 290562 # system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses system.cpu.l2cache.overall_misses::total 290562 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16093224000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16093224000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4428044750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4428044750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20521268750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20521268750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20521268750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20521268750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20526854250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) @@ -644,14 +683,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,14 +715,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13281416250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13281416250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3575940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3575940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16857356500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16857356500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16857356500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16857356500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16862626750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses @@ -692,14 +731,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution @@ -732,7 +771,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # La system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224341972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224438 # Transaction distribution system.membus.trans_dist::ReadResp 224438 # Transaction distribution @@ -754,9 +793,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 356627 # Request fanout histogram -system.membus.reqLayer0.occupancy 983533000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2738969000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 57de3b3e6..5cb40d175 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.407884 # Number of seconds simulated -sim_ticks 407883784500 # Number of ticks simulated -final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.408037 # Number of seconds simulated +sim_ticks 408037199500 # Number of ticks simulated +final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91246 # Simulator instruction rate (inst/s) -host_op_rate 112336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58093586 # Simulator tick rate (ticks/s) -host_mem_usage 2566152 # Number of bytes of host memory used -host_seconds 7021.15 # Real time elapsed on the host +host_inst_rate 90640 # Simulator instruction rate (inst/s) +host_op_rate 111590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57729920 # Simulator tick rate (ticks/s) +host_mem_usage 318440 # Number of bytes of host memory used +host_seconds 7068.04 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6867584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 13490752 # Number of bytes read from this memory -system.physmem.bytes_read::total 20421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243968 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 107306 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 210793 # Number of read requests responded to by this memory -system.physmem.num_reads::total 319089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66312 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66312 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 155338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16837110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 33074990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50067438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10404846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10404846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10404846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16837110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 33074990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60472284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 319089 # Number of read requests accepted -system.physmem.writeReqs 66312 # Number of write requests accepted -system.physmem.readBursts 319089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66312 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20403200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20421696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 20089 # Per bank write bursts -system.physmem.perBankRdBursts::1 19545 # Per bank write bursts -system.physmem.perBankRdBursts::2 20086 # Per bank write bursts -system.physmem.perBankRdBursts::3 20646 # Per bank write bursts -system.physmem.perBankRdBursts::4 19933 # Per bank write bursts -system.physmem.perBankRdBursts::5 20704 # Per bank write bursts -system.physmem.perBankRdBursts::6 19571 # Per bank write bursts -system.physmem.perBankRdBursts::7 19471 # Per bank write bursts -system.physmem.perBankRdBursts::8 19556 # Per bank write bursts -system.physmem.perBankRdBursts::9 19505 # Per bank write bursts -system.physmem.perBankRdBursts::10 19502 # Per bank write bursts -system.physmem.perBankRdBursts::11 20173 # Per bank write bursts -system.physmem.perBankRdBursts::12 19634 # Per bank write bursts -system.physmem.perBankRdBursts::13 20280 # Per bank write bursts -system.physmem.perBankRdBursts::14 19577 # Per bank write bursts -system.physmem.perBankRdBursts::15 20528 # Per bank write bursts -system.physmem.perBankWrBursts::0 4247 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory +system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315254 # Number of read requests accepted +system.physmem.writeReqs 66324 # Number of write requests accepted +system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19893 # Per bank write bursts +system.physmem.perBankRdBursts::1 19507 # Per bank write bursts +system.physmem.perBankRdBursts::2 19696 # Per bank write bursts +system.physmem.perBankRdBursts::3 19811 # Per bank write bursts +system.physmem.perBankRdBursts::4 19755 # Per bank write bursts +system.physmem.perBankRdBursts::5 20266 # Per bank write bursts +system.physmem.perBankRdBursts::6 19606 # Per bank write bursts +system.physmem.perBankRdBursts::7 19431 # Per bank write bursts +system.physmem.perBankRdBursts::8 19468 # Per bank write bursts +system.physmem.perBankRdBursts::9 19384 # Per bank write bursts +system.physmem.perBankRdBursts::10 19414 # Per bank write bursts +system.physmem.perBankRdBursts::11 19672 # Per bank write bursts +system.physmem.perBankRdBursts::12 19624 # Per bank write bursts +system.physmem.perBankRdBursts::13 19992 # Per bank write bursts +system.physmem.perBankRdBursts::14 19481 # Per bank write bursts +system.physmem.perBankRdBursts::15 19957 # Per bank write bursts +system.physmem.perBankWrBursts::0 4278 # Per bank write bursts system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4151 # Per bank write bursts -system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::2 4141 # Per bank write bursts +system.physmem.perBankWrBursts::3 4152 # Per bank write bursts +system.physmem.perBankWrBursts::4 4250 # Per bank write bursts system.physmem.perBankWrBursts::5 4232 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4153 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 407883730500 # Total gap between requests +system.physmem.totGap 408037145000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 319089 # Read request sizes (log2) +system.physmem.readPktSize::6 315254 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66312 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 124916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 644 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66324 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,189 +148,171 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 138324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.138053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.082938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 199.804046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 55124 39.85% 39.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 58239 42.10% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14671 10.61% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 966 0.70% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1420 1.03% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1368 0.99% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1462 1.06% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1224 0.88% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3850 2.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 138324 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 67.829475 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.454654 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 482.917109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3981 99.10% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 5 0.12% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 3 0.07% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 2 0.05% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 2 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.484690 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.435555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.421529 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3367 83.82% 83.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.22% 84.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 437 10.88% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 79 1.97% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 37 0.92% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.45% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.55% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.32% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.07% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.15% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.07% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 9958454882 # Total ticks spent queuing -system.physmem.totMemAccLat 15935954882 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1594000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31237.31 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads +system.physmem.totQLat 9384520258 # Total ticks spent queuing +system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49987.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.07 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.47 # Data bus utilization in percentage system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 219908 # Number of row buffer hits during reads -system.physmem.writeRowHits 26785 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.43 # Row buffer hit rate for writes -system.physmem.avgGap 1058335.94 # Average gap between requests -system.physmem.pageHitRate 64.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 155274651966 # Time in different power states -system.physmem.memoryStateTime::REF 13620100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 524928600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 520778160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 286419375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 284154750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1248351000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1238000400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216380160 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212718960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26640915600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26640915600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 97043660235 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 97028348895 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 159603762000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 159617193000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 285564416970 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 285542109765 # Total energy per rank (pJ) -system.physmem.averagePower::0 700.113612 # Core power per rank (mW) -system.physmem.averagePower::1 700.058922 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 317731 # Transaction distribution -system.membus.trans_dist::ReadResp 317731 # Transaction distribution -system.membus.trans_dist::Writeback 66312 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19 # Transaction distribution -system.membus.trans_dist::UpgradeResp 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 1358 # Transaction distribution -system.membus.trans_dist::ReadExResp 1358 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 704528 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 704528 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24665664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24665664 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 385420 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 385420 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 385420 # Request fanout histogram -system.membus.reqLayer0.occupancy 968060850 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2930140600 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 233961455 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822903 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15515021 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121571694 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108258179 # Number of BTB hits +system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 218395 # Number of row buffer hits during reads +system.physmem.writeRowHits 26455 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes +system.physmem.avgGap 1069341.38 # Average gap between requests +system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.765171 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states +system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.696391 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states +system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 233958621 # Number of BP lookups +system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.048836 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25034450 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300530 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -352,6 +334,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -373,6 +363,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,6 +392,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -416,95 +422,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 815767570 # number of cpu cycles simulated +system.cpu.numCycles 816074400 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064711 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370072724 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652087 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 815611997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.839157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134572174 16.50% 16.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 222502254 27.28% 43.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98076609 12.02% 55.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360460960 44.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 815611997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286799 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.471100 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119967047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 156830594 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662032 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38633655 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25180757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13832 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248142745 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176978211 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77349013 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 209115 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464956606 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80600383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190653187 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25546667 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24946830 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267986 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40254462 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1692453 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225396135 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812466885 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358185264 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876472 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350617905 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7272 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 7264 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108149104 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366119032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236098756 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1753479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5371728 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168565166 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017100859 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18396242 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379746204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032205063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 815611997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.247040 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 257903097 31.62% 31.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 228438073 28.01% 59.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215325690 26.40% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97769150 11.99% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16175979 1.98% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 815611997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64512923 19.13% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18147 0.01% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available @@ -532,13 +538,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155504488 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116641749 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456383765 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195693 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -560,90 +566,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550151 0.25% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478998 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322094029 31.67% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215573019 21.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017100859 # Type of FU issued -system.cpu.iq.rate 1.246802 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337314196 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331643 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3143647062 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504776491 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934274751 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877091 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565761 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152451 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320604680 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810375 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960281 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued +system.cpu.iq.rate 1.246337 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113878094 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1252 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107118260 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23979 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35328826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 675397 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168583078 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366119032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236098756 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 121 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 678981 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437712 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19222483 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974757504 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303300667 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42343355 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5552 # number of nop insts executed -system.cpu.iew.exec_refs 497757295 # number of memory reference insts executed -system.cpu.iew.exec_branches 150614518 # Number of branches executed -system.cpu.iew.exec_stores 194456628 # Number of stores executed -system.cpu.iew.exec_rate 1.194896 # Inst execution rate -system.cpu.iew.wb_sent 963726633 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960427202 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536683301 # num instructions producing a value -system.cpu.iew.wb_consumers 893293358 # num instructions consuming a value +system.cpu.iew.exec_nop 5556 # number of nop insts executed +system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed +system.cpu.iew.exec_branches 150614661 # Number of branches executed +system.cpu.iew.exec_stores 194464042 # Number of stores executed +system.cpu.iew.exec_rate 1.194456 # Inst execution rate +system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536684839 # num instructions producing a value +system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.177329 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600792 # average fanout of values written-back +system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357423726 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15501335 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764789514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.031303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.790973 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 428726988 56.06% 56.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171833427 22.47% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566428 9.62% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31619643 4.13% 92.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7902471 1.03% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14889027 1.95% 95.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7271717 0.95% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6618968 0.87% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360845 2.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764789514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -689,507 +695,529 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1888573713 # The number of ROB reads -system.cpu.rob.rob_writes 2343133826 # The number of ROB writes -system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1888745890 # The number of ROB reads +system.cpu.rob.rob_writes 2343137518 # The number of ROB writes +system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.273345 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads -system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995802642 # number of integer regfile reads -system.cpu.int_regfile_writes 567917186 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794452598 # number of cc regfile reads -system.cpu.cc_regfile_writes 384905504 # number of cc regfile writes -system.cpu.misc_regfile_reads 715806131 # number of misc regfile reads +system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads +system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995816176 # number of integer regfile reads +system.cpu.int_regfile_writes 567918829 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads +system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes +system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 7205652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7205652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 9840757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339627 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248397 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16588024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330867456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223467584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554335040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 9840776 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18503299 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.531838 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.498985 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 8662542 46.82% 46.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 9840757 53.18% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18503299 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5066671498 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754858551 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4142472532 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 5169293 # number of replacements -system.cpu.icache.tags.tagsinuse 510.870067 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364901080 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.583169 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 199337500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.870067 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 325 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745315243 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745315243 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364901109 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364901109 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364901109 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364901109 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364901109 # number of overall hits -system.cpu.icache.overall_hits::total 364901109 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171601 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171601 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171601 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171601 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171601 # number of overall misses -system.cpu.icache.overall_misses::total 5171601 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41478755019 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41478755019 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41478755019 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41478755019 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41478755019 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41478755019 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370072710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370072710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370072710 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370072710 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370072710 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370072710 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8020.486310 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8020.486310 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8020.486310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8020.486310 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17792 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1782 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9.984287 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1778 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1778 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1778 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1778 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1778 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1778 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169823 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169823 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169823 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169823 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169823 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33703861415 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33703861415 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33703861415 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33703861415 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33703861415 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33703861415 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6519.345327 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6519.345327 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 42714534 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 332916 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 32636070 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 18709 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3827 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 9723012 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4810754 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 302773 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16364.911497 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7827990 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 319143 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.528158 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 12938833000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 727.090986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.045333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8487.644412 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 7101.130766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.044378 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.518045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.433419 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998835 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 7180 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9190 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1499 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 5110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2000 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.438232 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.560913 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139624071 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139624071 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5168280 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1928699 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7096979 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 735005 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 735005 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718110 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718110 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5168280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2646809 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7815089 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5168280 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2646809 # number of overall hits -system.cpu.l2cache.overall_hits::total 7815089 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 107130 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 108654 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2737 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2737 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 109867 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 111391 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1524 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 109867 # number of overall misses -system.cpu.l2cache.overall_misses::total 111391 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107432161 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7354763933 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 7462196094 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 174400348 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 174400348 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107432161 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7529164281 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7636596442 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107432161 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7529164281 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7636596442 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169804 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 2035829 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7205633 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 735005 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 735005 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5169804 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756676 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7926480 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5169804 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756676 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7926480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.052622 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015079 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.950000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.950000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003797 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003797 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000295 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.039855 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014053 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000295 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.039855 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014053 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70493.543963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68652.701699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68678.521674 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63719.527950 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63719.527950 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68556.673717 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68556.673717 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 126545 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2364 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53.530034 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66312 # number of writebacks -system.cpu.l2cache.writebacks::total 66312 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 534 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1182 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1716 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1379 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1379 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 534 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2561 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3095 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 534 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2561 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3095 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 990 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 105948 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 106938 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 9723012 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1358 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1358 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 107306 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 108296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 107306 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 9831308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71873499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6404181248 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6476054747 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19431970184 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 143518 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 143518 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92793756 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92793756 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71873499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6496975004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6568848503 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71873499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6496975004 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26000818687 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.052042 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.014841 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.950000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.950000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.013663 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.240312 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72599.493939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60446.457205 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60558.966382 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 1998.554582 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 7553.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 7553.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68331.189985 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68331.189985 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.427781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 2644.695771 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2756164 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.948880 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414248795 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756676 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.271122 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 207459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.948880 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999900 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999900 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756166 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347154 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347154 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286297439 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286297439 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127936631 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127936631 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414234070 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414234070 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414237227 # number of overall hits -system.cpu.dcache.overall_hits::total 414237227 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031039 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031039 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1014846 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1014846 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 648 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 648 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits +system.cpu.dcache.overall_hits::total 414238542 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4045885 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4045885 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4046533 # number of overall misses -system.cpu.dcache.overall_misses::total 4046533 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33719933619 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33719933619 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9704111685 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9704111685 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 169500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 169500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43424045304 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43424045304 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43424045304 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43424045304 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses +system.cpu.dcache.overall_misses::total 4045534 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3805 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3805 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279955 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279955 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283760 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010476 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007870 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007870 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170302 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.170302 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009673 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009674 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009674 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11124.876196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11124.876196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9562.151977 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9562.151977 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10732.891643 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10732.891643 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10731.172909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10731.172909 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 339239 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5513 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.534373 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735005 # number of writebacks -system.cpu.dcache.writebacks::total 735005 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995853 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 995853 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293979 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 293979 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks +system.cpu.dcache.writebacks::total 735128 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1289832 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1289832 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1289832 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1289832 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720867 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720867 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 643 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 643 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756053 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756053 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756696 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756696 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20990186992 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20990186992 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5237168826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5237168826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5228000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5228000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26227355818 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26227355818 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26232583818 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26232583818 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2756054 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756054 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756695 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756695 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21052594116 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21052594116 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5256752100 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5256752100 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5684476 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5684476 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26309346216 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26309346216 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26315030692 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26315030692 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168988 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168988 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10313.645530 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10313.645530 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7265.097204 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7265.097204 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8130.637636 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8130.637636 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9516.274113 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9516.274113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9515.950913 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9515.950913 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9546.019859 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9546.019859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9545.862234 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9545.862234 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 5169210 # number of replacements +system.cpu.icache.tags.tagsinuse 510.721915 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364899992 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169720 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 745313375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 745313375 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 364900028 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 364900028 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 364900028 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 364900028 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 364900028 # number of overall hits +system.cpu.icache.overall_hits::total 364900028 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5171791 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5171791 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5171791 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5171791 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5171791 # number of overall misses +system.cpu.icache.overall_misses::total 5171791 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41611685167 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41611685167 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41611685167 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41611685167 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41611685167 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41611685167 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370071819 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370071819 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370071819 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370071819 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370071819 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370071819 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8045.894578 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8045.894578 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8045.894578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.075480 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 9.750000 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169737 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5169737 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33819004202 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6541.726243 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6541.726243 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.prefetcher.num_hwpf_issued 1345350 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355301 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 8714 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4790331 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 298968 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16361.863198 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7823723 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 315332 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.811066 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13372026000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 741.351492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.669964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8767.936523 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6722.905220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.045249 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007914 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.535152 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6534 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 9830 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1473 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4885 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2092 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.398804 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599976 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139620886 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139620886 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5166160 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1926359 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7092519 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 735128 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 735128 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 717996 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 717996 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5166160 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2644355 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7810515 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5166160 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2644355 # number of overall hits +system.cpu.l2cache.overall_hits::total 7810515 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3561 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 109472 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 113033 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2851 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2851 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3561 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 112323 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 115884 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3561 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 112323 # number of overall misses +system.cpu.l2cache.overall_misses::total 115884 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 237049229 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7458222067 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 7695271296 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 224011514 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 224011514 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 237049229 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7682233581 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7919282810 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 237049229 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7682233581 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7919282810 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169721 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 2035831 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7205552 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 735128 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 735128 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5169721 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7926399 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5169721 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7926399 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053773 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015687 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823529 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823529 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003955 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003955 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.040746 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014620 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.040746 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014620 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66568.163156 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68129.038174 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68079.864252 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78572.961768 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78572.961768 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68338.017414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68338.017414 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks +system.cpu.l2cache.writebacks::total 66324 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3550 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109507 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113057 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3550 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 109507 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202272 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 315329 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205967021 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6469574626 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6675541647 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18462254833 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 84014 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 84014 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126131000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126131000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205967021 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6595705626 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6801672647 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205967021 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 317003 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 313877 # Transaction distribution +system.membus.trans_dist::ReadResp 313877 # Transaction distribution +system.membus.trans_dist::Writeback 66324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 14 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 381592 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 381592 # Request fanout histogram +system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index b5ba9b69f..4817ec8a9 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1695212 # Simulator instruction rate (inst/s) -host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1047118075 # Simulator tick rate (ticks/s) -host_mem_usage 304696 # Number of bytes of host memory used -host_seconds 377.92 # Real time elapsed on the host +host_inst_rate 1395078 # Simulator instruction rate (inst/s) +host_op_rate 1717525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 861727739 # Simulator tick rate (ticks/s) +host_mem_usage 309420 # Number of bytes of host memory used +host_seconds 459.22 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1322421029 # Wr system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 893703777 # Transaction distribution -system.membus.trans_dist::ReadResp 893709516 # Transaction distribution -system.membus.trans_dist::WriteReq 128951477 # Transaction distribution -system.membus.trans_dist::WriteResp 128951477 # Transaction distribution -system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution -system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram -system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 1022670352 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction +system.membus.trans_dist::ReadReq 893703777 # Transaction distribution +system.membus.trans_dist::ReadResp 893709516 # Transaction distribution +system.membus.trans_dist::WriteReq 128951477 # Transaction distribution +system.membus.trans_dist::WriteResp 128951477 # Transaction distribution +system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution +system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram +system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 1022670352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index b1098c721..c5e3a18fc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.043695 # Nu sim_ticks 1043695084000 # Number of ticks simulated final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 974812 # Simulator instruction rate (inst/s) -host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1591272225 # Simulator tick rate (ticks/s) -host_mem_usage 314196 # Number of bytes of host memory used -host_seconds 655.89 # Real time elapsed on the host +host_inst_rate 894518 # Simulator instruction rate (inst/s) +host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1460200235 # Simulator tick rate (ticks/s) +host_mem_usage 317628 # Number of bytes of host memory used +host_seconds 714.76 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 4053168 # To system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 223619 # Transaction distribution -system.membus.trans_dist::ReadResp 223619 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::ReadExReq 66093 # Transaction distribution -system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 355811 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,145 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.dcache.tags.replacements 778046 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits +system.cpu.dcache.overall_hits::total 378498833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses +system.cpu.dcache.overall_misses::total 782143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks +system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. @@ -438,145 +585,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits -system.cpu.dcache.overall_hits::total 378498833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses -system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks -system.cpu.dcache.writebacks::total 91561 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution @@ -610,5 +618,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 15312000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66093 # Transaction distribution +system.membus.trans_dist::ReadExResp 66093 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 355811 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 355811 # Request fanout histogram +system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |