diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/40.perlbmk/ref | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
11 files changed, 1019 insertions, 999 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 5d9ef8c4a..721f1a541 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -817,7 +817,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/li gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout pgid=100 pid=100 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index fb1e27e73..6aa244964 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 2 2017 11:48:43 -gem5 started Apr 2 2017 11:49:00 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87253 +gem5 compiled Apr 3 2017 04:18:56 +gem5 started Apr 3 2017 04:19:11 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 3566 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -647,4 +647,4 @@ Global frequency set at 1000000000000 ticks per second 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 339069355000 because target called exit() +Exiting @ tick 339069355000 because exiting with last active thread context diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 48dadbf2b..51dd3b610 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.339069 sim_ticks 339069355000 final_tick 339069355000 sim_freq 1000000000000 -host_inst_rate 200289 -host_op_rate 246583 -host_tick_rate 106004783 -host_mem_usage 288044 -host_seconds 3198.62 +host_inst_rate 210410 +host_op_rate 259043 +host_tick_rate 111361442 +host_mem_usage 288088 +host_seconds 3044.76 sim_insts 640649299 sim_ops 788724958 system.voltage_domain.voltage 1 @@ -458,7 +458,7 @@ system.cpu.fetch.Insts 824295259 system.cpu.fetch.Branches 175312537 system.cpu.fetch.predictedBranches 103250498 system.cpu.fetch.Cycles 638595633 -system.cpu.fetch.SquashCycles 8083491 +system.cpu.fetch.SquashCycles 8083490 system.cpu.fetch.MiscStallCycles 2728 system.cpu.fetch.PendingTrapStallCycles 17 system.cpu.fetch.IcacheWaitRetryStallCycles 3109 @@ -516,7 +516,7 @@ system.cpu.iq.iqInstsAdded 899826395 system.cpu.iq.iqNonSpecInstsAdded 12582 system.cpu.iq.iqInstsIssued 860048195 system.cpu.iq.iqSquashedInstsIssued 9222152 -system.cpu.iq.iqSquashedInstsExamined 111114019 +system.cpu.iq.iqSquashedInstsExamined 111114018 system.cpu.iq.iqSquashedOperandsExamined 244270336 system.cpu.iq.iqSquashedNonSpecRemoved 428 system.cpu.iq.issued_per_cycle::samples 677669366 @@ -617,7 +617,7 @@ system.cpu.iq.rate 1.268248 system.cpu.iq.fu_busy_cnt 277608649 system.cpu.iq.fu_busy_rate 0.322783 system.cpu.iq.int_inst_queue_reads 2621941266 -system.cpu.iq.int_inst_queue_writes 980329396 +system.cpu.iq.int_inst_queue_writes 980329395 system.cpu.iq.int_inst_queue_wakeup_accesses 820105906 system.cpu.iq.fp_inst_queue_reads 62655291 system.cpu.iq.fp_inst_queue_writes 30642249 @@ -735,7 +735,7 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% system.cpu.commit.op_class_0::total 788730070 system.cpu.commit.bw_lim_events 29951867 system.cpu.rob.rob_reads 1525019812 -system.cpu.rob.rob_writes 1798395927 +system.cpu.rob.rob_writes 1798395926 system.cpu.timesIdled 10540 system.cpu.idleCycles 469345 system.cpu.committedInsts 640649299 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 5997dda79..8d15582fe 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=perlbmk -I. -I lib mdred.makerand.pl cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr index 937e051a4..92c744310 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr @@ -1,3 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: fcntl64(3, 2) passed through to host +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 74eea3e5b..2146043b6 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-at gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:51:02 -gem5 executing on e108600-lin, pid 23320 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:15 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54237 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. 637000: 2581848540 636000: 4117852332 635000: 329081094 @@ -650,4 +647,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 395726778500 because target called exit() +Exiting @ tick 395726778500 because exiting with last active thread context diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index c1630ee45..b1e10c075 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.395727 # Number of seconds simulated -sim_ticks 395726778500 # Number of ticks simulated -final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1825974 # Simulator instruction rate (inst/s) -host_op_rate 2248015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127888505 # Simulator tick rate (ticks/s) -host_mem_usage 268260 # Number of bytes of host memory used -host_seconds 350.86 # Real time elapsed on the host -sim_insts 640654411 # Number of instructions simulated -sim_ops 788730070 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory -system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory -system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory -system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 791453558 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 640654411 # Number of instructions committed -system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction -system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 893703778 # Transaction distribution -system.membus.trans_dist::ReadResp 893709517 # Transaction distribution -system.membus.trans_dist::WriteReq 128951477 # Transaction distribution -system.membus.trans_dist::WriteResp 128951477 # Transaction distribution -system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution -system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1022670353 # Request fanout histogram +sim_seconds 0.395727 +sim_ticks 395726778500 +final_tick 395726778500 +sim_freq 1000000000000 +host_inst_rate 761557 +host_op_rate 937577 +host_tick_rate 470407263 +host_mem_usage 279508 +host_seconds 841.24 +sim_insts 640654411 +sim_ops 788730070 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.physmem.bytes_read::cpu.inst 2573511596 +system.physmem.bytes_read::cpu.data 1144718516 +system.physmem.bytes_read::total 3718230112 +system.physmem.bytes_inst_read::cpu.inst 2573511596 +system.physmem.bytes_inst_read::total 2573511596 +system.physmem.bytes_written::cpu.data 523317413 +system.physmem.bytes_written::total 523317413 +system.physmem.num_reads::cpu.inst 643377899 +system.physmem.num_reads::cpu.data 250335238 +system.physmem.num_reads::total 893713137 +system.physmem.num_writes::cpu.data 128957216 +system.physmem.num_writes::total 128957216 +system.physmem.bw_read::cpu.inst 6503253598 +system.physmem.bw_read::cpu.data 2892699151 +system.physmem.bw_read::total 9395952748 +system.physmem.bw_inst_read::cpu.inst 6503253598 +system.physmem.bw_inst_read::total 6503253598 +system.physmem.bw_write::cpu.data 1322421027 +system.physmem.bw_write::total 1322421027 +system.physmem.bw_total::cpu.inst 6503253598 +system.physmem.bw_total::cpu.data 4215120178 +system.physmem.bw_total::total 10718373776 +system.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 673 +system.cpu.pwrStateResidencyTicks::ON 395726778500 +system.cpu.numCycles 791453558 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 640654411 +system.cpu.committedOps 788730070 +system.cpu.num_int_alu_accesses 682251400 +system.cpu.num_fp_alu_accesses 24239771 +system.cpu.num_func_calls 37261296 +system.cpu.num_conditional_control_insts 91575866 +system.cpu.num_int_insts 682251400 +system.cpu.num_fp_insts 24239771 +system.cpu.num_int_register_reads 1268495038 +system.cpu.num_int_register_writes 468423268 +system.cpu.num_fp_register_reads 28064643 +system.cpu.num_fp_register_writes 21684311 +system.cpu.num_cc_register_reads 2369173294 +system.cpu.num_cc_register_writes 351919006 +system.cpu.num_mem_refs 381221435 +system.cpu.num_load_insts 252240938 +system.cpu.num_store_insts 128980497 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 791453558 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 137364860 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% +system.cpu.op_class::IntMult 5173441 0.66% 49.56% +system.cpu.op_class::IntDiv 0 0.00% 49.56% +system.cpu.op_class::FloatAdd 0 0.00% 49.56% +system.cpu.op_class::FloatCmp 0 0.00% 49.56% +system.cpu.op_class::FloatCvt 0 0.00% 49.56% +system.cpu.op_class::FloatMult 0 0.00% 49.56% +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% +system.cpu.op_class::FloatDiv 0 0.00% 49.56% +system.cpu.op_class::FloatMisc 0 0.00% 49.56% +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdAdd 0 0.00% 49.56% +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% +system.cpu.op_class::SimdAlu 0 0.00% 49.56% +system.cpu.op_class::SimdCmp 0 0.00% 49.56% +system.cpu.op_class::SimdCvt 0 0.00% 49.56% +system.cpu.op_class::SimdMisc 0 0.00% 49.56% +system.cpu.op_class::SimdMult 0 0.00% 49.56% +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% +system.cpu.op_class::SimdShift 0 0.00% 49.56% +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% +system.cpu.op_class::MemRead 245222568 31.09% 82.76% +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 788730744 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.membus.trans_dist::ReadReq 893703778 +system.membus.trans_dist::ReadResp 893709517 +system.membus.trans_dist::WriteReq 128951477 +system.membus.trans_dist::WriteResp 128951477 +system.membus.trans_dist::SoftPFReq 3620 +system.membus.trans_dist::SoftPFResp 3620 +system.membus.trans_dist::LoadLockedReq 5739 +system.membus.trans_dist::StoreCondReq 5739 +system.membus.trans_dist::StoreCondResp 5739 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 +system.membus.pkt_count::total 2045340706 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 +system.membus.pkt_size::total 4241547525 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1022670353 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1022670353 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1022670353 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index ab5a083f3..b54691470 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=perlbmk -I. -I lib mdred.makerand.pl cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr index 937e051a4..92c744310 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: fcntl64(3, 2) passed through to host +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 75004ec86..e660db33d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:46:39 -gem5 executing on e108600-lin, pid 23194 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:24:09 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59398 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. 637000: 2581848540 636000: 4117852332 635000: 329081094 @@ -650,4 +647,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 1045756396500 because target called exit() +Exiting @ tick 1046047111500 because exiting with last active thread context diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e6b9bff19..be07be0d5 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,686 +1,686 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.046047 # Number of seconds simulated -sim_ticks 1046047111500 # Number of ticks simulated -final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1255251 # Simulator instruction rate (inst/s) -host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2053674689 # Simulator tick rate (ticks/s) -host_mem_usage 277480 # Number of bytes of host memory used -host_seconds 509.35 # Real time elapsed on the host -sim_insts 639366787 # Number of instructions simulated -sim_ops 785501035 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory -system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2092094223 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 639366787 # Number of instructions committed -system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1272307653 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction -system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits -system.cpu.dcache.overall_hits::total 378498833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses -system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks -system.cpu.dcache.writebacks::total 88967 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits -system.cpu.icache.overall_hits::total 643367692 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses -system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 8769 # number of writebacks -system.cpu.icache.writebacks::total 8769 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10208 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 257791 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits 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3998679500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks -system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257791 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224282 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190103 # Transaction distribution -system.membus.trans_dist::ReadExReq 66093 # Transaction distribution -system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 290376 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 290376 # Request fanout histogram -system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 1.046047 +sim_ticks 1046047111500 +final_tick 1046047111500 +sim_freq 1000000000000 +host_inst_rate 550252 +host_op_rate 676018 +host_tick_rate 900249421 +host_mem_usage 289500 +host_seconds 1161.95 +sim_insts 639366787 +sim_ops 785501035 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.physmem.bytes_read::cpu.inst 112576 +system.physmem.bytes_read::cpu.data 18471424 +system.physmem.bytes_read::total 18584000 +system.physmem.bytes_inst_read::cpu.inst 112576 +system.physmem.bytes_inst_read::total 112576 +system.physmem.bytes_written::writebacks 4230272 +system.physmem.bytes_written::total 4230272 +system.physmem.num_reads::cpu.inst 1759 +system.physmem.num_reads::cpu.data 288616 +system.physmem.num_reads::total 290375 +system.physmem.num_writes::writebacks 66098 +system.physmem.num_writes::total 66098 +system.physmem.bw_read::cpu.inst 107620 +system.physmem.bw_read::cpu.data 17658310 +system.physmem.bw_read::total 17765930 +system.physmem.bw_inst_read::cpu.inst 107620 +system.physmem.bw_inst_read::total 107620 +system.physmem.bw_write::writebacks 4044055 +system.physmem.bw_write::total 4044055 +system.physmem.bw_total::writebacks 4044055 +system.physmem.bw_total::cpu.inst 107620 +system.physmem.bw_total::cpu.data 17658310 +system.physmem.bw_total::total 21809985 +system.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 673 +system.cpu.pwrStateResidencyTicks::ON 1046047111500 +system.cpu.numCycles 2092094223 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 639366787 +system.cpu.committedOps 785501035 +system.cpu.num_int_alu_accesses 682251400 +system.cpu.num_fp_alu_accesses 24239771 +system.cpu.num_func_calls 37261296 +system.cpu.num_conditional_control_insts 91575866 +system.cpu.num_int_insts 682251400 +system.cpu.num_fp_insts 24239771 +system.cpu.num_int_register_reads 1272307653 +system.cpu.num_int_register_writes 468423268 +system.cpu.num_fp_register_reads 28064643 +system.cpu.num_fp_register_writes 21684311 +system.cpu.num_cc_register_reads 3116296060 +system.cpu.num_cc_register_writes 351919006 +system.cpu.num_mem_refs 381221435 +system.cpu.num_load_insts 252240938 +system.cpu.num_store_insts 128980497 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 2092094223 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 137364860 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% +system.cpu.op_class::IntMult 5173441 0.66% 49.56% +system.cpu.op_class::IntDiv 0 0.00% 49.56% +system.cpu.op_class::FloatAdd 0 0.00% 49.56% +system.cpu.op_class::FloatCmp 0 0.00% 49.56% +system.cpu.op_class::FloatCvt 0 0.00% 49.56% +system.cpu.op_class::FloatMult 0 0.00% 49.56% +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% +system.cpu.op_class::FloatDiv 0 0.00% 49.56% +system.cpu.op_class::FloatMisc 0 0.00% 49.56% +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdAdd 0 0.00% 49.56% +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% +system.cpu.op_class::SimdAlu 0 0.00% 49.56% +system.cpu.op_class::SimdCmp 0 0.00% 49.56% +system.cpu.op_class::SimdCvt 0 0.00% 49.56% +system.cpu.op_class::SimdMisc 0 0.00% 49.56% +system.cpu.op_class::SimdMult 0 0.00% 49.56% +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% +system.cpu.op_class::SimdShift 0 0.00% 49.56% +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% +system.cpu.op_class::MemRead 245222568 31.09% 82.76% +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 788730744 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu.dcache.tags.replacements 778046 +system.cpu.dcache.tags.tagsinuse 4093.536872 +system.cpu.dcache.tags.total_refs 378510311 +system.cpu.dcache.tags.sampled_refs 782142 +system.cpu.dcache.tags.avg_refs 483.940654 +system.cpu.dcache.tags.warmup_cycle 1048273500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 +system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 +system.cpu.dcache.tags.occ_percent::total 0.999399 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 759367050 +system.cpu.dcache.tags.data_accesses 759367050 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 +system.cpu.dcache.ReadReq_hits::total 249613198 +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 +system.cpu.dcache.WriteReq_hits::total 128882154 +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 +system.cpu.dcache.SoftPFReq_hits::total 3481 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 +system.cpu.dcache.LoadLockedReq_hits::total 5739 +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 +system.cpu.dcache.StoreCondReq_hits::total 5739 +system.cpu.dcache.demand_hits::cpu.data 378495352 +system.cpu.dcache.demand_hits::total 378495352 +system.cpu.dcache.overall_hits::cpu.data 378498833 +system.cpu.dcache.overall_hits::total 378498833 +system.cpu.dcache.ReadReq_misses::cpu.data 712681 +system.cpu.dcache.ReadReq_misses::total 712681 +system.cpu.dcache.WriteReq_misses::cpu.data 69323 +system.cpu.dcache.WriteReq_misses::total 69323 +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 +system.cpu.dcache.SoftPFReq_misses::total 139 +system.cpu.dcache.demand_misses::cpu.data 782004 +system.cpu.dcache.demand_misses::total 782004 +system.cpu.dcache.overall_misses::cpu.data 782143 +system.cpu.dcache.overall_misses::total 782143 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 +system.cpu.dcache.ReadReq_miss_latency::total 20392265000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 +system.cpu.dcache.WriteReq_miss_latency::total 4205904500 +system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 +system.cpu.dcache.demand_miss_latency::total 24598169500 +system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 +system.cpu.dcache.overall_miss_latency::total 24598169500 +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 +system.cpu.dcache.ReadReq_accesses::total 250325879 +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 +system.cpu.dcache.WriteReq_accesses::total 128951477 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0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 1050141 +system.cpu.toL2Bus.reqLayer0.occupancy 887318500 +system.cpu.toL2Bus.reqLayer0.utilization 0.1 +system.cpu.toL2Bus.respLayer0.occupancy 15312000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 1173213000 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 546577 +system.membus.snoop_filter.hit_single_requests 256223 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.membus.trans_dist::ReadResp 224282 +system.membus.trans_dist::WritebackDirty 66098 +system.membus.trans_dist::CleanEvict 190103 +system.membus.trans_dist::ReadExReq 66093 +system.membus.trans_dist::ReadExResp 66093 +system.membus.trans_dist::ReadSharedReq 224282 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 +system.membus.pkt_count::total 836951 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 +system.membus.pkt_size::total 22814272 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 290376 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 290376 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 290376 +system.membus.reqLayer0.occupancy 811341000 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 1451875000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- |