diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/40.perlbmk/ref | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
7 files changed, 2696 insertions, 2696 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 7bcf4595f..f83552a37 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.559962 # Number of seconds simulated -sim_ticks 559961514500 # Number of ticks simulated -final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.561963 # Number of seconds simulated +sim_ticks 561962991000 # Number of ticks simulated +final_tick 561962991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216839 # Simulator instruction rate (inst/s) -host_op_rate 216839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130731039 # Simulator tick rate (ticks/s) -host_mem_usage 291560 # Number of bytes of host memory used -host_seconds 4283.31 # Real time elapsed on the host +host_inst_rate 333136 # Simulator instruction rate (inst/s) +host_op_rate 333136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 201563357 # Simulator tick rate (ticks/s) +host_mem_usage 305440 # Number of bytes of host memory used +host_seconds 2788.02 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,45 +25,45 @@ system.physmem.num_reads::cpu.data 288600 # Nu system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32985124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 332435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 32867645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33200080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 332435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 332435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7594294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7594294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7594294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 332435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 32867645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40794373 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18640576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17935 # Per bank write bursts -system.physmem.perBankRdBursts::1 18289 # Per bank write bursts -system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::0 17933 # Per bank write bursts +system.physmem.perBankRdBursts::1 18288 # Per bank write bursts +system.physmem.perBankRdBursts::2 18309 # Per bank write bursts system.physmem.perBankRdBursts::3 18250 # Per bank write bursts -system.physmem.perBankRdBursts::4 18167 # Per bank write bursts -system.physmem.perBankRdBursts::5 18240 # Per bank write bursts -system.physmem.perBankRdBursts::6 18320 # Per bank write bursts -system.physmem.perBankRdBursts::7 18299 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18226 # Per bank write bursts -system.physmem.perBankRdBursts::10 18219 # Per bank write bursts -system.physmem.perBankRdBursts::11 18391 # Per bank write bursts -system.physmem.perBankRdBursts::12 18259 # Per bank write bursts -system.physmem.perBankRdBursts::13 18042 # Per bank write bursts -system.physmem.perBankRdBursts::14 17977 # Per bank write bursts -system.physmem.perBankRdBursts::15 18101 # Per bank write bursts +system.physmem.perBankRdBursts::4 18165 # Per bank write bursts +system.physmem.perBankRdBursts::5 18241 # Per bank write bursts +system.physmem.perBankRdBursts::6 18322 # Per bank write bursts +system.physmem.perBankRdBursts::7 18300 # Per bank write bursts +system.physmem.perBankRdBursts::8 18229 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18214 # Per bank write bursts +system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::12 18260 # Per bank write bursts +system.physmem.perBankRdBursts::13 18047 # Per bank write bursts +system.physmem.perBankRdBursts::14 17980 # Per bank write bursts +system.physmem.perBankRdBursts::15 18105 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 559961438500 # Total gap between requests +system.physmem.totGap 561962908000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,20 +144,20 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 106018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216.046030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 139.156746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 265.673827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41726 39.36% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42732 40.31% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8674 8.18% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 811 0.76% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1515 1.43% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1173 1.11% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 577 0.54% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 518 0.49% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8292 7.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106018 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.199159 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.197763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.963064 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes @@ -219,92 +219,92 @@ system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471357 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471396 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.862526 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3046 75.36% 75.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 995 24.62% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2985206750 # Total ticks spent queuing -system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst +system.physmem.totQLat 2975536250 # Total ticks spent queuing +system.physmem.totMemAccLat 8436642500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10216.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28966.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 202789 # Number of row buffer hits during reads -system.physmem.writeRowHits 50437 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes -system.physmem.avgGap 1563256.04 # Average gap between requests -system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 201381 # Number of row buffer hits during reads +system.physmem.writeRowHits 50515 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes +system.physmem.avgGap 1568843.58 # Average gap between requests +system.physmem.pageHitRate 70.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 399311640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 217878375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136904600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.597962 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states -system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_0.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 110801606310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 239979977250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 389456417535 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.035628 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 398531952000 # Time in different power states +system.physmem_0.memoryStateTime::REF 18764980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 144660363000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 402093720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 219396375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134346200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.677886 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_1.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 111289898520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 239551650750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 389517237165 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.143857 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 397813996000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18764980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 145378777500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749069 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103970439 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513487 # Number of BTB hits +system.cpu.branchPred.lookups 125749002 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144241 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157248 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103981751 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513628 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.324261 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691097 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9450 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.315658 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537681 # DTB read hits -system.cpu.dtb.read_misses 198468 # DTB read misses +system.cpu.dtb.read_hits 237537715 # DTB read hits +system.cpu.dtb.read_misses 198475 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736149 # DTB read accesses -system.cpu.dtb.write_hits 98305023 # DTB write hits -system.cpu.dtb.write_misses 7212 # DTB write misses +system.cpu.dtb.read_accesses 237736190 # DTB read accesses +system.cpu.dtb.write_hits 98305031 # DTB write hits +system.cpu.dtb.write_misses 7188 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312235 # DTB write accesses -system.cpu.dtb.data_hits 335842704 # DTB hits -system.cpu.dtb.data_misses 205680 # DTB misses +system.cpu.dtb.write_accesses 98312219 # DTB write accesses +system.cpu.dtb.data_hits 335842746 # DTB hits +system.cpu.dtb.data_misses 205663 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048384 # DTB accesses -system.cpu.itb.fetch_hits 317138761 # ITB hits +system.cpu.dtb.data_accesses 336048409 # DTB accesses +system.cpu.itb.fetch_hits 317139351 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 317138881 # ITB accesses +system.cpu.itb.fetch_accesses 317139471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,67 +318,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1119923029 # number of cpu cycles simulated +system.cpu.numCycles 1123925982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 27043469 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.205788 # CPI: cycles per instruction -system.cpu.ipc 0.829333 # IPC: instructions per cycle -system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.210098 # CPI: cycles per instruction +system.cpu.ipc 0.826379 # IPC: instructions per cycle +system.cpu.tickCycles 1060172068 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63753914 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.699416 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 323503203 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.890165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999241 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 414.414040 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 905250250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.699416 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999194 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 949 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1244 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1647 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 225339131 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 323503178 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 323503178 # number of overall hits -system.cpu.dcache.overall_hits::total 323503178 # number of overall hits +system.cpu.dcache.tags.tag_accesses 649485188 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 649485188 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 225339151 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 225339151 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164052 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164052 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 323503203 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 323503203 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 323503203 # number of overall hits +system.cpu.dcache.overall_hits::total 323503203 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses -system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32445902750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 226051060 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137148 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137148 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849077 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849077 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849077 # number of overall misses +system.cpu.dcache.overall_misses::total 849077 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24941013500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24941013500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10047073750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10047073750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34988087250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34988087250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34988087250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34988087250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 226051080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 226051080 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 324352260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 324352260 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 324352280 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 324352280 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 324352280 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324352280 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -387,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32892.515616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65829.890706 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35033.006803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35033.006803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73257.165617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73257.165617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41207.201761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41207.201761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,12 +407,12 @@ system.cpu.dcache.writebacks::writebacks 91489 # nu system.cpu.dcache.writebacks::total 91489 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68454 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68454 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68137 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68449 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -421,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21915650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4445743250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26361393250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26361393250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23795842750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23795842750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4974141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4974141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28769984250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28769984250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28769984250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28769984250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -437,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33439.115072 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33439.115072 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72077.516628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72077.516628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10606 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10603 # number of replacements +system.cpu.icache.tags.tagsinuse 1687.326033 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 317127004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12346 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25686.619472 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.326033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823890 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823890 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1575 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 634289871 # Number of tag accesses -system.cpu.icache.tags.data_accesses 634289871 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 317126411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 317126411 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 317126411 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 317126411 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 317126411 # number of overall hits -system.cpu.icache.overall_hits::total 317126411 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses -system.cpu.icache.overall_misses::total 12350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 317138761 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28743.196728 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,66 +508,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12350 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12350 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12350 # 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miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68944.863014 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73471.647406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65316.891740 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.367628 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76632.277397 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80839.635286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80785.002779 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73227.706505 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73227.706505 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79057.313392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79057.313392 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,68 +646,68 @@ system.cpu.l2cache.demand_mshr_misses::total 291520 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164600500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13505684500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519774750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17025459250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164600500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17025459250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187160250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15168425250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15355585500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4046889000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4046889000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187160250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19215314250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19402474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187160250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19215314250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19402474500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310616 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367628 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56370.034247 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60848.750873 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367628 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64095.976027 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68340.092586 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68284.982768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60723.069998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60723.069998 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 723964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723963 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24693 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56605632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 884464 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884467 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884464 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884467 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 884464 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 533721000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19157750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1221759250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution @@ -729,9 +729,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.reqLayer0.occupancy 667013500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1552224500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 8cb1b2d37..492f134ce 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278180 # Number of seconds simulated -sim_ticks 278180234500 # Number of ticks simulated -final_tick 278180234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279669 # Number of seconds simulated +sim_ticks 279668927000 # Number of ticks simulated +final_tick 279668927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185742 # Simulator instruction rate (inst/s) -host_op_rate 185742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61337566 # Simulator tick rate (ticks/s) -host_mem_usage 305284 # Number of bytes of host memory used -host_seconds 4535.23 # Real time elapsed on the host +host_inst_rate 180963 # Simulator instruction rate (inst/s) +host_op_rate 180963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60079385 # Simulator tick rate (ticks/s) +host_mem_usage 306712 # Number of bytes of host memory used +host_seconds 4654.99 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18652864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175680 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18476288 # Number of bytes read from this memory +system.physmem.bytes_read::total 18652544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288692 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291446 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 631533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66421628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67053161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15341536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15341536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15341536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66421628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82394697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291451 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 630231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66064858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 66695089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 630231 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 630231 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15259872 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15259872 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15259872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 630231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66064858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 81954961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291446 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291451 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291446 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18633536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18652864 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18633664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652544 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17916 # Per bank write bursts -system.physmem.perBankRdBursts::1 18271 # Per bank write bursts +system.physmem.perBankRdBursts::0 17911 # Per bank write bursts +system.physmem.perBankRdBursts::1 18258 # Per bank write bursts system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18248 # Per bank write bursts -system.physmem.perBankRdBursts::4 18157 # Per bank write bursts -system.physmem.perBankRdBursts::5 18220 # Per bank write bursts -system.physmem.perBankRdBursts::6 18319 # Per bank write bursts -system.physmem.perBankRdBursts::7 18312 # Per bank write bursts -system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18223 # Per bank write bursts -system.physmem.perBankRdBursts::10 18210 # Per bank write bursts -system.physmem.perBankRdBursts::11 18385 # Per bank write bursts -system.physmem.perBankRdBursts::12 18240 # Per bank write bursts -system.physmem.perBankRdBursts::13 18040 # Per bank write bursts -system.physmem.perBankRdBursts::14 17965 # Per bank write bursts -system.physmem.perBankRdBursts::15 18111 # Per bank write bursts +system.physmem.perBankRdBursts::3 18250 # Per bank write bursts +system.physmem.perBankRdBursts::4 18158 # Per bank write bursts +system.physmem.perBankRdBursts::5 18224 # Per bank write bursts +system.physmem.perBankRdBursts::6 18321 # Per bank write bursts +system.physmem.perBankRdBursts::7 18307 # Per bank write bursts +system.physmem.perBankRdBursts::8 18228 # Per bank write bursts +system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::11 18393 # Per bank write bursts +system.physmem.perBankRdBursts::12 18247 # Per bank write bursts +system.physmem.perBankRdBursts::13 18043 # Per bank write bursts +system.physmem.perBankRdBursts::14 17966 # Per bank write bursts +system.physmem.perBankRdBursts::15 18104 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4187 # Per bank write bursts +system.physmem.perBankWrBursts::9 4180 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278180151500 # Total gap between requests +system.physmem.totGap 279668837500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291451 # Read request sizes (log2) +system.physmem.readPktSize::6 291446 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 211637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,118 +193,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100542 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.760100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.180809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.034024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36066 35.87% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42234 42.01% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10234 10.18% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 483 0.48% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 471 0.47% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 384 0.38% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 767 0.76% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1163 1.16% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8740 8.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100542 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.840049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.159268 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 778.757650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 100388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 228.091007 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.320458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.791024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35777 35.64% 35.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42525 42.36% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10061 10.02% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 470 0.47% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 508 0.51% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 391 0.39% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 492 0.49% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1510 1.50% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8654 8.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100388 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.235658 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.129419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 756.508896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.480346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.459004 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.856073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3075 76.02% 76.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 76.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 965 23.86% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 3369536750 # Total ticks spent queuing -system.physmem.totMemAccLat 8828580500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11573.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.482690 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.461191 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3072 75.96% 75.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 964 23.84% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 8 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads +system.physmem.totQLat 3601508250 # Total ticks spent queuing +system.physmem.totMemAccLat 9060589500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12369.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30323.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31119.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 66.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 206912 # Number of row buffer hits during reads -system.physmem.writeRowHits 50353 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.51 # Row buffer hit rate for writes -system.physmem.avgGap 776748.79 # Average gap between requests -system.physmem.pageHitRate 71.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378604800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206580000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136756400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 206952 # Number of row buffer hits during reads +system.physmem.writeRowHits 50458 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes +system.physmem.avgGap 780916.48 # Average gap between requests +system.physmem.pageHitRate 71.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378650160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206604750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136467800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79832621385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96879153000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 196819477185 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.526603 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 160651755000 # Time in different power states -system.physmem_0.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_0.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79892908290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97718574000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 197816101560 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.327829 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 162042939000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9338680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108238852500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108285182250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 381470040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 208143375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 380207520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 207454500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79968075615 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96760333500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 196836972210 # Total energy per rank (pJ) -system.physmem_1.averagePower 707.589494 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 160452636750 # Time in different power states -system.physmem_1.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80233432560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 97419868500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 197857002360 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.474077 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 161543146250 # Time in different power states +system.physmem_1.memoryStateTime::REF 9338680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108437970750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108784975000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192516083 # Number of BP lookups -system.cpu.branchPred.condPredicted 125602202 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11889251 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155393318 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126938973 # Number of BTB hits +system.cpu.branchPred.lookups 192995150 # Number of BP lookups +system.cpu.branchPred.condPredicted 125739221 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11883936 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 145375032 # Number of BTB lookups +system.cpu.branchPred.BTBHits 127081867 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.688823 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28938957 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.416570 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 29018342 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244535558 # DTB read hits -system.cpu.dtb.read_misses 309848 # DTB read misses +system.cpu.dtb.read_hits 244533779 # DTB read hits +system.cpu.dtb.read_misses 309591 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244845406 # DTB read accesses -system.cpu.dtb.write_hits 135688740 # DTB write hits -system.cpu.dtb.write_misses 31438 # DTB write misses +system.cpu.dtb.read_accesses 244843370 # DTB read accesses +system.cpu.dtb.write_hits 135671849 # DTB write hits +system.cpu.dtb.write_misses 31346 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135720178 # DTB write accesses -system.cpu.dtb.data_hits 380224298 # DTB hits -system.cpu.dtb.data_misses 341286 # DTB misses +system.cpu.dtb.write_accesses 135703195 # DTB write accesses +system.cpu.dtb.data_hits 380205628 # DTB hits +system.cpu.dtb.data_misses 340937 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380565584 # DTB accesses -system.cpu.itb.fetch_hits 196974389 # ITB hits -system.cpu.itb.fetch_misses 282 # ITB misses +system.cpu.dtb.data_accesses 380546565 # DTB accesses +system.cpu.itb.fetch_hits 197011138 # ITB hits +system.cpu.itb.fetch_misses 297 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 196974671 # ITB accesses +system.cpu.itb.fetch_accesses 197011435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,138 +317,137 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556360470 # number of cpu cycles simulated +system.cpu.numCycles 559337855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202471372 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648161036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192516083 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155877930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341537101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24247434 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6713 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 196974389 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6735628 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556139161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202154435 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1649182914 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192995150 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156100209 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 344813807 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24235896 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6519 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 197011138 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7083229 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 559092875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.175515 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236974879 42.61% 42.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30241040 5.44% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22122460 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36446378 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67887841 12.21% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21615986 3.89% 74.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19300231 3.47% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3499506 0.63% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118050840 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 239653225 42.86% 42.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30449692 5.45% 48.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22058642 3.95% 52.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36467190 6.52% 58.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 68017058 12.17% 70.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21431579 3.83% 74.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299153 3.45% 78.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3537365 0.63% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118178971 21.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556139161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346028 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962398 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168673381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 88906441 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273702922 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12739464 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12116953 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15366288 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7026 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1584564231 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12116953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176662049 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61884123 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13864 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278433046 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27029126 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538057639 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6904 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2373775 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17934465 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6832008 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1026949046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1768413823 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728631636 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39782186 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 559092875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345042 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.948456 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168803167 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 91739479 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273671215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12767829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12111185 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15522167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 6976 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1584668893 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12111185 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176688622 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61751221 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14050 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278532777 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29995020 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538585292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9438 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2658750 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20386888 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7267964 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1027382191 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1769248125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1729530138 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39717986 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 387981888 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 388415033 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 99 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9559876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372392006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175420299 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40717360 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11158065 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304772774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015651643 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8789932 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462366805 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427709940 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556139161 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.901646 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9495582 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372551032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175434243 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40723012 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11258595 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304972518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1016009395 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790765 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462565445 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427723515 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 559092875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.817246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.904787 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 196811929 35.39% 35.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93156725 16.75% 52.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91633615 16.48% 68.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59891442 10.77% 79.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56837976 10.22% 89.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29662833 5.33% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17038989 3.06% 98.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7191857 1.29% 99.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3913795 0.70% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 200119998 35.79% 35.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93029621 16.64% 52.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91384631 16.35% 68.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59843024 10.70% 79.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56522593 10.11% 89.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29852885 5.34% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17077557 3.05% 97.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7239227 1.29% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4023339 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556139161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 559092875 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2464081 10.47% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15568992 66.16% 76.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5500305 23.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2463450 10.43% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15566876 65.90% 76.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5592414 23.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579437623 57.05% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181925 1.30% 58.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579702610 57.06% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7931 0.00% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13180646 1.30% 58.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826544 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339801 0.33% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued @@ -473,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276912765 27.26% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138943776 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 277022873 27.27% 86.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138927710 13.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015651643 # Type of FU issued -system.cpu.iq.rate 1.825528 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23533378 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023171 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548957351 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1725871307 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940019268 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808406 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41313833 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425264 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002821720 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36362025 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50456367 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1016009395 # Type of FU issued +system.cpu.iq.rate 1.816450 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23622740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023251 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2552720615 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1726495098 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940123896 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70804555 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41088088 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34423394 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1003270759 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36360100 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50476055 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 134881409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1145791 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45978 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77119099 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 135040435 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1174528 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45615 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77133043 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2647 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4470 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2509 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4123 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12116953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60932529 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 189663 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479247252 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16168 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372392006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175420299 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26629 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 174749 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45978 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11882583 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16645 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11899228 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976172370 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244845576 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39479273 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12111185 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60760024 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 216464 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479434002 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17901 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372551032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175434243 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 87 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21559 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 205996 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45615 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11877701 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16644 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11894345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976302878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244843546 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39706517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174474397 # number of nop insts executed -system.cpu.iew.exec_refs 380566182 # number of memory reference insts executed -system.cpu.iew.exec_branches 129102826 # Number of branches executed -system.cpu.iew.exec_stores 135720606 # Number of stores executed -system.cpu.iew.exec_rate 1.754568 # Inst execution rate -system.cpu.iew.wb_sent 974964146 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974444532 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556292557 # num instructions producing a value -system.cpu.iew.wb_consumers 832443785 # num instructions consuming a value +system.cpu.iew.exec_nop 174461395 # number of nop insts executed +system.cpu.iew.exec_refs 380547191 # number of memory reference insts executed +system.cpu.iew.exec_branches 129259483 # Number of branches executed +system.cpu.iew.exec_stores 135703645 # Number of stores executed +system.cpu.iew.exec_rate 1.745462 # Inst execution rate +system.cpu.iew.wb_sent 975066188 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974547290 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556173359 # num instructions producing a value +system.cpu.iew.wb_consumers 831980820 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751463 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668264 # average fanout of values written-back +system.cpu.iew.wb_rate 1.742323 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668493 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543416365 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543601549 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11882488 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483294798 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.921369 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.600805 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11877174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 486379014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.909185 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.596644 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205311965 42.48% 42.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102147195 21.14% 63.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51748026 10.71% 74.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25735966 5.33% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21537447 4.46% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9139527 1.89% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10425967 2.16% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6656382 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50592323 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 208258289 42.82% 42.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102386957 21.05% 63.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51676822 10.62% 74.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25636051 5.27% 79.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21554637 4.43% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9250657 1.90% 86.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10396507 2.14% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6664753 1.37% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50554341 10.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483294798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 486379014 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -596,330 +594,346 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50592323 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50554341 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1902085330 # The number of ROB reads -system.cpu.rob.rob_writes 3016853590 # The number of ROB writes -system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 221309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1905392712 # The number of ROB reads +system.cpu.rob.rob_writes 3017093514 # The number of ROB writes +system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 244980 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660461 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660461 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237238749 # number of integer regfile reads -system.cpu.int_regfile_writes 705818584 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691517 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411333 # number of floating regfile writes +system.cpu.cpi 0.663995 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.663995 # CPI: Total CPI of All Threads +system.cpu.ipc 1.506034 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.506034 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237178642 # number of integer regfile reads +system.cpu.int_regfile_writes 705781417 # number of integer regfile writes +system.cpu.fp_regfile_reads 36689419 # number of floating regfile reads +system.cpu.fp_regfile_writes 24410667 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777239 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.040110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289873961 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781335 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 370.998305 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.040110 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777209 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.895157 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289903947 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 371.050930 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 374093250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.895157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2501 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 253 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585528663 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585528663 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192492893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192492893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97381046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97381046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289873939 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289873939 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289873939 # number of overall hits -system.cpu.dcache.overall_hits::total 289873939 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1579549 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1579549 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 920154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 920154 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2499703 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2499703 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2499703 # number of overall misses -system.cpu.dcache.overall_misses::total 2499703 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79817656500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79817656500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57409075211 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57409075211 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137226731711 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137226731711 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137226731711 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137226731711 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194072442 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194072442 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 585486411 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585486411 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192496951 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192496951 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97406971 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97406971 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289903922 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289903922 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289903922 # number of overall hits +system.cpu.dcache.overall_hits::total 289903922 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554376 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554376 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 894229 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 894229 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2448605 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2448605 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2448605 # number of overall misses +system.cpu.dcache.overall_misses::total 2448605 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84529453750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84529453750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62304618080 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62304618080 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 100250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 100250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 146834071830 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 146834071830 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 146834071830 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 146834071830 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194051327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194051327 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292373642 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292373642 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292373642 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292373642 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008139 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008139 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009361 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009361 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008550 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008550 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008550 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008550 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50531.928101 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50531.928101 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62390.725043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62390.725043 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54897.214473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54897.214473 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21908 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 55699 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 467 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.912206 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 107.943798 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 26 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 26 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292352527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292352527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292352527 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292352527 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009097 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038462 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038462 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008376 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008376 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008376 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008376 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54381.599915 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54381.599915 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69674.119359 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69674.119359 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 100250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 100250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59966.418361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59966.418361 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21964 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 69527 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 515 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.034985 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 135.003883 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks -system.cpu.dcache.writebacks::total 91488 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867045 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867045 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851323 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 851323 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1718368 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1718368 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1718368 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1718368 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712504 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712504 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68831 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68831 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781335 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781335 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21874292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21874292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5221022246 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5221022246 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27095314246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27095314246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27095314246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27095314246 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 91524 # number of writebacks +system.cpu.dcache.writebacks::total 91524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 841911 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 841911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 825390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 825390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1667301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1667301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1667301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1667301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68839 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68839 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781304 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781304 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781304 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781304 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23794966500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23794966500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5675142998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5675142998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29470109498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29470109498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29470109498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29470109498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038462 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.038462 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30700.588348 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30700.588348 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75852.773402 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75852.773402 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33398.084818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33398.084818 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82440.811139 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82440.811139 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4662 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.102487 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 196966072 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 4665 # number of replacements +system.cpu.icache.tags.tagsinuse 1651.262169 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 197002801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6374 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30901.486037 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 30907.248353 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.102487 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808156 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808156 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1712 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1651.262169 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.835938 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 393955150 # Number of tag accesses -system.cpu.icache.tags.data_accesses 393955150 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 196966072 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 196966072 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 196966072 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 196966072 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 196966072 # number of overall hits -system.cpu.icache.overall_hits::total 196966072 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8316 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8316 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8316 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8316 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8316 # number of overall misses -system.cpu.icache.overall_misses::total 8316 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 334444749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 334444749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 334444749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 334444749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 334444749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 334444749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 196974388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 196974388 # 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number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 197002801 # number of overall hits +system.cpu.icache.overall_hits::total 197002801 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8337 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8337 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8337 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8337 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8337 # number of overall misses +system.cpu.icache.overall_misses::total 8337 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 359956749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 359956749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 359956749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 359956749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 359956749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 359956749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 197011138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 197011138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 197011138 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 197011138 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 197011138 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 197011138 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40217.021284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40217.021284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40217.021284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40217.021284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43175.812522 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43175.812522 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43175.812522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43175.812522 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 938 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.545455 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.533333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -930,103 +944,103 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224828 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66624 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66624 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288706 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291452 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2746 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288706 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291452 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 165368000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13488499500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13653867500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4314074750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4314074750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165368000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17802574250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17967942250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165368000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17802574250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17967942250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.369999 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.369999 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60221.412964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60736.572527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60730.280481 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64752.562890 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64752.562890 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224819 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66628 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66628 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288692 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288692 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291447 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 185539750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15158114250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15343654000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4753161750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4753161750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 185539750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19911276000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20096815750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 185539750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19911276000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20096815750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312752 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370007 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370007 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67346.551724 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68260.115327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68248.920243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71338.802756 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71338.802756 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 718879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 718841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68839 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666883 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55860672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56268608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56268992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879198 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 879204 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879198 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879204 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879198 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531087000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 879204 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531126000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10054750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10103500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1207495250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1213595000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224827 # Transaction distribution -system.membus.trans_dist::ReadResp 224827 # Transaction distribution +system.membus.trans_dist::ReadReq 224818 # Transaction distribution +system.membus.trans_dist::ReadResp 224818 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66624 # Transaction distribution -system.membus.trans_dist::ReadExResp 66624 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649585 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649585 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 66628 # Transaction distribution +system.membus.trans_dist::ReadExResp 66628 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358134 # Request fanout histogram +system.membus.snoop_fanout::samples 358129 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 358129 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358134 # Request fanout histogram -system.membus.reqLayer0.occupancy 959207000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2708819750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.snoop_fanout::total 358129 # Request fanout histogram +system.membus.reqLayer0.occupancy 682357500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1548216750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 8acd26381..eff48cf7e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.286250 # Number of seconds simulated -sim_ticks 1286249820000 # Number of ticks simulated -final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1286249817500 # Number of ticks simulated +final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1681245 # Simulator instruction rate (inst/s) -host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2328806930 # Simulator tick rate (ticks/s) -host_mem_usage 298588 # Number of bytes of host memory used -host_seconds 552.32 # Real time elapsed on the host +host_inst_rate 1412500 # Simulator instruction rate (inst/s) +host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1956550284 # Simulator tick rate (ticks/s) +host_mem_usage 303116 # Number of bytes of host memory used +host_seconds 657.41 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,30 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 224031 # Transaction distribution -system.membus.trans_dist::ReadResp 224031 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 357362 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 357362 # Request fanout histogram -system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572499640 # number of cpu cycles simulated +system.cpu.numCycles 2572499635 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572499640 # Number of busy cycles +system.cpu.num_busy_cycles 2572499635 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.dcache.tags.replacements 776432 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits +system.cpu.dcache.overall_hits::total 335031269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses +system.cpu.dcache.overall_misses::total 780528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks +system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id @@ -181,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -199,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -219,34 +304,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257900 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy @@ -284,17 +369,17 @@ system.cpu.l2cache.demand_misses::total 290679 # nu system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses system.cpu.l2cache.overall_misses::total 290679 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11537659000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11649615000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15003355000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15115311000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15003355000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15115311000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11648595000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11761628000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 113033000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15147615000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15260648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 113033000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses) @@ -319,17 +404,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.369493 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,17 +436,17 @@ system.cpu.l2cache.demand_mshr_misses::total 290679 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8875123000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8961243000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11541043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11627163000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11541043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11627163000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses @@ -373,127 +458,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks -system.cpu.dcache.writebacks::total 91660 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution @@ -523,5 +499,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 9252000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 357362 # Request fanout histogram +system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 7a6d5db32..3406c4e55 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541786 # Number of seconds simulated -sim_ticks 541786101000 # Number of ticks simulated -final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.545057 # Number of seconds simulated +sim_ticks 545056655500 # Number of ticks simulated +final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115987 # Simulator instruction rate (inst/s) -host_op_rate 142796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98087491 # Simulator tick rate (ticks/s) -host_mem_usage 309428 # Number of bytes of host memory used -host_seconds 5523.50 # Real time elapsed on the host +host_inst_rate 182072 # Simulator instruction rate (inst/s) +host_op_rate 224154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154902851 # Simulator tick rate (ticks/s) +host_mem_usage 321108 # Number of bytes of host memory used +host_seconds 3518.70 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429248 # Number of bytes read from this memory +system.physmem.bytes_read::total 18594112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164864 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287957 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290529 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 302471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33811619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34114090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7761160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7761160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7761160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33811619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41875251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290533 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290533 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18594112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18289 # Per bank write bursts -system.physmem.perBankRdBursts::1 18137 # Per bank write bursts -system.physmem.perBankRdBursts::2 18222 # Per bank write bursts +system.physmem.perBankRdBursts::0 18287 # Per bank write bursts +system.physmem.perBankRdBursts::1 18141 # Per bank write bursts +system.physmem.perBankRdBursts::2 18224 # Per bank write bursts system.physmem.perBankRdBursts::3 18184 # Per bank write bursts -system.physmem.perBankRdBursts::4 18266 # Per bank write bursts -system.physmem.perBankRdBursts::5 18308 # Per bank write bursts -system.physmem.perBankRdBursts::6 18094 # Per bank write bursts -system.physmem.perBankRdBursts::7 17914 # Per bank write bursts -system.physmem.perBankRdBursts::8 17939 # Per bank write bursts -system.physmem.perBankRdBursts::9 17962 # Per bank write bursts -system.physmem.perBankRdBursts::10 18018 # Per bank write bursts -system.physmem.perBankRdBursts::11 18110 # Per bank write bursts +system.physmem.perBankRdBursts::4 18267 # Per bank write bursts +system.physmem.perBankRdBursts::5 18318 # Per bank write bursts +system.physmem.perBankRdBursts::6 18100 # Per bank write bursts +system.physmem.perBankRdBursts::7 17916 # Per bank write bursts +system.physmem.perBankRdBursts::8 17940 # Per bank write bursts +system.physmem.perBankRdBursts::9 17966 # Per bank write bursts +system.physmem.perBankRdBursts::10 18025 # Per bank write bursts +system.physmem.perBankRdBursts::11 18111 # Per bank write bursts system.physmem.perBankRdBursts::12 18143 # Per bank write bursts -system.physmem.perBankRdBursts::13 18270 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18266 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4101 # Per bank write bursts -system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18269 # Per bank write bursts +system.physmem.perBankRdBursts::14 18078 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts +system.physmem.perBankWrBursts::2 4136 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4225 # Per bank write bursts -system.physmem.perBankWrBursts::5 4225 # Per bank write bursts +system.physmem.perBankWrBursts::5 4223 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4090 # Per bank write bursts -system.physmem.perBankWrBursts::11 4094 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4138 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541786012500 # Total gap between requests +system.physmem.totGap 545056561000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290529 # Read request sizes (log2) +system.physmem.readPktSize::6 290533 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,97 +193,95 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.549530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads -system.physmem.totQLat 2707676000 # Total ticks spent queuing -system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.481417 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.460113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads +system.physmem.totQLat 2737356250 # Total ticks spent queuing +system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing -system.physmem.readRowHits 194608 # Number of row buffer hits during reads -system.physmem.writeRowHits 50098 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing +system.physmem.readRowHits 193898 # Number of row buffer hits during reads +system.physmem.writeRowHits 50093 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 1519195.16 # Average gap between requests -system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.117148 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem.avgGap 1528348.80 # Average gap between requests +system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.076638 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 387358600750 # Time in different power states +system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 139494961250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.890615 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_1.actEnergy 424962720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231874500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105917359815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 234122034750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 377638135065 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.846209 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 388771820250 # Time in different power states +system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138081006000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 156937341 # Number of BP lookups -system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups -system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits +system.cpu.branchPred.lookups 155213668 # Number of BP lookups +system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12879317 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90304208 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82854286 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.750194 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19341274 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,75 +400,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083572202 # number of cpu cycles simulated +system.cpu.numCycles 1090113311 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 22623250 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691350 # CPI: cycles per instruction -system.cpu.ipc 0.591244 # IPC: instructions per cycle -system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778221 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy +system.cpu.cpi 1.701560 # CPI: cycles per instruction +system.cpu.ipc 0.587696 # IPC: instructions per cycle +system.cpu.tickCycles 1030411592 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59701719 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778141 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378456482 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.813067 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249631239 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249631239 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits -system.cpu.dcache.overall_hits::total 378446269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses -system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 378445004 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378445004 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378445004 # number of overall hits +system.cpu.dcache.overall_hits::total 378445004 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713665 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713665 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 851377 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851377 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851377 # number of overall misses +system.cpu.dcache.overall_misses::total 851377 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24698082718 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24698082718 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34888334468 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34888334468 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34888334468 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34888334468 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250344904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250344904 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379296381 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379296381 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -479,14 +477,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.389627 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.389627 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40978.713858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40978.713858 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,99 +495,99 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 750 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69140 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69140 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69140 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69140 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712915 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782237 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23543649027 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23543649027 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28589180277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28589180277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589180277 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28589180277 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33024.482620 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33024.482620 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23590 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23596 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.064969 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064969 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits -system.cpu.icache.overall_hits::total 289921723 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses -system.cpu.icache.overall_misses::total 25342 # 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number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 583983749 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583983749 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291953853 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291953853 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291953853 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291953853 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291953853 # number of overall hits +system.cpu.icache.overall_hits::total 291953853 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses +system.cpu.icache.overall_misses::total 25348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499968245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499968245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499968245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499968245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499968245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499968245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291979201 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19724.169362 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19724.169362 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19724.169362 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257753 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994072 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2793 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29433 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 25342 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782237 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 807585 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311247 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.304058 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359758 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368154 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359796 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,116 +723,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2577 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221866 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224443 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2577 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290534 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55914048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57536256 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 899005 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 899005 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224438 # Transaction distribution -system.membus.trans_dist::ReadResp 224438 # Transaction distribution +system.membus.trans_dist::ReadReq 224442 # Transaction distribution +system.membus.trans_dist::ReadResp 224442 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824384 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356627 # Request fanout histogram +system.membus.snoop_fanout::samples 356631 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 356631 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356627 # Request fanout histogram -system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.snoop_fanout::total 356631 # Request fanout histogram +system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 5cb40d175..c41e8c5e9 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.408037 # Number of seconds simulated -sim_ticks 408037199500 # Number of ticks simulated -final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.409399 # Number of seconds simulated +sim_ticks 409399480000 # Number of ticks simulated +final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90640 # Simulator instruction rate (inst/s) -host_op_rate 111590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57729920 # Simulator tick rate (ticks/s) -host_mem_usage 318440 # Number of bytes of host memory used -host_seconds 7068.04 # Real time elapsed on the host +host_inst_rate 93383 # Simulator instruction rate (inst/s) +host_op_rate 114967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59675446 # Simulator tick rate (ticks/s) +host_mem_usage 317532 # Number of bytes of host memory used +host_seconds 6860.43 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory -system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315254 # Number of read requests accepted -system.physmem.writeReqs 66324 # Number of write requests accepted -system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19893 # Per bank write bursts -system.physmem.perBankRdBursts::1 19507 # Per bank write bursts -system.physmem.perBankRdBursts::2 19696 # Per bank write bursts -system.physmem.perBankRdBursts::3 19811 # Per bank write bursts -system.physmem.perBankRdBursts::4 19755 # Per bank write bursts -system.physmem.perBankRdBursts::5 20266 # Per bank write bursts -system.physmem.perBankRdBursts::6 19606 # Per bank write bursts -system.physmem.perBankRdBursts::7 19431 # Per bank write bursts -system.physmem.perBankRdBursts::8 19468 # Per bank write bursts -system.physmem.perBankRdBursts::9 19384 # Per bank write bursts -system.physmem.perBankRdBursts::10 19414 # Per bank write bursts -system.physmem.perBankRdBursts::11 19672 # Per bank write bursts -system.physmem.perBankRdBursts::12 19624 # Per bank write bursts -system.physmem.perBankRdBursts::13 19992 # Per bank write bursts -system.physmem.perBankRdBursts::14 19481 # Per bank write bursts -system.physmem.perBankRdBursts::15 19957 # Per bank write bursts -system.physmem.perBankWrBursts::0 4278 # Per bank write bursts -system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7025088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12938560 # Number of bytes read from this memory +system.physmem.bytes_read::total 20195840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244864 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66326 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66326 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 567153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17159494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31603753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49330400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 567153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 567153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10368513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10368513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10368513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 567153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17159494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31603753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59698913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315560 # Number of read requests accepted +system.physmem.writeReqs 66326 # Number of write requests accepted +system.physmem.readBursts 315560 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66326 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20177344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20195840 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19474 # Per bank write bursts +system.physmem.perBankRdBursts::2 19822 # Per bank write bursts +system.physmem.perBankRdBursts::3 19845 # Per bank write bursts +system.physmem.perBankRdBursts::4 19720 # Per bank write bursts +system.physmem.perBankRdBursts::5 20103 # Per bank write bursts +system.physmem.perBankRdBursts::6 19622 # Per bank write bursts +system.physmem.perBankRdBursts::7 19424 # Per bank write bursts +system.physmem.perBankRdBursts::8 19577 # Per bank write bursts +system.physmem.perBankRdBursts::9 19501 # Per bank write bursts +system.physmem.perBankRdBursts::10 19475 # Per bank write bursts +system.physmem.perBankRdBursts::11 19731 # Per bank write bursts +system.physmem.perBankRdBursts::12 19558 # Per bank write bursts +system.physmem.perBankRdBursts::13 20043 # Per bank write bursts +system.physmem.perBankRdBursts::14 19546 # Per bank write bursts +system.physmem.perBankRdBursts::15 19920 # Per bank write bursts +system.physmem.perBankWrBursts::0 4269 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts system.physmem.perBankWrBursts::2 4141 # Per bank write bursts -system.physmem.perBankWrBursts::3 4152 # Per bank write bursts -system.physmem.perBankWrBursts::4 4250 # Per bank write bursts -system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankWrBursts::3 4150 # Per bank write bursts +system.physmem.perBankWrBursts::4 4244 # Per bank write bursts +system.physmem.perBankWrBursts::5 4227 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::12 4097 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4151 # Per bank write bursts +system.physmem.perBankWrBursts::15 4154 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 408037145000 # Total gap between requests +system.physmem.totGap 409399425500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315254 # Read request sizes (log2) +system.physmem.readPktSize::6 315560 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66324 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66326 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 122658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1337 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -197,113 +197,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads -system.physmem.totQLat 9384520258 # Total ticks spent queuing -system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.677557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.806703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.419690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53973 39.50% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57563 42.13% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14775 10.81% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1288 0.94% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1420 1.04% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1465 1.07% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1207 0.88% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1190 0.87% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3757 2.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136638 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.784581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.732770 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 517.054396 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4014 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.20% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 5 0.12% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.418691 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.384198 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.147646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3405 84.41% 84.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.17% 84.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 450 11.16% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 75 1.86% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 34 0.84% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 21 0.52% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 13 0.32% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 12 0.30% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads +system.physmem.totQLat 9487812639 # Total ticks spent queuing +system.physmem.totMemAccLat 15399143889 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1576355000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30094.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48844.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.47 # Data bus utilization in percentage system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 218395 # Number of row buffer hits during reads -system.physmem.writeRowHits 26455 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing +system.physmem.readRowHits 218399 # Number of row buffer hits during reads +system.physmem.writeRowHits 26454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes -system.physmem.avgGap 1069341.38 # Average gap between requests -system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.765171 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states -system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem.avgGap 1072046.17 # Average gap between requests +system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 517640760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282442875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1231518600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216464400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96784987680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 160736987250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 286509617805 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.839198 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 266762765318 # Time in different power states +system.physmem_0.memoryStateTime::REF 13670540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128960598682 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.696391 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states -system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_1.actEnergy 515168640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 281094000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1226955600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96280028955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 161179933500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 286435482375 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.658112 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 267502793659 # Time in different power states +system.physmem_1.memoryStateTime::REF 13670540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states +system.physmem_1.memoryStateTime::ACT 128220707341 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233958621 # Number of BP lookups -system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits +system.cpu.branchPred.lookups 234006176 # Number of BP lookups +system.cpu.branchPred.condPredicted 161868409 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514584 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121529948 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108213709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.042833 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25036783 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300149 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -422,84 +418,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 816074400 # number of cpu cycles simulated +system.cpu.numCycles 818798961 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 84078294 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200783068 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234006176 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133250492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718844861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063585 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3349 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370656305 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652882 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 818460793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.833394 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.163540 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136795118 16.71% 16.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223180654 27.27% 43.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98074923 11.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360410098 44.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 818460793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285792 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.466518 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119991092 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159658898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662986 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38629701 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518116 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25135087 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13824 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248129900 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966537 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518116 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176998470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78894904 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 210510 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464956548 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81882245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190637892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25457774 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24955109 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267146 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41533192 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1699566 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225425199 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812490436 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358169789 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876588 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 350646969 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 108140115 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366205100 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236096667 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1646330 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5328678 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168639452 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379819992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.242727 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 260810349 31.87% 31.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227739162 27.83% 59.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216495712 26.45% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97269955 11.88% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16145606 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -507,44 +503,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 818460793 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64512117 19.12% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18144 0.01% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155573719 46.11% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116674794 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456371749 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -568,88 +564,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322115143 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215585851 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued -system.cpu.iq.rate 1.246337 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017122920 # Type of FU issued +system.cpu.iq.rate 1.242213 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504924384 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565805 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960122 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113964162 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18388 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116171 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065787 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22375 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518116 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35326355 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168657365 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366205100 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236096667 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 109 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 45517 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18388 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437362 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784555 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221917 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974750423 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42372497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed -system.cpu.iew.exec_branches 150614661 # Number of branches executed -system.cpu.iew.exec_stores 194464042 # Number of stores executed -system.cpu.iew.exec_rate 1.194456 # Inst execution rate -system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536684839 # num instructions producing a value -system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value +system.cpu.iew.exec_nop 5553 # number of nop insts executed +system.cpu.iew.exec_refs 497763737 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613650 # Number of branches executed +system.cpu.iew.exec_stores 194466026 # Number of stores executed +system.cpu.iew.exec_rate 1.190464 # Inst execution rate +system.cpu.iew.wb_sent 963723367 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960423035 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536681402 # num instructions producing a value +system.cpu.iew.wb_consumers 893284482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172966 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357409752 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500908 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 767640271 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.027474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 430932808 56.14% 56.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172476946 22.47% 78.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566678 9.58% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31624021 4.12% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8540196 1.11% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14250754 1.86% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269409 0.95% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618976 0.86% 97.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360483 2.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 767640271 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -695,382 +691,382 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1888745890 # The number of ROB reads -system.cpu.rob.rob_writes 2343137518 # The number of ROB writes -system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1891410858 # The number of ROB reads +system.cpu.rob.rob_writes 2343104087 # The number of ROB writes +system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 338168 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads -system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995816176 # number of integer regfile reads -system.cpu.int_regfile_writes 567918829 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads +system.cpu.cpi 1.278077 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.278077 # CPI: Total CPI of All Threads +system.cpu.ipc 0.782426 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.782426 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995803851 # number of integer regfile reads +system.cpu.int_regfile_writes 567906934 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads -system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes -system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794434058 # number of cc regfile reads +system.cpu.cc_regfile_writes 384899317 # number of cc regfile writes +system.cpu.misc_regfile_reads 715816288 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756166 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756182 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.932940 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414226912 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756694 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.262202 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.932940 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839344268 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839344268 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286295518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286295518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127916671 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127916671 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3177 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3177 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits -system.cpu.dcache.overall_hits::total 414238542 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414212189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414212189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414215366 # number of overall hits +system.cpu.dcache.overall_hits::total 414215366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1034806 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1034806 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses -system.cpu.dcache.overall_misses::total 4045534 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4066295 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4066295 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4066942 # number of overall misses +system.cpu.dcache.overall_misses::total 4066942 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35316006617 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35316006617 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10004118304 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10004118304 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 202750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 202750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45320124921 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45320124921 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45320124921 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45320124921 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289327007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289327007 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3824 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3824 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418278484 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418278484 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418282308 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418282308 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169195 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169195 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9667.626883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9667.626883 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11145.311622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11143.538541 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 349732 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5194 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 67.333847 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks -system.cpu.dcache.writebacks::total 735128 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735277 # number of writebacks +system.cpu.dcache.writebacks::total 735277 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996280 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 996280 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313945 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 313945 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1310225 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1310225 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1310225 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1310225 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28726022904 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28726022904 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167626 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167626 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # 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Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169874 # number of replacements +system.cpu.icache.tags.tagsinuse 510.641329 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 365482216 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5170384 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.687635 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 247770250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.641329 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997346 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997346 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745313375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745313375 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364900028 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364900028 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364900028 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364900028 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364900028 # number of overall hits -system.cpu.icache.overall_hits::total 364900028 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171791 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171791 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171791 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171791 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171791 # number of overall misses -system.cpu.icache.overall_misses::total 5171791 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41611685167 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.075480 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9.750000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 746482947 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746482947 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365482251 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365482251 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365482251 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41654200685 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41654200685 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41654200685 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370656273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370656273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370656273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370656273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370656273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370656273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013959 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013959 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013959 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013959 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013959 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013959 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8050.642360 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8050.642360 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8050.642360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8050.642360 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76485 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.358280 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169737 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169737 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33819004202 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6541.726243 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6541.726243 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1079,145 +1075,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks -system.cpu.l2cache.writebacks::total 66324 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 66326 # number of writebacks +system.cpu.l2cache.writebacks::total 66326 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1303 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1318 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1445 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1445 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2748 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2748 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2763 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108380 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 112008 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202241 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202241 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109767 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113395 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 109767 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202241 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 315636 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 238098541 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7611970750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7850069291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17087057356 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 219516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 219516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114561754 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114561754 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238098541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7726532504 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7964631045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238098541 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7726532504 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25051688401 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053236 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014305 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039817 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7206252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7206251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 248818 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 317003 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 720844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720844 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340787 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16589486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330904640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223486144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554390784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 248834 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8911208 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.027922 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.164749 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 8662390 97.21% 97.21% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 248818 2.79% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8911208 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5066472000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756152507 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4138701196 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 313877 # Transaction distribution -system.membus.trans_dist::ReadResp 313877 # Transaction distribution -system.membus.trans_dist::Writeback 66324 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 314173 # Transaction distribution +system.membus.trans_dist::ReadResp 314173 # Transaction distribution +system.membus.trans_dist::Writeback 66326 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697478 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697478 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24440704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24440704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381592 # Request fanout histogram +system.membus.snoop_fanout::samples 381902 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381902 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381592 # Request fanout histogram -system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381902 # Request fanout histogram +system.membus.reqLayer0.occupancy 746879857 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1648874306 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 4817ec8a9..ba52b772d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1395078 # Simulator instruction rate (inst/s) -host_op_rate 1717525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 861727739 # Simulator tick rate (ticks/s) -host_mem_usage 309420 # Number of bytes of host memory used -host_seconds 459.22 # Real time elapsed on the host +host_inst_rate 1601804 # Simulator instruction rate (inst/s) +host_op_rate 1972032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 989420456 # Simulator tick rate (ticks/s) +host_mem_usage 309588 # Number of bytes of host memory used +host_seconds 399.96 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram -system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::3 643377898 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 1022670352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index c5e3a18fc..e078716d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.043695 # Number of seconds simulated -sim_ticks 1043695084000 # Number of ticks simulated -final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1043695077500 # Number of ticks simulated +final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 894518 # Simulator instruction rate (inst/s) -host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1460200235 # Simulator tick rate (ticks/s) -host_mem_usage 317628 # Number of bytes of host memory used -host_seconds 714.76 # Real time elapsed on the host +host_inst_rate 877071 # Simulator instruction rate (inst/s) +host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1431720298 # Simulator tick rate (ticks/s) +host_mem_usage 317788 # Number of bytes of host memory used +host_seconds 728.98 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087390168 # number of cpu cycles simulated +system.cpu.numCycles 2087390155 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366786 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087390167.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364859 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 256932 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy @@ -484,17 +484,17 @@ system.cpu.l2cache.demand_misses::total 289712 # nu system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses system.cpu.l2cache.overall_misses::total 289712 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92118500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11536392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11628510500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436883000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3436883000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92118500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14973275000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15065393500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92118500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14973275000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15065393500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92997000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647316500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11740313500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469929500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3469929500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 92997000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15117246000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 92997000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15117246000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses) @@ -519,17 +519,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.365636 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 289712 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70811000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8873960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8944771000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70811000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11517680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11588491000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70811000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11517680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution @@ -598,19 +598,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) @@ -638,9 +636,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |