diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/long/se/40.perlbmk/ref | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | 960 | ||||
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt | 952 |
2 files changed, 955 insertions, 957 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index ba9298aae..3373b2092 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.555533 # Number of seconds simulated -sim_ticks 555532734000 # Number of ticks simulated -final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.559967 # Number of seconds simulated +sim_ticks 559966999500 # Number of ticks simulated +final_tick 559966999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 316770 # Simulator instruction rate (inst/s) -host_op_rate 316770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189468265 # Simulator tick rate (ticks/s) -host_mem_usage 247360 # Number of bytes of host memory used -host_seconds 2932.06 # Real time elapsed on the host +host_inst_rate 393705 # Simulator instruction rate (inst/s) +host_op_rate 393705 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 237364888 # Simulator tick rate (ticks/s) +host_mem_usage 245892 # Number of bytes of host memory used +host_seconds 2359.10 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18657152 # Number of bytes read from this memory -system.physmem.bytes_read::total 18657152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186688 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 18657216 # Number of bytes read from this memory +system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 291518 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 291519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33584253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33584253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 336052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 336052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7682197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7682197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7682197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33584253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41266450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291518 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 33318421 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33318421 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7621363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7621363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7621363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33318421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40939784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17088 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18639936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17280 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 267 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 270 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17939 # Per bank write bursts -system.physmem.perBankRdBursts::1 18284 # Per bank write bursts -system.physmem.perBankRdBursts::2 18304 # Per bank write bursts -system.physmem.perBankRdBursts::3 18254 # Per bank write bursts +system.physmem.perBankRdBursts::0 17935 # Per bank write bursts +system.physmem.perBankRdBursts::1 18289 # Per bank write bursts +system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::3 18248 # Per bank write bursts system.physmem.perBankRdBursts::4 18163 # Per bank write bursts -system.physmem.perBankRdBursts::5 18248 # Per bank write bursts -system.physmem.perBankRdBursts::6 18324 # Per bank write bursts +system.physmem.perBankRdBursts::5 18239 # Per bank write bursts +system.physmem.perBankRdBursts::6 18320 # Per bank write bursts system.physmem.perBankRdBursts::7 18299 # Per bank write bursts -system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts system.physmem.perBankRdBursts::9 18226 # Per bank write bursts -system.physmem.perBankRdBursts::10 18216 # Per bank write bursts -system.physmem.perBankRdBursts::11 18389 # Per bank write bursts -system.physmem.perBankRdBursts::12 18256 # Per bank write bursts -system.physmem.perBankRdBursts::13 18039 # Per bank write bursts -system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18104 # Per bank write bursts +system.physmem.perBankRdBursts::10 18219 # Per bank write bursts +system.physmem.perBankRdBursts::11 18391 # Per bank write bursts +system.physmem.perBankRdBursts::12 18259 # Per bank write bursts +system.physmem.perBankRdBursts::13 18042 # Per bank write bursts +system.physmem.perBankRdBursts::14 17977 # Per bank write bursts +system.physmem.perBankRdBursts::15 18106 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -69,7 +69,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4190 # Per bank write bursts +system.physmem.perBankWrBursts::9 4189 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -78,14 +78,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 555532658500 # Total gap between requests +system.physmem.totGap 559966923500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291518 # Read request sizes (log2) +system.physmem.readPktSize::6 291519 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,137 +189,113 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 217.968119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 139.907625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 270.030152 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 40113 38.17% 38.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 44071 41.94% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8455 8.05% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 717 0.68% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 543 0.52% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 672 0.64% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1241 1.18% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1153 1.10% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8114 7.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105079 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.423096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.196398 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 785.521839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 104630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.912664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.833166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 269.609760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39535 37.79% 37.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43904 41.96% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8672 8.29% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 695 0.66% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 728 0.70% 89.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 763 0.73% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1332 1.27% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 808 0.77% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8193 7.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104630 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.196437 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.192949 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.958027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.485163 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.463667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3065 75.79% 75.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 975 24.11% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 2419619750 # Total ticks spent queuing -system.physmem.totMemAccLat 7880576000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8307.68 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471357 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.863386 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads +system.physmem.totQLat 2990654250 # Total ticks spent queuing +system.physmem.totMemAccLat 8451573000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10268.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27057.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29018.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 202343 # Number of row buffer hits during reads -system.physmem.writeRowHits 50484 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes -system.physmem.avgGap 1550896.45 # Average gap between requests -system.physmem.pageHitRate 70.64 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275459224750 # Time in different power states -system.physmem.memoryStateTime::REF 18550220000 # Time in different power states +system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing +system.physmem.readRowHits 202814 # Number of row buffer hits during reads +system.physmem.writeRowHits 50461 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes +system.physmem.avgGap 1563271.35 # Average gap between requests +system.physmem.pageHitRate 70.76 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275670988500 # Time in different power states +system.physmem.memoryStateTime::REF 18698420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states +system.physmem.memoryStateTime::ACT 265594606500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 396060840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 398223000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 216104625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 217284375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136803200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1134198000 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 393989400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 396952920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 214974375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 216591375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1136974800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1134400800 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215557200 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 36284230320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 36284230320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 106733795895 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 107171521695 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 239689369500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 239305399500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 384672802860 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 384726414090 # Total energy per rank (pJ) -system.physmem.averagePower::0 692.448078 # Core power per rank (mW) -system.physmem.averagePower::1 692.544584 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 224874 # Transaction distribution -system.membus.trans_dist::ReadResp 224874 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66644 # Transaction distribution -system.membus.trans_dist::ReadExResp 66644 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358201 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358201 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358201 # Request fanout histogram -system.membus.reqLayer0.occupancy 954482500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2723745500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 125108663 # Number of BP lookups -system.cpu.branchPred.condPredicted 80505376 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103330871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82874854 # Number of BTB hits +system.physmem.writeEnergy::1 215550720 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 36574109520 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 36574109520 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 108415975050 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 108760602465 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 240876668250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 240574363500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 387829129875 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 387872571300 # Total energy per rank (pJ) +system.physmem.averagePower::0 692.596540 # Core power per rank (mW) +system.physmem.averagePower::1 692.674119 # Core power per rank (mW) +system.cpu.branchPred.lookups 125749069 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103970439 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513487 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18690215 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.324261 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691097 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9450 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537573 # DTB read hits -system.cpu.dtb.read_misses 198412 # DTB read misses +system.cpu.dtb.read_hits 237537681 # DTB read hits +system.cpu.dtb.read_misses 198468 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237735985 # DTB read accesses -system.cpu.dtb.write_hits 98305055 # DTB write hits -system.cpu.dtb.write_misses 7206 # DTB write misses +system.cpu.dtb.read_accesses 237736149 # DTB read accesses +system.cpu.dtb.write_hits 98305023 # DTB write hits +system.cpu.dtb.write_misses 7212 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312261 # DTB write accesses -system.cpu.dtb.data_hits 335842628 # DTB hits -system.cpu.dtb.data_misses 205618 # DTB misses +system.cpu.dtb.write_accesses 98312235 # DTB write accesses +system.cpu.dtb.data_hits 335842704 # DTB hits +system.cpu.dtb.data_misses 205680 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048246 # DTB accesses -system.cpu.itb.fetch_hits 315070347 # ITB hits +system.cpu.dtb.data_accesses 336048384 # DTB accesses +system.cpu.itb.fetch_hits 317138761 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 315070467 # ITB accesses +system.cpu.itb.fetch_accesses 317138881 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -333,71 +309,188 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1111065468 # number of cpu cycles simulated +system.cpu.numCycles 1119933999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23870771 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.196252 # CPI: cycles per instruction -system.cpu.ipc 0.835945 # IPC: instructions per cycle -system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58517266 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 10608 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.446779 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 315057996 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25510.768907 # Average number of references to valid blocks. +system.cpu.cpi 1.205800 # CPI: cycles per instruction +system.cpu.ipc 0.829325 # IPC: instructions per cycle +system.cpu.tickCycles 1060170405 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59763594 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 776532 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.890193 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 225339131 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 323503178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 323503178 # number of overall hits +system.cpu.dcache.overall_hits::total 323503178 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 711929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 849082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses +system.cpu.dcache.overall_misses::total 849082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23415653250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23415653250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9042894000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9042894000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32458547250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32458547250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32458547250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32458547250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 324352260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 324352260 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks +system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 312 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68142 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 68454 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 68454 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69011 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 780628 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 780628 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21914188000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21914188000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4452805750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4452805750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26366993750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26366993750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 10606 # number of replacements +system.cpu.icache.tags.tagsinuse 1687.447542 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.446779 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447542 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 630153044 # Number of tag accesses -system.cpu.icache.tags.data_accesses 630153044 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 315057996 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 315057996 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 315057996 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 315057996 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 315057996 # number of overall hits -system.cpu.icache.overall_hits::total 315057996 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses -system.cpu.icache.overall_misses::total 12351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 334498250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 334498250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 334498250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 334498250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 334498250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 334498250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 315070347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 315070347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 315070347 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 315070347 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 315070347 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 315070347 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 634289871 # Number of tag accesses +system.cpu.icache.tags.data_accesses 634289871 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 317126411 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 317126411 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 317126411 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 317126411 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 317126411 # number of overall hits +system.cpu.icache.overall_hits::total 317126411 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses +system.cpu.icache.overall_misses::total 12350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333735500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333735500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333735500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333735500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333735500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333735500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 317138761 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 317138761 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 317138761 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27082.685613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27082.685613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27082.685613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27082.685613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27023.117409 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27023.117409 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,132 +499,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308545750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 308545750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308545750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 308545750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308545750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 308545750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12350 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12350 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12350 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307779500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 307779500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307779500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 307779500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307779500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 307779500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24981.438750 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69010 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884470 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884470 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884470 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19151250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1221989250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 258739 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.629306 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 523854 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291475 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.797252 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258740 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32601.453126 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2865.774027 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.855280 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907466 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994923 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2865.906217 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2681 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29449 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7436245 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7436245 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 499096 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 499096 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7436223 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 499092 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 499092 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.inst 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 501462 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501462 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 501462 # number of overall hits -system.cpu.l2cache.overall_hits::total 501462 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 501458 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 501458 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 501458 # number of overall hits +system.cpu.l2cache.overall_hits::total 501458 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 224875 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66644 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66644 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 291519 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291519 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 291519 # number of overall misses -system.cpu.l2cache.overall_misses::total 291519 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15924584250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15924584250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4349858250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4349858250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20274442500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20274442500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20274442500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20274442500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 723971 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 723971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66645 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 291520 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 291520 # number of overall misses +system.cpu.l2cache.overall_misses::total 291520 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16507068000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16507068000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4360106750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4360106750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20867174750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20867174750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20867174750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20867174750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 723967 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69010 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69010 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 792981 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792981 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792981 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792981 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.310613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.965715 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965715 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367624 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.367624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70815.271818 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70815.271818 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65270.065572 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65270.065572 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69547.585235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69547.585235 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 792978 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792978 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792978 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792978 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.310615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.310615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.965716 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367627 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367627 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73405.527515 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73405.527515 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65422.863681 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65422.863681 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71580.593956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71580.593956 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,153 +608,89 @@ system.cpu.l2cache.writebacks::writebacks 66683 # n system.cpu.l2cache.writebacks::total 66683 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224875 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66644 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66644 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 291519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 291519 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13108086750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13108086750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3516385750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3516385750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16624472500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16624472500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16624472500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16624472500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965715 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965715 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367624 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58290.546971 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58290.546971 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52763.725917 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.725917 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66645 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 291520 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 291520 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13668599500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13668599500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3526847250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3526847250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17195446750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17195446750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 776534 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.879782 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322859767 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.588726 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879782 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648198336 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648198336 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 224695720 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224695720 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 322859767 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322859767 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 322859767 # number of overall hits -system.cpu.dcache.overall_hits::total 322859767 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 849086 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses -system.cpu.dcache.overall_misses::total 849086 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22831828750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22831828750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9022635000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9022635000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 31854463750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31854463750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 31854463750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31854463750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 225407653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225407653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 323708853 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323708853 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 323708853 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323708853 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32070.193052 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32070.193052 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65785.181513 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65785.181513 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37516.180634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37516.180634 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks -system.cpu.dcache.writebacks::total 91489 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 313 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68143 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 68456 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 68456 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69010 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69010 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21330988000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21330988000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4442556750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4442556750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25773544750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25773544750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25773544750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25773544750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 29975.250836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29975.250836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64375.550645 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64375.550645 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56605824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 884467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884467 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 884467 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1222199250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224874 # Transaction distribution +system.membus.trans_dist::ReadResp 224874 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66645 # Transaction distribution +system.membus.trans_dist::ReadExResp 66645 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649721 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649721 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22924928 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358202 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358202 # Request fanout histogram +system.membus.reqLayer0.occupancy 975509000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2745284750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 12718eef7..531c5ebad 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.537826 # Number of seconds simulated -sim_ticks 537826498500 # Number of ticks simulated -final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541781 # Number of seconds simulated +sim_ticks 541781076000 # Number of ticks simulated +final_tick 541781076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182992 # Simulator instruction rate (inst/s) -host_op_rate 225287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153620567 # Simulator tick rate (ticks/s) -host_mem_usage 318916 # Number of bytes of host memory used -host_seconds 3501.01 # Real time elapsed on the host +host_inst_rate 140173 # Simulator instruction rate (inst/s) +host_op_rate 172571 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118539448 # Simulator tick rate (ticks/s) +host_mem_usage 261676 # Number of bytes of host memory used +host_seconds 4570.47 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 18593856 # Number of bytes read from this memory +system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290531 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 34319870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34319870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7808084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7808084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7808084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34319870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42127954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18573248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18291 # Per bank write bursts -system.physmem.perBankRdBursts::1 18140 # Per bank write bursts -system.physmem.perBankRdBursts::2 18223 # Per bank write bursts -system.physmem.perBankRdBursts::3 18183 # Per bank write bursts -system.physmem.perBankRdBursts::4 18268 # Per bank write bursts +system.physmem.perBankRdBursts::0 18288 # Per bank write bursts +system.physmem.perBankRdBursts::1 18139 # Per bank write bursts +system.physmem.perBankRdBursts::2 18224 # Per bank write bursts +system.physmem.perBankRdBursts::3 18182 # Per bank write bursts +system.physmem.perBankRdBursts::4 18264 # Per bank write bursts system.physmem.perBankRdBursts::5 18315 # Per bank write bursts -system.physmem.perBankRdBursts::6 18099 # Per bank write bursts -system.physmem.perBankRdBursts::7 17920 # Per bank write bursts -system.physmem.perBankRdBursts::8 17939 # Per bank write bursts -system.physmem.perBankRdBursts::9 17964 # Per bank write bursts -system.physmem.perBankRdBursts::10 18020 # Per bank write bursts +system.physmem.perBankRdBursts::6 18098 # Per bank write bursts +system.physmem.perBankRdBursts::7 17914 # Per bank write bursts +system.physmem.perBankRdBursts::8 17936 # Per bank write bursts +system.physmem.perBankRdBursts::9 17963 # Per bank write bursts +system.physmem.perBankRdBursts::10 18015 # Per bank write bursts system.physmem.perBankRdBursts::11 18110 # Per bank write bursts -system.physmem.perBankRdBursts::12 18148 # Per bank write bursts -system.physmem.perBankRdBursts::13 18270 # Per bank write bursts -system.physmem.perBankRdBursts::14 18079 # Per bank write bursts -system.physmem.perBankRdBursts::15 18262 # Per bank write bursts +system.physmem.perBankRdBursts::12 18146 # Per bank write bursts +system.physmem.perBankRdBursts::13 18271 # Per bank write bursts +system.physmem.perBankRdBursts::14 18075 # Per bank write bursts +system.physmem.perBankRdBursts::15 18267 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts +system.physmem.perBankWrBursts::1 4101 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts system.physmem.perBankWrBursts::3 4147 # Per bank write bursts system.physmem.perBankWrBursts::4 4225 # Per bank write bursts @@ -70,22 +70,22 @@ system.physmem.perBankWrBursts::6 4171 # Pe system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4091 # Per bank write bursts +system.physmem.perBankWrBursts::10 4090 # Per bank write bursts system.physmem.perBankWrBursts::11 4094 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 537826410500 # Total gap between requests +system.physmem.totGap 541780987500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290531 # Read request sizes (log2) +system.physmem.readPktSize::6 290529 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -141,7 +141,7 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 980 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see @@ -149,9 +149,9 @@ system.physmem.wrQLenPdf::20 4008 # Wh system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see @@ -189,117 +189,91 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 111520 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.445337 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.546078 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.289579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46919 42.07% 42.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43694 39.18% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8696 7.80% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 722 0.65% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1258 1.13% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1255 1.13% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 576 0.52% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 502 0.45% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7898 7.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111520 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.543798 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.072613 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.664819 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.488645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.467122 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3028 75.57% 75.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 3341982750 # Total ticks spent queuing -system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst +system.physmem.totQLat 2702187250 # Total ticks spent queuing +system.physmem.totMemAccLat 8143568500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9311.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28061.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing -system.physmem.readRowHits 194589 # Number of row buffer hits during reads -system.physmem.writeRowHits 50052 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes -system.physmem.avgGap 1508083.78 # Average gap between requests -system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states -system.physmem.memoryStateTime::REF 17958980000 # Time in different power states +system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing +system.physmem.readRowHits 194639 # Number of row buffer hits during reads +system.physmem.writeRowHits 50105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.80 # Row buffer hit rate for writes +system.physmem.avgGap 1519181.07 # Average gap between requests +system.physmem.pageHitRate 68.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 263887343000 # Time in different power states +system.physmem.memoryStateTime::REF 18091060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states +system.physmem.memoryStateTime::ACT 259796939500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 422248680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 421734600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 230393625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 230113125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1134268200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1129057800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 215634960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212524560 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 35127764880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 35127764880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 108230961600 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 107988304905 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 227752503750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 227965360500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 373113775695 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 373074860370 # Total energy per rank (pJ) -system.physmem.averagePower::0 693.752260 # Core power per rank (mW) -system.physmem.averagePower::1 693.679903 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 224439 # Transaction distribution -system.membus.trans_dist::ReadResp 224439 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::ReadExReq 66092 # Transaction distribution -system.membus.trans_dist::ReadExResp 66092 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356629 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356629 # Request fanout histogram -system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 154837020 # Number of BP lookups -system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits +system.physmem.actEnergy::0 421530480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 421462440 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 230001750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 229964625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1134174600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1128987600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 215628480 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 212505120 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 35386113360 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 35386113360 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 105979651695 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 105556941405 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 232100586000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 232471384500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 375467686365 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 375407359050 # Total energy per rank (pJ) +system.physmem.averagePower::0 693.032096 # Core power per rank (mW) +system.physmem.averagePower::1 692.920745 # Core power per rank (mW) +system.cpu.branchPred.lookups 156937341 # Number of BP lookups +system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups +system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -385,69 +359,194 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1075652997 # number of cpu cycles simulated +system.cpu.numCycles 1083562152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.678989 # CPI: cycles per instruction -system.cpu.ipc 0.595596 # IPC: instructions per cycle -system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked -system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 23597 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. +system.cpu.cpi 1.691335 # CPI: cycles per instruction +system.cpu.ipc 0.591249 # IPC: instructions per cycle +system.cpu.tickCycles 1029140125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54422027 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778221 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.644165 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 752182250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.644165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 249632505 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 128813764 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 378446269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 378446269 # number of overall hits +system.cpu.dcache.overall_hits::total 378446269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 713747 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 137713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 851460 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses +system.cpu.dcache.overall_misses::total 851460 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23050728217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23050728217 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9196889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9196889000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32247617217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32247617217 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32247617217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32247617217 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 379297729 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 379297729 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37873.320199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37873.320199 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks +system.cpu.dcache.writebacks::total 91420 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 752 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68391 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 69143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 69143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21540338778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21540338778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529678750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529678750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26070017528 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26070017528 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26070017528 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26070017528 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 23590 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.180354 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289921724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11440.816227 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses -system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits -system.cpu.icache.overall_hits::total 289999264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses -system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180354 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 579919473 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579919473 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289921724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289921724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289921724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289921724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289921724 # number of overall hits +system.cpu.icache.overall_hits::total 289921724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses +system.cpu.icache.overall_misses::total 25342 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 481750746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 481750746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 481750746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 481750746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 481750746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 481750746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289947066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289947066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289947066 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289947066 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289947066 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289947066 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19009.973404 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19009.973404 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,136 +555,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 428895254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25342 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25342 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25342 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429966254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 429966254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429966254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 429966254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429966254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 429966254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16966.547786 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16966.547786 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38571746 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224928725 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 257750 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32583.011088 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257749 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32583.074549 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2866.114553 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087467 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906888 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2860.585859 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.488690 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087298 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907058 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994357 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2831 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29389 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7553321 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7553321 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 513976 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 513976 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 513866 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 517207 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517207 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 517207 # number of overall hits -system.cpu.l2cache.overall_hits::total 517207 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 224469 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224469 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66092 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66092 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 290561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses -system.cpu.l2cache.overall_misses::total 290561 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16739408750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16739408750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits::cpu.inst 517097 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 517097 # number of overall hits +system.cpu.l2cache.overall_hits::total 517097 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 224471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66091 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 290562 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses +system.cpu.l2cache.overall_misses::total 290562 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16093224000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16093224000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4428044750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4428044750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20521268750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20521268750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20521268750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20521268750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 807768 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 807768 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 807768 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.303975 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.303975 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953392 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.953392 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69322 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 807659 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 807659 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.304022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,169 +662,101 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 29 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 29 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 29 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224440 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66092 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66092 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13904175250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13904175250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3593710250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3593710250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497885500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17497885500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497885500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17497885500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953392 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 32 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 32 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 32 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13281416250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13281416250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3575940250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3575940250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16857356500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16857356500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16857356500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16857356500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 778324 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378453595 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782420 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.696218 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 745524250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.650508 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1577 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759392478 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759392478 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 249628224 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249628224 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 128813893 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813893 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 378442117 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378442117 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 378442117 # number of overall hits -system.cpu.dcache.overall_hits::total 378442117 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 713850 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713850 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 137584 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137584 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 851434 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses -system.cpu.dcache.overall_misses::total 851434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23700601220 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23700601220 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9183787250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9183787250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32884388470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32884388470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32884388470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32884388470 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks -system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22188801525 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1224341972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224438 # Transaction distribution +system.membus.trans_dist::ReadResp 224438 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66091 # Transaction distribution +system.membus.trans_dist::ReadExResp 66091 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 356627 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 356627 # Request fanout histogram +system.membus.reqLayer0.occupancy 983533000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2738969000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |