diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/40.perlbmk/ref | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/40.perlbmk/ref')
4 files changed, 1373 insertions, 1363 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 0912a812f..1c7f4cd18 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.646278 # Number of seconds simulated -sim_ticks 646278143000 # Number of ticks simulated -final_tick 646278143000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.644314 # Number of seconds simulated +sim_ticks 644314104000 # Number of ticks simulated +final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208687 # Simulator instruction rate (inst/s) -host_op_rate 208687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73980757 # Simulator tick rate (ticks/s) -host_mem_usage 229204 # Number of bytes of host memory used -host_seconds 8735.76 # Real time elapsed on the host +host_inst_rate 127860 # Simulator instruction rate (inst/s) +host_op_rate 127860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45189117 # Simulator tick rate (ticks/s) +host_mem_usage 230524 # Number of bytes of host memory used +host_seconds 14258.17 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 191680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94465088 # Number of bytes read from this memory -system.physmem.bytes_read::total 94656768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 191680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 191680 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94463936 # Number of bytes read from this memory +system.physmem.bytes_read::total 94654784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 190848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 190848 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476017 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2982 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475999 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1478981 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 296591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146167852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146464443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 296591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 296591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6624813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6624813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6624813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 296591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146167852 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153089256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 296203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146611622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146907826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 296203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 296203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6645007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6645007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6645007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 296203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146611622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153552833 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 528353322 # DTB read hits -system.cpu.dtb.read_misses 626455 # DTB read misses +system.cpu.dtb.read_hits 526091283 # DTB read hits +system.cpu.dtb.read_misses 609189 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 528979777 # DTB read accesses -system.cpu.dtb.write_hits 292227311 # DTB write hits -system.cpu.dtb.write_misses 54391 # DTB write misses +system.cpu.dtb.read_accesses 526700472 # DTB read accesses +system.cpu.dtb.write_hits 292251681 # DTB write hits +system.cpu.dtb.write_misses 54656 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 292281702 # DTB write accesses -system.cpu.dtb.data_hits 820580633 # DTB hits -system.cpu.dtb.data_misses 680846 # DTB misses +system.cpu.dtb.write_accesses 292306337 # DTB write accesses +system.cpu.dtb.data_hits 818342964 # DTB hits +system.cpu.dtb.data_misses 663845 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 821261479 # DTB accesses -system.cpu.itb.fetch_hits 401438115 # ITB hits -system.cpu.itb.fetch_misses 852 # ITB misses +system.cpu.dtb.data_accesses 819006809 # DTB accesses +system.cpu.itb.fetch_hits 402493704 # ITB hits +system.cpu.itb.fetch_misses 819 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 401438967 # ITB accesses +system.cpu.itb.fetch_accesses 402494523 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +67,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1292556287 # number of cpu cycles simulated +system.cpu.numCycles 1288628209 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 394747270 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 256599366 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27590844 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 323468940 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262010178 # Number of BTB hits +system.cpu.BPredUnit.lookups 393523603 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 256622136 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27591372 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 324682531 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262034039 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57787448 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7273 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421195062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3322341707 # Number of instructions fetch has processed -system.cpu.fetch.Branches 394747270 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 319797626 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638354680 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162914776 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 98034186 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9284 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 401438115 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8412038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1292428872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.570619 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.140035 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57682078 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6792 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421081938 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3322079900 # Number of instructions fetch has processed +system.cpu.fetch.Branches 393523603 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 319716117 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638226273 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162822813 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 94445154 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8938 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402493704 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9540813 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1288505558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.578243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.138227 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 654074192 50.61% 50.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60911661 4.71% 55.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43750931 3.39% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72637907 5.62% 64.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126293368 9.77% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45669959 3.53% 77.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41606825 3.22% 80.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7021986 0.54% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 240462043 18.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 650279285 50.47% 50.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 59669001 4.63% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43760756 3.40% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72624833 5.64% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127388332 9.89% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46848563 3.64% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41619525 3.23% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7020509 0.54% 81.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 239294754 18.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1292428872 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305400 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.570365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 452871377 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80658879 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 614115225 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9960097 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134823294 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 34649231 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12312 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3231646719 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46688 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134823294 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 482927898 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33597059 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 26321 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 592678255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48376045 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3142025529 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 359 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42577598 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2088048291 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3654580534 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3537192548 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117387986 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1288505558 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305382 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.577997 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 453351036 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 77522549 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 613342023 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9559025 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134730925 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33522574 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12306 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3228150524 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46600 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134730925 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 483601779 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 32079469 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 591314469 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46752919 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3136805366 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 365 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7001 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40828800 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2086363185 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3649389993 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3531980340 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117409653 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 703079221 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4247 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 139 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 143016934 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 739120183 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 360450433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67842482 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9359459 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2647443516 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 119 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2196739037 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17945817 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 824288886 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 711675229 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1292428872 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.699698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805222 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 701394115 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4228 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 134 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 140886298 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 736269341 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 360318998 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68834783 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9382400 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2642228655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2193185137 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17944949 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 819070745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 708820503 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 83 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1288505558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.702115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805670 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470829232 36.43% 36.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 219635474 16.99% 53.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252835921 19.56% 72.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120249084 9.30% 82.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106312849 8.23% 90.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 78591497 6.08% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21017973 1.63% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17286986 1.34% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5669856 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470226956 36.49% 36.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 215277039 16.71% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 253569254 19.68% 72.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121312750 9.41% 82.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106354397 8.25% 90.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 77759673 6.03% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21099202 1.64% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17230121 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5676166 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1292428872 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1288505558 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1140834 3.16% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24068551 66.72% 69.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10866173 30.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1175249 3.24% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24027488 66.23% 69.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11077412 30.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1257954367 57.26% 57.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29223285 1.33% 58.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254700 0.38% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204654 0.33% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 590393009 26.88% 86.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 303689578 13.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1255595425 57.25% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16675 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29225002 1.33% 58.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589172005 26.86% 86.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 303713925 13.85% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2196739037 # Type of FU issued -system.cpu.iq.rate 1.699531 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36075558 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5585448865 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3387972537 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2024033733 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 154479456 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 83833082 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75371142 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2153745375 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 79066468 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69378492 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2193185137 # Type of FU issued +system.cpu.iq.rate 1.701953 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36280149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016542 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5574611120 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3377500690 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2021426713 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 154489810 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 83871907 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75374894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2150389693 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 79072841 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67211668 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 228050157 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2255425 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 75959 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 149655537 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 225199315 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24267 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76315 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 149524102 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4423 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4398 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134823294 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4267155 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 460832 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3006059047 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2702146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 739120183 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 360450433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 119 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 451591 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5232 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 75959 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27593158 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31610 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27624768 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2105923301 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 528979869 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90815736 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134730925 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4001327 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 199767 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3000725705 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2706866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 736269341 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 360318998 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195059 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4865 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76315 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27584399 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31784 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27616183 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2101081456 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526700571 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 92103681 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358615412 # number of nop insts executed -system.cpu.iew.exec_refs 821261997 # number of memory reference insts executed -system.cpu.iew.exec_branches 282350798 # Number of branches executed -system.cpu.iew.exec_stores 292282128 # Number of stores executed -system.cpu.iew.exec_rate 1.629270 # Inst execution rate -system.cpu.iew.wb_sent 2102194150 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2099404875 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185212780 # num instructions producing a value -system.cpu.iew.wb_consumers 1754721967 # num instructions consuming a value +system.cpu.iew.exec_nop 358496928 # number of nop insts executed +system.cpu.iew.exec_refs 819007361 # number of memory reference insts executed +system.cpu.iew.exec_branches 281208089 # Number of branches executed +system.cpu.iew.exec_stores 292306790 # Number of stores executed +system.cpu.iew.exec_rate 1.630479 # Inst execution rate +system.cpu.iew.wb_sent 2099578580 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2096801607 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1184710151 # num instructions producing a value +system.cpu.iew.wb_consumers 1754117094 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.624227 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675442 # average fanout of values written-back +system.cpu.iew.wb_rate 1.627158 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675388 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 980398495 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 975019383 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27578641 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1157605578 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.735468 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.494432 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27579200 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1153774633 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.741231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495587 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 541345066 46.76% 46.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227581476 19.66% 66.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119272186 10.30% 76.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56742028 4.90% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 51019590 4.41% 86.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24162950 2.09% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18255180 1.58% 89.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15605334 1.35% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103621768 8.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 537356152 46.57% 46.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227667410 19.73% 66.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119239977 10.33% 76.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56780365 4.92% 81.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50766064 4.40% 85.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24581833 2.13% 88.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18432159 1.60% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15672614 1.36% 91.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103278059 8.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1157605578 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1153774633 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103621768 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103278059 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4037733499 # The number of ROB reads -system.cpu.rob.rob_writes 6113598006 # The number of ROB writes -system.cpu.timesIdled 3575 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 127415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4028867151 # The number of ROB reads +system.cpu.rob.rob_writes 6102747283 # The number of ROB writes +system.cpu.timesIdled 3543 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 122651 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.709010 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.709010 # CPI: Total CPI of All Threads -system.cpu.ipc 1.410417 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.410417 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2681938582 # number of integer regfile reads -system.cpu.int_regfile_writes 1518871452 # number of integer regfile writes -system.cpu.fp_regfile_reads 81943465 # number of floating regfile reads -system.cpu.fp_regfile_writes 54033824 # number of floating regfile writes +system.cpu.cpi 0.706855 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.706855 # CPI: Total CPI of All Threads +system.cpu.ipc 1.414716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.414716 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2678227479 # number of integer regfile reads +system.cpu.int_regfile_writes 1517398403 # number of integer regfile writes +system.cpu.fp_regfile_reads 81948895 # number of floating regfile reads +system.cpu.fp_regfile_writes 54035615 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8410 # number of replacements -system.cpu.icache.tagsinuse 1670.523326 # Cycle average of tags in use -system.cpu.icache.total_refs 401426768 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10133 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39615.786835 # Average number of references to valid blocks. +system.cpu.icache.replacements 8420 # number of replacements +system.cpu.icache.tagsinuse 1668.242053 # Cycle average of tags in use +system.cpu.icache.total_refs 402482315 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39688.621931 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1670.523326 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.815685 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.815685 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 401426768 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 401426768 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 401426768 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 401426768 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 401426768 # number of overall hits -system.cpu.icache.overall_hits::total 401426768 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11347 # number of overall misses -system.cpu.icache.overall_misses::total 11347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204562000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204562000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204562000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204562000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204562000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204562000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 401438115 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 401438115 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 401438115 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 401438115 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 401438115 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 401438115 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1668.242053 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.814571 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.814571 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402482315 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402482315 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402482315 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402482315 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402482315 # number of overall hits +system.cpu.icache.overall_hits::total 402482315 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11389 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11389 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11389 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11389 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11389 # number of overall misses +system.cpu.icache.overall_misses::total 11389 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 178670000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 178670000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 178670000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 178670000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 178670000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 178670000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402493704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402493704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402493704 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402493704 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 402493704 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 402493704 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.848771 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18027.848771 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18027.848771 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18027.848771 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15687.944508 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15687.944508 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15687.944508 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15687.944508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15687.944508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15687.944508 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +388,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1213 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1213 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1213 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1213 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1213 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1213 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10134 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10134 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10134 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10134 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10134 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10134 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139352000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 139352000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139352000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 139352000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139352000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 139352000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1247 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1247 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1247 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1247 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1247 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1247 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10142 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10142 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10142 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10142 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10142 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10142 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124096500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124096500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13750.937438 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13750.937438 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13750.937438 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13750.937438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13750.937438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13750.937438 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12235.900217 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12235.900217 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12235.900217 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12235.900217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12235.900217 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12235.900217 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1528066 # number of replacements -system.cpu.dcache.tagsinuse 4095.024861 # Cycle average of tags in use -system.cpu.dcache.total_refs 667221349 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532162 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 435.477025 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 286461000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.024861 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999762 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999762 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 457042035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457042035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210179266 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210179266 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 48 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 48 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667221301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667221301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667221301 # number of overall hits -system.cpu.dcache.overall_hits::total 667221301 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928301 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1928301 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 615630 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 615630 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2543931 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2543931 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2543931 # number of overall misses -system.cpu.dcache.overall_misses::total 2543931 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609210500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76609210500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362476485 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30362476485 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106971686985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106971686985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106971686985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106971686985 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 458970336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 458970336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1528011 # number of replacements +system.cpu.dcache.tagsinuse 4095.070038 # Cycle average of tags in use +system.cpu.dcache.total_refs 666681777 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1532107 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 435.140481 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 262302000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.070038 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999773 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999773 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 456946751 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 456946751 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209734975 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209734975 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 51 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 51 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 666681726 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666681726 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666681726 # number of overall hits +system.cpu.dcache.overall_hits::total 666681726 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928385 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928385 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1059921 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1059921 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2988306 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2988306 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2988306 # number of overall misses +system.cpu.dcache.overall_misses::total 2988306 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71846140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71846140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29139765486 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29139765486 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 19500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 19500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 100985905486 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 100985905486 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 100985905486 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 100985905486 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 458875136 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458875136 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 48 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 48 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 669765232 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 669765232 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 669765232 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 669765232 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004201 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004201 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002921 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002921 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003798 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003798 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003798 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003798 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.865203 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.865203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.358194 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.358194 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42049.759598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42049.759598 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 174500 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669670032 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669670032 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669670032 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669670032 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005028 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005028 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.019231 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.019231 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004462 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004462 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004462 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004462 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37257.155599 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37257.155599 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27492.393760 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27492.393760 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33793.696324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33793.696324 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9184.210526 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7952.380952 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109390 # number of writebacks -system.cpu.dcache.writebacks::total 109390 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467746 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467746 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 544023 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 544023 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1011769 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1011769 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1011769 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1011769 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460555 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460555 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71607 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71607 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1532162 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1532162 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1532162 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1532162 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266349000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266349000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176578500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176578500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 53442927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 53442927500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 109393 # number of writebacks +system.cpu.dcache.writebacks::total 109393 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467889 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467889 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 988310 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 988310 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1456199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1456199 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1456199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1456199 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460496 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460496 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71611 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71611 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1532107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532107 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532107 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532107 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50211071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50211071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3191098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3191098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53402169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 53402169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53402169000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 53402169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003183 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003183 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.923399 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.923399 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.284511 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.284511 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34379.464922 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34379.464922 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44561.561771 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44561.561771 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34855.378247 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34855.378247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34855.378247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34855.378247 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480672 # number of replacements -system.cpu.l2cache.tagsinuse 32700.801233 # Cycle average of tags in use -system.cpu.l2cache.total_refs 66336 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.043832 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480649 # number of replacements +system.cpu.l2cache.tagsinuse 32705.674184 # Cycle average of tags in use +system.cpu.l2cache.total_refs 66319 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513383 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.043822 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3222.422931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 46.121134 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29432.257169 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.098341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001408 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.898201 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997949 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7139 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51386 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 58525 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109390 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109390 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4759 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7139 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 56145 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 63284 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7139 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 56145 # number of overall hits -system.cpu.l2cache.overall_hits::total 63284 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2995 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1409163 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1412158 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66854 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2995 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1476017 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1479012 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2995 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1476017 # number of overall misses -system.cpu.l2cache.overall_misses::total 1479012 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399927000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48506895000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813613000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2813613000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 106968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 51213540000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 51320508000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 106968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 51213540000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 51320508000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10134 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1460549 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1470683 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 109390 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 109390 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 71613 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71613 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1532162 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1542296 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1532162 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1542296 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.295540 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964817 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.960206 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933546 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.933546 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.295540 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963356 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.958968 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295540 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963356 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.958968 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35715.525876 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.578075 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.481432 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.933527 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.933527 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34699.182968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34699.182968 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 107500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 3216.878531 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 46.035813 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29442.759840 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.098171 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001405 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.898522 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998098 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7160 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 51354 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 58514 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109393 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109393 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 7160 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 56108 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 63268 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7160 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 56108 # number of overall hits +system.cpu.l2cache.overall_hits::total 63268 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2982 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1409142 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1412124 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66857 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66857 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2982 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1475999 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1478981 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2982 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1475999 # number of overall misses +system.cpu.l2cache.overall_misses::total 1478981 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106529000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48698727500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48805256500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3114588000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3114588000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 106529000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 51813315500 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1532107 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1542249 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1532107 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1542249 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.294025 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964838 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.960212 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933614 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933614 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.294025 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963379 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.958977 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.294025 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963379 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.958977 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35724.010731 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34559.134211 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34561.594095 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46585.817491 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46585.817491 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35724.010731 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35103.896073 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 35105.146381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35724.010731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35103.896073 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 35105.146381 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 105500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5375 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5275 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks system.cpu.l2cache.writebacks::total 66898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2995 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409163 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1412158 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2995 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1476017 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1479012 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1476017 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1479012 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717505000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814870000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612284000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612284000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329789000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46427154000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329789000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46427154000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964817 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960206 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963356 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.958968 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963356 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.958968 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32509.181970 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.738915 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.889342 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.460765 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.460765 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2982 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409142 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1412124 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66857 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66857 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1475999 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1478981 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2982 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1475999 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1478981 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96989500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44003988500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44100978000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913645500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913645500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96989500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46917634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 47014623500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96989500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46917634000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 47014623500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964838 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960212 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933614 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933614 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.958977 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.958977 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32524.983233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31227.504751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31230.244653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43580.260855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43580.260855 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index ed560b063..a8bcfc08a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.813572 # Number of seconds simulated -sim_ticks 2813572242000 # Number of ticks simulated -final_tick 2813572242000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.811836 # Number of seconds simulated +sim_ticks 2811836424000 # Number of ticks simulated +final_tick 2811836424000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1893151 # Simulator instruction rate (inst/s) -host_op_rate 1893151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2651343461 # Simulator tick rate (ticks/s) -host_mem_usage 227888 # Number of bytes of host memory used -host_seconds 1061.19 # Real time elapsed on the host +host_inst_rate 1325085 # Simulator instruction rate (inst/s) +host_op_rate 1325085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1854626286 # Simulator tick rate (ticks/s) +host_mem_usage 228472 # Number of bytes of host memory used +host_seconds 1516.12 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475279 # Nu system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33558000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33612069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1521721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1521721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1521721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33558000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35133790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33578716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33632818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54103 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54103 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1522660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1522660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1522660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33578716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35155479 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5627144484 # number of cpu cycles simulated +system.cpu.numCycles 5623672848 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5627144484 # Number of busy cycles +system.cpu.num_busy_cycles 5623672848 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.417406 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.427768 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.417406 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721883 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721883 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1478.427768 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.721889 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.721889 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 248319000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 248319000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 248319000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 248319000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 248319000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 248319000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 237582000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 237582000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 237582000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 237582000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 237582000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 237582000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23435.164213 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23435.164213 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22421.857305 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216531000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216531000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216531000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216531000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216531000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216531000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.192384 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.209846 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1063975000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.192384 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999803 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999803 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.209846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999807 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999807 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567803000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79567803000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3816006000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3816006000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83383809000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83383809000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83383809000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83383809000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81853590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81853590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81853590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81853590000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54494.092713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54494.092713 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53566.024227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53566.024227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53494.043698 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600150000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793377000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78793377000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793377000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78793377000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1479705 # number of replacements -system.cpu.l2cache.tagsinuse 32703.875584 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32704.499819 # Cycle average of tags in use system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3255.326122 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.503711 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29415.045751 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.099345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3254.482584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.474832 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29416.542403 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.099319 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.897676 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.897722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998062 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b1563a03b..70391a345 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.653191 # Number of seconds simulated -sim_ticks 653190727500 # Number of ticks simulated -final_tick 653190727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.659244 # Number of seconds simulated +sim_ticks 659244465000 # Number of ticks simulated +final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90710 # Simulator instruction rate (inst/s) -host_op_rate 123535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42799734 # Simulator tick rate (ticks/s) -host_mem_usage 235092 # Number of bytes of host memory used -host_seconds 15261.56 # Real time elapsed on the host -sim_insts 1384379220 # Number of instructions simulated -sim_ops 1885333972 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 203328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94517952 # Number of bytes read from this memory -system.physmem.bytes_read::total 94721280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 203328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 203328 # Number of instructions bytes read from this memory +host_inst_rate 88407 # Simulator instruction rate (inst/s) +host_op_rate 120399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42099861 # Simulator tick rate (ticks/s) +host_mem_usage 243836 # Number of bytes of host memory used +host_seconds 15659.07 # Real time elapsed on the host +sim_insts 1384375635 # Number of instructions simulated +sim_ops 1885330387 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94515200 # Number of bytes read from this memory +system.physmem.bytes_read::total 94714816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 199616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 199616 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476843 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1480020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476800 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479919 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 311284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 144701919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 145013204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 311284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 311284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6476418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6476418 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6476418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 311284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 144701919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 151489621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 143368970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 143671765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6416946 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6416946 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6416946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 143368970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 150088711 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1306381456 # number of cpu cycles simulated +system.cpu.numCycles 1318488931 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 451886525 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 356592173 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33205003 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 281633187 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 237475635 # Number of BTB hits +system.cpu.BPredUnit.lookups 461326092 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 364071075 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 34100101 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 298580925 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 245422956 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53725762 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2808142 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 371691213 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2329385713 # Number of instructions fetch has processed -system.cpu.fetch.Branches 451886525 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 291201397 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621090552 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 170450530 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 138693587 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 29461 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 349470928 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11301689 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1268700671 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.542231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.167897 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 54976315 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2806988 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 381926912 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2354617227 # Number of instructions fetch has processed +system.cpu.fetch.Branches 461326092 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 300399271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 631966560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 174781634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133381872 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1547 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 26290 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 359560180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11891763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1287933807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.529860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156146 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 647656502 51.05% 51.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44886599 3.54% 54.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100617653 7.93% 62.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 60404416 4.76% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 73875113 5.82% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44960792 3.54% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31035484 2.45% 79.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30635125 2.41% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 234628987 18.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 656012764 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47127862 3.66% 54.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105351348 8.18% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 60429666 4.69% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 75027065 5.83% 73.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45419751 3.53% 76.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32157937 2.50% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 32241388 2.50% 81.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 234166026 18.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1268700671 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345907 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.783082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 423570129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 110130146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 579255946 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18563929 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 137180521 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 50568077 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 14826 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3119517279 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28937 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 137180521 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 460603750 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40419610 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 558753819 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71243284 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3033648086 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 193 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4887381 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56133943 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1685 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2996122982 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14446186472 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13843342856 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 602843616 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153898 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1002969084 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28984 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24876 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 185421286 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 977548256 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 509159433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36902722 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 39166460 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2862588309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35911 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2484024411 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13118317 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 964784903 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2432051802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12801 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1268700671 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.957928 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.885204 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1287933807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349890 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.785845 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433461682 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105761116 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 591844441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16248270 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 140618298 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 52072887 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12605 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3150187282 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 23939 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 140618298 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 469309271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39277977 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 483250 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 570159229 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68085782 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3069262221 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 155 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4380621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54394099 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1922 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3038163295 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14611934802 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13977694721 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 634240081 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993148162 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1045015133 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27322 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23140 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179514029 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 982659180 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 514844433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35819898 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36120464 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2890303698 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 33130 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2506565055 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17234382 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 992532581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2476785189 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1287933807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.946191 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883330 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 413577866 32.60% 32.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 194484687 15.33% 47.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 205713957 16.21% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171271635 13.50% 77.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 131142170 10.34% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97400688 7.68% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37845090 2.98% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12462379 0.98% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4802199 0.38% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 425460645 33.03% 33.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 193710960 15.04% 48.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 207680071 16.13% 64.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 174651445 13.56% 77.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137124890 10.65% 88.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 94993427 7.38% 95.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35869114 2.79% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12687801 0.99% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5755454 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1268700671 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1287933807 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 960888 1.05% 1.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23894 0.03% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55821815 60.83% 61.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 34963808 38.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 692420 0.75% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24115 0.03% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56113360 61.04% 61.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35101326 38.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1133289530 45.62% 45.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11232040 0.45% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876506 0.28% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503108 0.22% 46.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23588545 0.95% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 841636528 33.88% 81.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 460522863 18.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1147061112 45.76% 45.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11228333 0.45% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876483 0.27% 46.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5512765 0.22% 46.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 16 0.00% 46.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23755231 0.95% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 846734490 33.78% 81.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 464021335 18.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2484024411 # Type of FU issued -system.cpu.iq.rate 1.901454 # Inst issue rate -system.cpu.iq.fu_busy_cnt 91770405 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036944 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6213658406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3738455000 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2292430207 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 127979809 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 89021624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58699426 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2509271154 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66523662 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 80303664 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2506565055 # Type of FU issued +system.cpu.iq.rate 1.901089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91931221 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036676 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6281789129 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3788847878 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2312502456 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 128440391 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 94088071 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58648289 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2531838073 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66658203 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 81288215 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 346159349 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5258 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1403998 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 232162410 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 351270990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1405210 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 237848127 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 137180521 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17480517 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1686547 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2862638347 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 10688123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 977548256 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 509159433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24752 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1673918 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2091 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1403998 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34817527 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1757167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36574694 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2405136648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 795998932 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78887763 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 140618298 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16819525 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1547443 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2890351322 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8718298 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 982659180 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 514844433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22537 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1538114 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1067 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1405210 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36121914 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2298987 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 38420901 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2424696979 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 800223206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 81868076 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14127 # number of nop insts executed -system.cpu.iew.exec_refs 1234173393 # number of memory reference insts executed -system.cpu.iew.exec_branches 329367580 # Number of branches executed -system.cpu.iew.exec_stores 438174461 # Number of stores executed -system.cpu.iew.exec_rate 1.841068 # Inst execution rate -system.cpu.iew.wb_sent 2376887575 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2351129633 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1360698402 # num instructions producing a value -system.cpu.iew.wb_consumers 2562363668 # num instructions consuming a value +system.cpu.iew.exec_nop 14494 # number of nop insts executed +system.cpu.iew.exec_refs 1240121255 # number of memory reference insts executed +system.cpu.iew.exec_branches 334180264 # Number of branches executed +system.cpu.iew.exec_stores 439898049 # Number of stores executed +system.cpu.iew.exec_rate 1.838997 # Inst execution rate +system.cpu.iew.wb_sent 2396725321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2371150745 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1368219909 # num instructions producing a value +system.cpu.iew.wb_consumers 2564381587 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.799727 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.531033 # average fanout of values written-back +system.cpu.iew.wb_rate 1.798385 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533548 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 977293768 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23110 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33191422 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1131520152 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.666205 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.368466 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 1005010225 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22393 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 34087773 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1147315511 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.643263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.351044 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 484597847 42.83% 42.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 298921465 26.42% 69.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90821305 8.03% 77.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 72269012 6.39% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 45034307 3.98% 87.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23256378 2.06% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15793077 1.40% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9817791 0.87% 91.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 91008970 8.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 497187613 43.33% 43.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 300050723 26.15% 69.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93458742 8.15% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72384885 6.31% 83.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45393865 3.96% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22818775 1.99% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15801520 1.38% 91.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11015018 0.96% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89204370 7.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1131520152 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390236 # Number of instructions committed -system.cpu.commit.committedOps 1885344988 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1147315511 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384386651 # Number of instructions committed +system.cpu.commit.committedOps 1885341403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385930 # Number of memory references committed -system.cpu.commit.loads 631388907 # Number of loads committed +system.cpu.commit.refs 908384496 # Number of memory references committed +system.cpu.commit.loads 631388190 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299636121 # Number of branches committed +system.cpu.commit.branches 299635404 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705771 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653702903 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 91008970 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89204370 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3903131593 # The number of ROB reads -system.cpu.rob.rob_writes 5862472148 # The number of ROB writes -system.cpu.timesIdled 1341228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37680785 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379220 # Number of Instructions Simulated -system.cpu.committedOps 1885333972 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379220 # Number of Instructions Simulated -system.cpu.cpi 0.943659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.943659 # CPI: Total CPI of All Threads -system.cpu.ipc 1.059705 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.059705 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11952036932 # number of integer regfile reads -system.cpu.int_regfile_writes 2256711080 # number of integer regfile writes -system.cpu.fp_regfile_reads 70681119 # number of floating regfile reads -system.cpu.fp_regfile_writes 50325350 # number of floating regfile writes -system.cpu.misc_regfile_reads 3723531681 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776354 # number of misc regfile writes -system.cpu.icache.replacements 23459 # number of replacements -system.cpu.icache.tagsinuse 1656.238339 # Cycle average of tags in use -system.cpu.icache.total_refs 349436364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 25154 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13891.880576 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3948444424 # The number of ROB reads +system.cpu.rob.rob_writes 5921335810 # The number of ROB writes +system.cpu.timesIdled 1335770 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30555124 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384375635 # Number of Instructions Simulated +system.cpu.committedOps 1885330387 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384375635 # Number of Instructions Simulated +system.cpu.cpi 0.952407 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.952407 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049971 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049971 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12040516185 # number of integer regfile reads +system.cpu.int_regfile_writes 2278755627 # number of integer regfile writes +system.cpu.fp_regfile_reads 70304928 # number of floating regfile reads +system.cpu.fp_regfile_writes 50983418 # number of floating regfile writes +system.cpu.misc_regfile_reads 3755360027 # number of misc regfile reads +system.cpu.misc_regfile_writes 13774920 # number of misc regfile writes +system.cpu.icache.replacements 22971 # number of replacements +system.cpu.icache.tagsinuse 1659.651348 # Cycle average of tags in use +system.cpu.icache.total_refs 359526375 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24666 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14575.787521 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1656.238339 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808710 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808710 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 349440471 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 349440471 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 349440471 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 349440471 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 349440471 # number of overall hits -system.cpu.icache.overall_hits::total 349440471 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30457 # number of overall misses -system.cpu.icache.overall_misses::total 30457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 315232000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 315232000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 315232000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 315232000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 315232000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 315232000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 349470928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 349470928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 349470928 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 349470928 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 349470928 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 349470928 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10350.067308 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10350.067308 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10350.067308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10350.067308 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1659.651348 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.810377 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.810377 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 359530551 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 359530551 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 359530551 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 359530551 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 359530551 # number of overall hits +system.cpu.icache.overall_hits::total 359530551 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 29629 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 29629 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 29629 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 29629 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 29629 # number of overall misses +system.cpu.icache.overall_misses::total 29629 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 243264500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 243264500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 243264500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 243264500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 243264500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 243264500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 359560180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 359560180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 359560180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 359560180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 359560180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 359560180 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000082 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000082 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000082 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000082 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000082 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000082 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8210.351345 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8210.351345 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8210.351345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8210.351345 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 916 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 916 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 916 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 916 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 916 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 916 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29541 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 29541 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 29541 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 29541 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 29541 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 29541 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 200922000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 200922000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 200922000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 200922000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 200922000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 200922000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6801.462374 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6801.462374 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 731 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 731 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 731 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 731 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 731 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 731 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28898 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28898 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28898 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28898 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28898 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28898 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 166216000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 166216000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 166216000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 166216000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 166216000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 166216000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5751.816735 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5751.816735 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533244 # number of replacements -system.cpu.dcache.tagsinuse 4094.802366 # Cycle average of tags in use -system.cpu.dcache.total_refs 977260435 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537340 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 635.682695 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 300664000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.802366 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 701107300 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 701107300 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276115713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276115713 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 12426 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 12426 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11711 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11711 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 977223013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 977223013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 977223013 # number of overall hits -system.cpu.dcache.overall_hits::total 977223013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2133926 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2133926 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 819965 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 819965 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2953891 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2953891 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2953891 # number of overall misses -system.cpu.dcache.overall_misses::total 2953891 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80611211500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80611211500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33925562500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33925562500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 304000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114536774000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114536774000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114536774000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114536774000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 703241226 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 703241226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533081 # number of replacements +system.cpu.dcache.tagsinuse 4094.855996 # Cycle average of tags in use +system.cpu.dcache.total_refs 980345028 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537177 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 637.756763 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 283497000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.855996 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999721 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999721 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 704193068 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 704193068 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276118274 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276118274 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11579 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11579 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10994 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10994 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 980311342 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 980311342 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 980311342 # number of overall hits +system.cpu.dcache.overall_hits::total 980311342 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2282979 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2282979 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 817404 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 817404 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3100383 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3100383 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3100383 # number of overall misses +system.cpu.dcache.overall_misses::total 3100383 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77215847500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77215847500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27888772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27888772000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105104619500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105104619500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105104619500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105104619500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 706476047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 706476047 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12437 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11711 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 980176904 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 980176904 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 980176904 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 980176904 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003034 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003034 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002961 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002961 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000884 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000884 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003014 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003014 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37776.010743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37776.010743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41374.403176 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41374.403176 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 27636.363636 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 27636.363636 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38774.881673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38774.881673 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11582 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11582 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10994 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10994 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 983411725 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 983411725 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 983411725 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 983411725 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002952 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002952 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000259 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000259 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33822.408134 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33822.408134 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34118.712411 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34118.712411 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108418 # number of writebacks -system.cpu.dcache.writebacks::total 108418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 669125 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 669125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 11 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 11 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1412163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1412163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1412163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1412163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464801 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464801 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76927 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76927 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541728 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541728 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541728 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541728 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50340349002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50340349002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506118000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506118000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52846467002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52846467002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52846467002 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52846467002 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001573 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001573 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34366.681209 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34366.681209 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32577.872529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32577.872529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks +system.cpu.dcache.writebacks::total 108430 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 818362 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 818362 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740610 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 740610 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1558972 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1558972 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1558972 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1558972 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464617 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76794 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76794 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541411 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541411 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541411 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541411 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50261586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50261586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2476957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2476957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52738544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52738544000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52738544000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52738544000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002073 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002073 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001567 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001567 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34317.221840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34317.221840 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32254.570670 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32254.570670 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480210 # number of replacements -system.cpu.l2cache.tagsinuse 32693.720569 # Cycle average of tags in use -system.cpu.l2cache.total_refs 84475 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512954 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.055834 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480118 # number of replacements +system.cpu.l2cache.tagsinuse 32698.465426 # Cycle average of tags in use +system.cpu.l2cache.total_refs 83907 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512862 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.055462 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3140.945883 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 59.138585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29493.636100 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.095854 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001805 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.900074 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997733 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 54011 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 75979 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108418 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.949342 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999291 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999291 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910683 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910683 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.947546 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.947546 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32419.044566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31312.826651 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31315.267025 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.917193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.917193 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32419.044566 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31299.362134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31301.721919 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 06a14cc7a..1b9ad306d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.369932 # Number of seconds simulated -sim_ticks 2369931974000 # Number of ticks simulated -final_tick 2369931974000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.368273 # Number of seconds simulated +sim_ticks 2368273403000 # Number of ticks simulated +final_tick 2368273403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 844398 # Simulator instruction rate (inst/s) -host_op_rate 1145486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1448435887 # Simulator tick rate (ticks/s) -host_mem_usage 232760 # Number of bytes of host memory used -host_seconds 1636.20 # Real time elapsed on the host +host_inst_rate 821983 # Simulator instruction rate (inst/s) +host_op_rate 1115078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1408999350 # Simulator tick rate (ticks/s) +host_mem_usage 241788 # Number of bytes of host memory used +host_seconds 1680.82 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475585 # Nu system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39848165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39909115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60950 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60950 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785003 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785003 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39848165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41694118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 60993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39876072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39937065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1786253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1786253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1786253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39876072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41723318 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4739863948 # number of cpu cycles simulated +system.cpu.numCycles 4736546806 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1381604339 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 908382479 # nu system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4739863948 # Number of busy cycles +system.cpu.num_busy_cycles 4736546806 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.322496 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1392.329214 # Cycle average of tags in use system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.322496 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.679845 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.679845 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1392.329214 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.679848 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.679848 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 19803 # n system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 372133000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 372133000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 372133000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 372133000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 372133000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 372133000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352238000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352238000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352238000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352238000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352238000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352238000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18791.748725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18791.748725 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18791.748725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18791.748725 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17787.102964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17787.102964 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 19803 system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312724000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312724000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312724000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312724000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312724000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312724000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312632000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312632000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15791.748725 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15791.748725 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.950469 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.965929 # Cycle average of tags in use system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1004561000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.950469 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999744 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999744 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.965929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999748 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999748 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650958000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79650958000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794840000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3794840000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83445798000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83445798000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83445798000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83445798000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78190013000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78190013000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81912059000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81912059000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81912059000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81912059000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.849009 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.849009 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.247595 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.247595 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54409.829342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54409.829342 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53409.773267 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268339000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268339000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844839000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78844839000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844839000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78844839000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.849009 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.849009 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.247595 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.247595 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1478696 # number of replacements -system.cpu.l2cache.tagsinuse 32689.689328 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32690.092056 # Cycle average of tags in use system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3194.581985 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.931287 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29462.176056 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.097491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3194.112587 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 32.917167 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29463.062302 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.097477 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.899114 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.899141 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997622 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 1477842 # nu system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1475585 # number of overall misses system.cpu.l2cache.overall_misses::total 1477842 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117364000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117369000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73293584000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73410948000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73410953000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 117364000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 117369000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 76730420000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76847784000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 117364000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 76847789000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 117369000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 76730420000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76847784000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76847789000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.951325 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.215330 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.003542 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.215330 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.003383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.215330 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.003383 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1477842 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1475585 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1477842 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90285000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56379680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469965000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90285000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59023400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59113680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90280000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59113685000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90285000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59023400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59113680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59113685000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |