diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/se/40.perlbmk | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/se/40.perlbmk')
8 files changed, 2243 insertions, 2031 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index cf6f894cc..2ef1dce8d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.555548 # Number of seconds simulated -sim_ticks 555548307000 # Number of ticks simulated -final_tick 555548307000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.555533 # Number of seconds simulated +sim_ticks 555532734000 # Number of ticks simulated +final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201077 # Simulator instruction rate (inst/s) -host_op_rate 201077 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120272803 # Simulator tick rate (ticks/s) -host_mem_usage 246132 # Number of bytes of host memory used -host_seconds 4619.07 # Real time elapsed on the host +host_inst_rate 337976 # Simulator instruction rate (inst/s) +host_op_rate 337976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 202152446 # Simulator tick rate (ticks/s) +host_mem_usage 300884 # Number of bytes of host memory used +host_seconds 2748.09 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,43 +23,43 @@ system.physmem.num_reads::cpu.inst 291518 # Nu system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33583312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33583312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 336043 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 336043 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7681982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7681982 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7681982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33583312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41265294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 33584253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33584253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 336052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 336052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7682197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7682197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7682197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33584253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41266450 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291518 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17984 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17088 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 281 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 267 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17934 # Per bank write bursts -system.physmem.perBankRdBursts::1 18286 # Per bank write bursts +system.physmem.perBankRdBursts::0 17939 # Per bank write bursts +system.physmem.perBankRdBursts::1 18284 # Per bank write bursts system.physmem.perBankRdBursts::2 18304 # Per bank write bursts -system.physmem.perBankRdBursts::3 18252 # Per bank write bursts -system.physmem.perBankRdBursts::4 18169 # Per bank write bursts -system.physmem.perBankRdBursts::5 18242 # Per bank write bursts -system.physmem.perBankRdBursts::6 18316 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts +system.physmem.perBankRdBursts::3 18254 # Per bank write bursts +system.physmem.perBankRdBursts::4 18163 # Per bank write bursts +system.physmem.perBankRdBursts::5 18248 # Per bank write bursts +system.physmem.perBankRdBursts::6 18324 # Per bank write bursts +system.physmem.perBankRdBursts::7 18299 # Per bank write bursts system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts -system.physmem.perBankRdBursts::10 18210 # Per bank write bursts -system.physmem.perBankRdBursts::11 18385 # Per bank write bursts -system.physmem.perBankRdBursts::12 18260 # Per bank write bursts -system.physmem.perBankRdBursts::13 18048 # Per bank write bursts +system.physmem.perBankRdBursts::9 18226 # Per bank write bursts +system.physmem.perBankRdBursts::10 18216 # Per bank write bursts +system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18039 # Per bank write bursts system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18103 # Per bank write bursts +system.physmem.perBankRdBursts::15 18104 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -69,7 +69,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::9 4190 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 555548231500 # Total gap between requests +system.physmem.totGap 555532658500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4046 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,44 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.415915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.780585 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.040689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39691 37.85% 37.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43831 41.80% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8352 7.97% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1265 1.21% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 732 0.70% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 905 0.86% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1060 1.01% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 884 0.84% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8138 7.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104858 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.322621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.136998 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 770.555291 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 105079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 217.968119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 139.907625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 270.030152 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 40113 38.17% 38.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44071 41.94% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8455 8.05% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 717 0.68% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 543 0.52% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 672 0.64% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1241 1.18% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1153 1.10% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8114 7.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105079 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.423096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.196398 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 785.521839 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.458537 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.855483 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3076 76.04% 76.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 966 23.88% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 2434432250 # Total ticks spent queuing -system.physmem.totMemAccLat 7895126000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456185000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8358.94 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.485163 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.463667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3065 75.79% 75.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 975 24.11% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads +system.physmem.totQLat 2419619750 # Total ticks spent queuing +system.physmem.totMemAccLat 7880576000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8307.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27108.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27057.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s @@ -236,19 +236,18 @@ system.physmem.busUtil 0.32 # Da system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 202612 # Number of row buffer hits during reads -system.physmem.writeRowHits 50417 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes -system.physmem.avgGap 1550939.92 # Average gap between requests -system.physmem.pageHitRate 70.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275426566250 # Time in different power states -system.physmem.memoryStateTime::REF 18550740000 # Time in different power states +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 202343 # Number of row buffer hits during reads +system.physmem.writeRowHits 50484 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes +system.physmem.avgGap 1550896.45 # Average gap between requests +system.physmem.pageHitRate 70.64 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275459224750 # Time in different power states +system.physmem.memoryStateTime::REF 18550220000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261564123750 # Time in different power states +system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 41265294 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution @@ -256,23 +255,32 @@ system.membus.trans_dist::ReadExReq 66644 # Tr system.membus.trans_dist::ReadExResp 66644 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22924864 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 954576500 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358201 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358201 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358201 # Request fanout histogram +system.membus.reqLayer0.occupancy 954482500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2724054750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2723745500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 125108663 # Number of BP lookups -system.cpu.branchPred.condPredicted 80505378 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 80505376 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103330872 # Number of BTB lookups -system.cpu.branchPred.BTBHits 82874855 # Number of BTB hits +system.cpu.branchPred.BTBLookups 103330871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82874854 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18690214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 18690215 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -290,10 +298,10 @@ system.cpu.dtb.data_hits 335842628 # DT system.cpu.dtb.data_misses 205618 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 336048246 # DTB accesses -system.cpu.itb.fetch_hits 315070348 # ITB hits +system.cpu.itb.fetch_hits 315070347 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 315070468 # ITB accesses +system.cpu.itb.fetch_accesses 315070467 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,24 +315,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1111096614 # number of cpu cycles simulated +system.cpu.numCycles 1111065468 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23870770 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23870771 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.196285 # CPI: cycles per instruction -system.cpu.ipc 0.835921 # IPC: instructions per cycle +system.cpu.cpi 1.196252 # CPI: cycles per instruction +system.cpu.ipc 0.835945 # IPC: instructions per cycle system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58548412 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 58517266 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 10608 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.445112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 315057997 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1686.446779 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 315057996 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25510.768988 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 25510.768907 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.445112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.446779 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id @@ -334,44 +342,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 630153046 # Number of tag accesses -system.cpu.icache.tags.data_accesses 630153046 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 315057997 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 315057997 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 315057997 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 315057997 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 315057997 # number of overall hits -system.cpu.icache.overall_hits::total 315057997 # number of overall hits +system.cpu.icache.tags.tag_accesses 630153044 # Number of tag accesses +system.cpu.icache.tags.data_accesses 630153044 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 315057996 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 315057996 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 315057996 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 315057996 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 315057996 # number of overall hits +system.cpu.icache.overall_hits::total 315057996 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses system.cpu.icache.overall_misses::total 12351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 334622500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 334622500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 334622500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 334622500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 334622500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 334622500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 315070348 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 315070348 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 315070348 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 315070348 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 315070348 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 315070348 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 334498250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 334498250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 334498250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 334498250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 334498250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 334498250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 315070347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 315070347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 315070347 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 315070347 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 315070347 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 315070347 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27092.745527 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27092.745527 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27092.745527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27092.745527 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27082.685613 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27082.685613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27082.685613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27082.685613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -386,26 +394,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12351 system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308669500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 308669500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308669500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 308669500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308669500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 308669500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308545750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 308545750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308545750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 308545750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308545750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 308545750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24991.458182 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24991.458182 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24981.438750 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 101892158 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution @@ -414,28 +421,38 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69010 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56606016 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 884470 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884470 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 884470 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19151500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19151250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222065750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1221989250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.l2cache.tags.replacements 258739 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.591220 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32601.629306 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 523854 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291475 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.797252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2866.071604 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087466 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994922 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2865.774027 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.855280 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994923 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id @@ -463,14 +480,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 291519 # system.cpu.l2cache.demand_misses::total 291519 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 291519 # number of overall misses system.cpu.l2cache.overall_misses::total 291519 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15957253750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15957253750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4332290500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4332290500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20289544250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20289544250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20289544250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20289544250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15924584250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15924584250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4349858250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4349858250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20274442500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20274442500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20274442500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20274442500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 723971 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723971 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) @@ -489,14 +506,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367624 system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.367624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70960.550306 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70960.550306 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65006.459696 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65006.459696 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69599.388891 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69599.388891 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70815.271818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70815.271818 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65270.065572 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65270.065572 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69547.585235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69547.585235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,14 +532,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 291519 system.cpu.l2cache.demand_mshr_misses::total 291519 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 291519 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13140394750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13140394750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3498793500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3498793500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16639188250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16639188250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16639188250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16639188250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13108086750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13108086750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3516385750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3516385750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16624472500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16624472500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16624472500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16624472500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965715 # mshr miss rate for ReadExReq accesses @@ -531,22 +548,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367624 system.cpu.l2cache.demand_mshr_miss_rate::total 0.367624 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58434.217899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58434.217899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52499.752416 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52499.752416 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58290.546971 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58290.546971 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52763.725917 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.725917 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 776534 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.879870 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322859768 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.879782 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322859767 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.588727 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 413.588726 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879870 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879782 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -556,16 +573,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 950 system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648198338 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648198338 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 224695721 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224695721 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 648198336 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648198336 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 224695720 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224695720 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 322859768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322859768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 322859768 # number of overall hits -system.cpu.dcache.overall_hits::total 322859768 # number of overall hits +system.cpu.dcache.demand_hits::cpu.inst 322859767 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322859767 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 322859767 # number of overall hits +system.cpu.dcache.overall_hits::total 322859767 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses @@ -574,22 +591,22 @@ system.cpu.dcache.demand_misses::cpu.inst 849086 # n system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses system.cpu.dcache.overall_misses::total 849086 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22864552750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22864552750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8987445000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8987445000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 31851997750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31851997750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 31851997750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31851997750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 225407654 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225407654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22831828750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22831828750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9022635000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9022635000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 31854463750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31854463750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 31854463750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31854463750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 225407653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225407653 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 323708854 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323708854 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 323708854 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323708854 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 323708853 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323708853 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 323708853 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323708853 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses @@ -598,14 +615,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32116.158051 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.158051 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65528.606738 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65528.606738 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37513.276335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37513.276335 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32070.193052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32070.193052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65785.181513 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65785.181513 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37516.180634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37516.180634 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -632,14 +649,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 780630 system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21363533750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21363533750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4424989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4424989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25788522750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25788522750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25788522750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25788522750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21330988000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21330988000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4442556750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4442556750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25773544750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25773544750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25773544750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25773544750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses @@ -648,14 +665,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412 system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30020.985568 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.985568 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64120.982466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64120.982466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 29975.250836 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29975.250836 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64375.550645 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64375.550645 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 9bdd841ee..b682164e9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278171 # Number of seconds simulated -sim_ticks 278170874500 # Number of ticks simulated -final_tick 278170874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278139 # Number of seconds simulated +sim_ticks 278139424500 # Number of ticks simulated +final_tick 278139424500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125961 # Simulator instruction rate (inst/s) -host_op_rate 125961 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41594749 # Simulator tick rate (ticks/s) -host_mem_usage 247184 # Number of bytes of host memory used -host_seconds 6687.64 # Real time elapsed on the host +host_inst_rate 187672 # Simulator instruction rate (inst/s) +host_op_rate 187672 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61966028 # Simulator tick rate (ticks/s) +host_mem_usage 301896 # Number of bytes of host memory used +host_seconds 4488.58 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18476352 # Number of bytes read from this memory -system.physmem.bytes_read::total 18652352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176000 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory +system.physmem.bytes_read::total 18653120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288693 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291455 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 632705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66420872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67053576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 632705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 632705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15342052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15342052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15342052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 632705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66420872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82395628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291443 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 632546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66431374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67063920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 632546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 632546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15343787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15343787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15343787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 632546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66431374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82407706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291455 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291455 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18634688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18652352 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18634176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18944 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18653120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 296 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17914 # Per bank write bursts -system.physmem.perBankRdBursts::1 18261 # Per bank write bursts -system.physmem.perBankRdBursts::2 18310 # Per bank write bursts +system.physmem.perBankRdBursts::0 17915 # Per bank write bursts +system.physmem.perBankRdBursts::1 18264 # Per bank write bursts +system.physmem.perBankRdBursts::2 18305 # Per bank write bursts system.physmem.perBankRdBursts::3 18245 # Per bank write bursts -system.physmem.perBankRdBursts::4 18158 # Per bank write bursts -system.physmem.perBankRdBursts::5 18234 # Per bank write bursts -system.physmem.perBankRdBursts::6 18318 # Per bank write bursts -system.physmem.perBankRdBursts::7 18307 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::4 18154 # Per bank write bursts +system.physmem.perBankRdBursts::5 18231 # Per bank write bursts +system.physmem.perBankRdBursts::6 18323 # Per bank write bursts +system.physmem.perBankRdBursts::7 18314 # Per bank write bursts +system.physmem.perBankRdBursts::8 18231 # Per bank write bursts +system.physmem.perBankRdBursts::9 18221 # Per bank write bursts system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18386 # Per bank write bursts -system.physmem.perBankRdBursts::12 18247 # Per bank write bursts -system.physmem.perBankRdBursts::13 18053 # Per bank write bursts +system.physmem.perBankRdBursts::11 18383 # Per bank write bursts +system.physmem.perBankRdBursts::12 18244 # Per bank write bursts +system.physmem.perBankRdBursts::13 18043 # Per bank write bursts system.physmem.perBankRdBursts::14 17967 # Per bank write bursts -system.physmem.perBankRdBursts::15 18100 # Per bank write bursts +system.physmem.perBankRdBursts::15 18104 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4179 # Per bank write bursts -system.physmem.perBankWrBursts::10 4147 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278170791500 # Total gap between requests +system.physmem.totGap 278139341500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291443 # Read request sizes (log2) +system.physmem.readPktSize::6 291455 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 214189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 211494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4578 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,111 +193,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 228.644373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.919705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.922323 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35701 35.65% 35.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41944 41.88% 77.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10332 10.32% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 643 0.64% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 550 0.55% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 478 0.48% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 606 0.61% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1154 1.15% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8739 8.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100147 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.435955 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.134261 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 746.811219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 100451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.952415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.081554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 279.010577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36030 35.87% 35.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42282 42.09% 77.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10217 10.17% 88.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 414 0.41% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 384 0.38% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 317 0.32% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 757 0.75% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1270 1.26% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8780 8.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100451 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.301854 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.144651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 769.722850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.481701 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.460271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.857904 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3073 75.99% 75.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 965 23.86% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 3337058000 # Total ticks spent queuing -system.physmem.totMemAccLat 8796439250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11460.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.458498 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856350 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3077 76.07% 76.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 963 23.81% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads +system.physmem.totQLat 3340616250 # Total ticks spent queuing +system.physmem.totMemAccLat 8799847500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455795000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11473.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30210.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.33 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30223.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 67.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.06 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 207319 # Number of row buffer hits during reads -system.physmem.writeRowHits 50340 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.49 # Row buffer hit rate for writes -system.physmem.avgGap 776740.01 # Average gap between requests -system.physmem.pageHitRate 72.00 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 73797472500 # Time in different power states -system.physmem.memoryStateTime::REF 9288500000 # Time in different power states +system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing +system.physmem.readRowHits 206977 # Number of row buffer hits during reads +system.physmem.writeRowHits 50379 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.55 # Row buffer hit rate for writes +system.physmem.avgGap 776626.17 # Average gap between requests +system.physmem.pageHitRate 71.92 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 74109656250 # Time in different power states +system.physmem.memoryStateTime::REF 9287460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 195078106500 # Time in different power states +system.physmem.memoryStateTime::ACT 194735825750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 82395628 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 224814 # Transaction distribution -system.membus.trans_dist::ReadResp 224814 # Transaction distribution +system.membus.trans_dist::ReadReq 224829 # Transaction distribution +system.membus.trans_dist::ReadResp 224829 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66629 # Transaction distribution -system.membus.trans_dist::ReadExResp 66629 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649569 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22920064 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22920064 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 964230000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadExReq 66626 # Transaction distribution +system.membus.trans_dist::ReadExResp 66626 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649593 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649593 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920832 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358138 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358138 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358138 # Request fanout histogram +system.membus.reqLayer0.occupancy 956225500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2710224500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2708510750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 192451615 # Number of BP lookups -system.cpu.branchPred.condPredicted 125635967 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11884604 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155866017 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126935891 # Number of BTB hits +system.cpu.branchPred.lookups 192497192 # Number of BP lookups +system.cpu.branchPred.condPredicted 125506208 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11891081 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155386216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126898467 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.439106 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28844958 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.666489 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 29014222 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244501349 # DTB read hits -system.cpu.dtb.read_misses 309633 # DTB read misses +system.cpu.dtb.read_hits 244546246 # DTB read hits +system.cpu.dtb.read_misses 309763 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244810982 # DTB read accesses -system.cpu.dtb.write_hits 135678395 # DTB write hits -system.cpu.dtb.write_misses 31433 # DTB write misses +system.cpu.dtb.read_accesses 244856009 # DTB read accesses +system.cpu.dtb.write_hits 135693142 # DTB write hits +system.cpu.dtb.write_misses 31331 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135709828 # DTB write accesses -system.cpu.dtb.data_hits 380179744 # DTB hits -system.cpu.dtb.data_misses 341066 # DTB misses +system.cpu.dtb.write_accesses 135724473 # DTB write accesses +system.cpu.dtb.data_hits 380239388 # DTB hits +system.cpu.dtb.data_misses 341094 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380520810 # DTB accesses -system.cpu.itb.fetch_hits 196843274 # ITB hits -system.cpu.itb.fetch_misses 340 # ITB misses +system.cpu.dtb.data_accesses 380580482 # DTB accesses +system.cpu.itb.fetch_hits 197059053 # ITB hits +system.cpu.itb.fetch_misses 278 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 196843614 # ITB accesses +system.cpu.itb.fetch_accesses 197059331 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,99 +319,99 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556341750 # number of cpu cycles simulated +system.cpu.numCycles 556278850 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202596472 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648022555 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192451615 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155780849 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341400338 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24237220 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 65 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6944 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 202390061 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648021471 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192497192 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155912689 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341534414 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24250324 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6722 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 196843274 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6474022 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556122593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 197059053 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6903560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556056617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 237070993 42.63% 42.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30141188 5.42% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22117288 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36437929 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67906358 12.21% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21586506 3.88% 74.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19299171 3.47% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3525264 0.63% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118037896 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236849124 42.59% 42.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30318987 5.45% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22124224 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36449383 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67846603 12.20% 70.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21659642 3.90% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19297725 3.47% 78.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3452517 0.62% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118058412 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556122593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345923 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962249 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168349447 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89068138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273848076 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12745104 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12111828 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15365676 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7037 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1585434415 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25396 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12111828 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176490492 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 62059786 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14189 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278431125 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27015173 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538086365 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7791 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2366498 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17905765 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6836076 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1026692475 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1767991158 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728209753 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39781404 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 556056617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346044 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962582 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168903349 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88724490 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273566111 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12744273 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12118394 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15366279 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7028 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1583865955 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12118394 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176795678 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61743317 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13930 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278397423 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 26987875 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1537838720 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7334 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2373790 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17873362 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6849052 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1027019192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1768562187 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728780266 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39781920 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 387725317 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1423 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9582425 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372570647 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175396988 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40822996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11172222 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1305164678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015585029 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8790961 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462756562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 428157425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 86 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556122593 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826189 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.898849 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 388052034 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9574141 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372265088 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175432833 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40642740 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11166161 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304456084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1015678873 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790246 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462050270 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427374200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 556056617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.903970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 196378723 35.31% 35.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93218493 16.76% 52.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 92101634 16.56% 68.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 60001110 10.79% 79.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56881652 10.23% 89.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29459866 5.30% 94.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17057995 3.07% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7198930 1.29% 99.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3824190 0.69% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197073815 35.44% 35.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93100278 16.74% 52.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91275539 16.41% 68.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59807751 10.76% 79.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56767795 10.21% 89.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29817356 5.36% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17038926 3.06% 97.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7188508 1.29% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3986649 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556122593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556056617 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2464498 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2463855 10.47% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available @@ -432,118 +440,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15571985 66.15% 76.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5503822 23.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15566694 66.15% 76.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5500530 23.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579410115 57.05% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7864 0.00% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579447507 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181855 1.30% 58.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276884212 27.26% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138933358 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181923 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276926005 27.27% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138947884 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015585029 # Type of FU issued -system.cpu.iq.rate 1.825470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23540305 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023179 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548815722 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1726656461 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 939949010 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808195 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41310105 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425215 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002762123 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36361935 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50443717 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015678873 # Type of FU issued +system.cpu.iq.rate 1.825845 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23531079 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023168 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548927232 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1725239923 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940039301 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808456 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41311588 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425282 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002846638 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36362038 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50462240 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 135060050 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1143240 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45700 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77095788 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 134754491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1146539 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45582 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77131633 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2279 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4366 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4422 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12111828 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 61105954 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 191244 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479623370 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16690 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372570647 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175396988 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26783 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 176241 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45700 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11878414 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16350 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11894764 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976099064 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244811165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39485965 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12118394 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60795579 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 183960 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1478937167 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16099 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372265088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175432833 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 26971 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 168750 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45582 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11885427 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16182 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11901609 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976191371 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244856188 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39487502 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174458569 # number of nop insts executed -system.cpu.iew.exec_refs 380521398 # number of memory reference insts executed -system.cpu.iew.exec_branches 129090215 # Number of branches executed -system.cpu.iew.exec_stores 135710233 # Number of stores executed -system.cpu.iew.exec_rate 1.754495 # Inst execution rate -system.cpu.iew.wb_sent 974894086 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974374225 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556362190 # num instructions producing a value -system.cpu.iew.wb_consumers 832682807 # num instructions consuming a value +system.cpu.iew.exec_nop 174481002 # number of nop insts executed +system.cpu.iew.exec_refs 380581036 # number of memory reference insts executed +system.cpu.iew.exec_branches 129104728 # Number of branches executed +system.cpu.iew.exec_stores 135724848 # Number of stores executed +system.cpu.iew.exec_rate 1.754860 # Inst execution rate +system.cpu.iew.wb_sent 974983742 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974464583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556223277 # num instructions producing a value +system.cpu.iew.wb_consumers 832224680 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751395 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668156 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751756 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668357 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543793882 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543106202 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11877823 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483108609 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.922109 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.601347 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11884314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483349873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.921150 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.600543 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205236337 42.48% 42.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102049514 21.12% 63.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51661331 10.69% 74.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25803847 5.34% 79.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21528421 4.46% 84.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9152086 1.89% 85.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10413942 2.16% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6658903 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50604228 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205286712 42.47% 42.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102225167 21.15% 63.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51816081 10.72% 74.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25666887 5.31% 79.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21541208 4.46% 84.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9141976 1.89% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10432211 2.16% 88.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6655388 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50584243 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483108609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 483349873 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -589,229 +597,238 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50604228 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50584243 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1902264753 # The number of ROB reads -system.cpu.rob.rob_writes 3017778261 # The number of ROB writes -system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 219157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1901838322 # The number of ROB reads +system.cpu.rob.rob_writes 3016095658 # The number of ROB writes +system.cpu.timesIdled 3295 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 222233 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660439 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660439 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514145 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237156032 # number of integer regfile reads -system.cpu.int_regfile_writes 705771856 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691388 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411317 # number of floating regfile writes +system.cpu.cpi 0.660364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660364 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514316 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514316 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237260763 # number of integer regfile reads +system.cpu.int_regfile_writes 705832198 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691509 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411335 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 202299828 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 718925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718924 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68836 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68836 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12807 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654234 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1667041 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55864128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56273920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56273920 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 531160500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 718899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68835 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 408320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56270144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 879222 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879222 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 879222 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531099000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10099250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10065500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1208088500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1207435500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4693 # number of replacements -system.cpu.icache.tags.tagsinuse 1650.457565 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 196834917 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6403 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30741.045916 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4667 # number of replacements +system.cpu.icache.tags.tagsinuse 1655.176031 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 197050731 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6380 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30885.694514 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1650.457565 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.805887 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.805887 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1710 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1655.176031 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.808191 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.808191 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.834961 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 393692951 # Number of tag accesses -system.cpu.icache.tags.data_accesses 393692951 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 196834917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 196834917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 196834917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 196834917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 196834917 # number of overall hits -system.cpu.icache.overall_hits::total 196834917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8357 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8357 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8357 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8357 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8357 # number of overall misses -system.cpu.icache.overall_misses::total 8357 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329567249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329567249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329567249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329567249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329567249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329567249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 196843274 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 196843274 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 196843274 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 196843274 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 196843274 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 196843274 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1559 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 394124484 # Number of tag accesses +system.cpu.icache.tags.data_accesses 394124484 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 197050731 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 197050731 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 197050731 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 197050731 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 197050731 # number of overall hits +system.cpu.icache.overall_hits::total 197050731 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8321 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8321 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8321 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8321 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8321 # number of overall misses +system.cpu.icache.overall_misses::total 8321 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333298749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333298749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333298749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333298749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333298749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333298749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 197059052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 197059052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 197059052 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 197059052 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 197059052 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 197059052 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39436.071437 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39436.071437 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39436.071437 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39436.071437 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39436.071437 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40055.131475 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40055.131475 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40055.131475 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40055.131475 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40055.131475 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 711 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 64.636364 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1953 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1953 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1953 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1953 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1953 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1953 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6404 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6404 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6404 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6404 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6404 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6404 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242038999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242038999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242038999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242038999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242038999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242038999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37794.971736 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37794.971736 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37794.971736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37794.971736 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1940 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1940 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1940 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1940 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1940 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1940 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6381 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6381 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6381 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6381 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6381 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6381 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242585749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 242585749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242585749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242585749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242585749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242585749 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38016.885911 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38016.885911 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38016.885911 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38016.885911 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258665 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32635.252362 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 518921 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291402 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.780774 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258677 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32635.114541 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518852 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.780464 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2794.296231 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 67.207459 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29773.748672 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.085275 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002051 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.908623 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995949 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2797.134842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.663964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29769.315735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.085362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002095 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.908487 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995945 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32737 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5318 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26506 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5321 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26521 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999054 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7394486 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7394486 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3653 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 490457 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 494110 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91520 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91520 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2207 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2207 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3653 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492664 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 496317 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3653 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492664 # number of overall hits -system.cpu.l2cache.overall_hits::total 496317 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2751 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 222064 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224815 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66629 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66629 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288693 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291444 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2751 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288693 # number of overall misses -system.cpu.l2cache.overall_misses::total 291444 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 199081000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16245693500 # 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 371.002686 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354263250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.039658 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2496 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 242 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585486507 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585486507 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192472293 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192472293 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97380937 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97380937 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 19 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 19 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289853230 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289853230 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289853230 # number of overall hits -system.cpu.dcache.overall_hits::total 289853230 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1579063 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1579063 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 920263 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 920263 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2499326 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2499326 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2499326 # number of overall misses -system.cpu.dcache.overall_misses::total 2499326 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79789190750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79789190750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377622714 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57377622714 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137166813464 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137166813464 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137166813464 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137166813464 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194051356 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194051356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 585539447 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585539447 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192500682 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192500682 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97383359 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97383359 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 21 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 21 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289884041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289884041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289884041 # number of overall hits +system.cpu.dcache.overall_hits::total 289884041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1577144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1577144 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 917841 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 917841 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2494985 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2494985 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2494985 # number of overall misses +system.cpu.dcache.overall_misses::total 2494985 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79985151750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79985151750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57294656713 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57294656713 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137279808463 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137279808463 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137279808463 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137279808463 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194077826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194077826 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 19 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 19 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292352556 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292352556 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292352556 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292352556 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008137 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008137 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009362 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009362 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008549 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008549 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008549 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008549 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50529.453701 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50529.453701 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62349.157484 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62349.157484 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54881.521444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54881.521444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54881.521444 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 55443 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 471 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.690021 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 107.447674 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292379026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292379026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292379026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292379026 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008126 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008126 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009337 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009337 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008533 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008533 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008533 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008533 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50715.186280 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50715.186280 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62423.291957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62423.291957 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55022.298115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55022.298115 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21941 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 56666 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 465 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.184946 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 109.605416 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91520 # number of writebacks -system.cpu.dcache.writebacks::total 91520 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 866542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 866542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851427 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 851427 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1717969 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1717969 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1717969 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1717969 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712521 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712521 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68836 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68836 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781357 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781357 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781357 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781357 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21863154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21863154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5224164248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5224164248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27087318248 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27087318248 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27087318248 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27087318248 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks +system.cpu.dcache.writebacks::total 91488 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 864626 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 849006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 849006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1713632 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1713632 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1713632 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1713632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712518 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712518 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68835 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68835 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781353 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781353 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781353 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781353 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21854414000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21854414000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5217448748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5217448748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27071862748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27071862748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27071862748 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27071862748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002673 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002673 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002673 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30684.224044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30684.224044 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75892.908478 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75892.908478 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34667.019362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34667.019362 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30672.086881 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30672.086881 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75796.451631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75796.451631 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 2d72b8ec8..f8aa50083 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1843860 # Simulator instruction rate (inst/s) -host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 922130037 # Simulator tick rate (ticks/s) -host_mem_usage 234352 # Number of bytes of host memory used -host_seconds 503.61 # Real time elapsed on the host +host_inst_rate 2843750 # Simulator instruction rate (inst/s) +host_op_rate 2843750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1422183537 # Simulator tick rate (ticks/s) +host_mem_usage 289848 # Number of bytes of host memory used +host_seconds 326.54 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1588466830 # Wr system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 13156831461 # Throughput (bytes/s) -system.membus.data_through_bus 6109961839 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution +system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution +system.membus.trans_dist::WriteReq 98301200 # Transaction distribution +system.membus.trans_dist::WriteResp 98301200 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram +system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram +system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1264600947 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 9f0d0f3c5..8acd26381 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.286250 # Nu sim_ticks 1286249820000 # Number of ticks simulated final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 839019 # Simulator instruction rate (inst/s) -host_op_rate 839019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1162182391 # Simulator tick rate (ticks/s) -host_mem_usage 244120 # Number of bytes of host memory used -host_seconds 1106.75 # Real time elapsed on the host +host_inst_rate 1681245 # Simulator instruction rate (inst/s) +host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2328806930 # Simulator tick rate (ticks/s) +host_mem_usage 298588 # Number of bytes of host memory used +host_seconds 552.32 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 17781280 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 224031 # Transaction distribution system.membus.trans_dist::ReadResp 224031 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 66648 # Tr system.membus.trans_dist::ReadExResp 66648 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22871168 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 357362 # Request fanout histogram system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) @@ -486,7 +494,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution @@ -495,11 +502,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 878356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 878356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 878356 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index dc7a25182..ff20ac42e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.537826 # Nu sim_ticks 537826498500 # Number of ticks simulated final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114564 # Simulator instruction rate (inst/s) -host_op_rate 141043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96175687 # Simulator tick rate (ticks/s) -host_mem_usage 263048 # Number of bytes of host memory used -host_seconds 5592.13 # Real time elapsed on the host +host_inst_rate 160425 # Simulator instruction rate (inst/s) +host_op_rate 197504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134676016 # Simulator tick rate (ticks/s) +host_mem_usage 315984 # Number of bytes of host memory used +host_seconds 3993.48 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,30 +36,30 @@ system.physmem.readReqs 290531 # Nu system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18283 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts +system.physmem.perBankRdBursts::0 18291 # Per bank write bursts +system.physmem.perBankRdBursts::1 18140 # Per bank write bursts system.physmem.perBankRdBursts::2 18223 # Per bank write bursts -system.physmem.perBankRdBursts::3 18187 # Per bank write bursts -system.physmem.perBankRdBursts::4 18258 # Per bank write bursts -system.physmem.perBankRdBursts::5 18313 # Per bank write bursts -system.physmem.perBankRdBursts::6 18090 # Per bank write bursts -system.physmem.perBankRdBursts::7 17910 # Per bank write bursts -system.physmem.perBankRdBursts::8 17943 # Per bank write bursts -system.physmem.perBankRdBursts::9 17966 # Per bank write bursts -system.physmem.perBankRdBursts::10 18023 # Per bank write bursts -system.physmem.perBankRdBursts::11 18118 # Per bank write bursts -system.physmem.perBankRdBursts::12 18159 # Per bank write bursts -system.physmem.perBankRdBursts::13 18277 # Per bank write bursts -system.physmem.perBankRdBursts::14 18081 # Per bank write bursts -system.physmem.perBankRdBursts::15 18260 # Per bank write bursts +system.physmem.perBankRdBursts::3 18183 # Per bank write bursts +system.physmem.perBankRdBursts::4 18268 # Per bank write bursts +system.physmem.perBankRdBursts::5 18315 # Per bank write bursts +system.physmem.perBankRdBursts::6 18099 # Per bank write bursts +system.physmem.perBankRdBursts::7 17920 # Per bank write bursts +system.physmem.perBankRdBursts::8 17939 # Per bank write bursts +system.physmem.perBankRdBursts::9 17964 # Per bank write bursts +system.physmem.perBankRdBursts::10 18020 # Per bank write bursts +system.physmem.perBankRdBursts::11 18110 # Per bank write bursts +system.physmem.perBankRdBursts::12 18148 # Per bank write bursts +system.physmem.perBankRdBursts::13 18270 # Per bank write bursts +system.physmem.perBankRdBursts::14 18079 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4102 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts @@ -67,13 +67,13 @@ system.physmem.perBankWrBursts::3 4147 # Pe system.physmem.perBankWrBursts::4 4225 # Per bank write bursts system.physmem.perBankWrBursts::5 4225 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4094 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::10 4091 # Per bank write bursts +system.physmem.perBankWrBursts::11 4094 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry @@ -93,7 +93,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -140,8 +140,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see @@ -149,15 +149,15 @@ system.physmem.wrQLenPdf::20 4008 # Wh system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,44 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads -system.physmem.totQLat 3341298000 # Total ticks spent queuing -system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads +system.physmem.totQLat 3341982750 # Total ticks spent queuing +system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s @@ -236,19 +236,18 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing -system.physmem.readRowHits 194846 # Number of row buffer hits during reads -system.physmem.writeRowHits 49995 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing +system.physmem.readRowHits 194589 # Number of row buffer hits during reads +system.physmem.writeRowHits 50052 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes system.physmem.avgGap 1508083.78 # Average gap between requests -system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states +system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states system.physmem.memoryStateTime::REF 17958980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states +system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 42437954 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 224439 # Transaction distribution system.membus.trans_dist::ReadResp 224439 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution @@ -256,13 +255,22 @@ system.membus.trans_dist::ReadExReq 66092 # Tr system.membus.trans_dist::ReadExResp 66092 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22824256 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 356629 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 356629 # Request fanout histogram +system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 154837020 # Number of BP lookups @@ -368,17 +376,17 @@ system.cpu.discardedOps 25219021 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.678989 # CPI: cycles per instruction system.cpu.ipc 0.595596 # IPC: instructions per cycle -system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked -system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked +system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 23597 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id @@ -398,12 +406,12 @@ system.cpu.icache.demand_misses::cpu.inst 25348 # n system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses system.cpu.icache.overall_misses::total 25348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses @@ -416,12 +424,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,26 +444,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25348 system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 428895254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution @@ -464,28 +471,42 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38571746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224928725 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.l2cache.tags.replacements 257750 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32583.011088 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2866.114553 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906888 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994355 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id @@ -513,14 +534,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 290561 # system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses system.cpu.l2cache.overall_misses::total 290561 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16739408750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16739408750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) @@ -539,14 +560,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,14 +592,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13904175250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13904175250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3593710250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3593710250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497885500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17497885500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497885500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17497885500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses @@ -587,14 +608,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 778324 # number of replacements system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use @@ -634,14 +655,14 @@ system.cpu.dcache.demand_misses::cpu.inst 851434 # n system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses system.cpu.dcache.overall_misses::total 851434 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23700601220 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23700601220 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9183787250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9183787250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32884388470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32884388470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32884388470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32884388470 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) @@ -662,14 +683,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,14 +717,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22188801525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses @@ -712,14 +733,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e42758d84..9c87a9d2e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.297198 # Number of seconds simulated -sim_ticks 297198275500 # Number of ticks simulated -final_tick 297198275500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.407884 # Number of seconds simulated +sim_ticks 407883784500 # Number of ticks simulated +final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98901 # Simulator instruction rate (inst/s) -host_op_rate 121761 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45880544 # Simulator tick rate (ticks/s) -host_mem_usage 261988 # Number of bytes of host memory used -host_seconds 6477.65 # Real time elapsed on the host +host_inst_rate 87874 # Simulator instruction rate (inst/s) +host_op_rate 108185 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55946898 # Simulator tick rate (ticks/s) +host_mem_usage 2562780 # Number of bytes of host memory used +host_seconds 7290.55 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 150208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18436864 # Number of bytes read from this memory -system.physmem.bytes_read::total 18587072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 150208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 150208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288076 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290423 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 505413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62035569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 62540982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 505413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 14233838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 14233838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 14233838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 505413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62035569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 76774820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290424 # Number of read requests accepted -system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290424 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18565376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18587136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2334 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18318 # Per bank write bursts -system.physmem.perBankRdBursts::1 18131 # Per bank write bursts -system.physmem.perBankRdBursts::2 18196 # Per bank write bursts -system.physmem.perBankRdBursts::3 18163 # Per bank write bursts -system.physmem.perBankRdBursts::4 18256 # Per bank write bursts -system.physmem.perBankRdBursts::5 18279 # Per bank write bursts -system.physmem.perBankRdBursts::6 18091 # Per bank write bursts -system.physmem.perBankRdBursts::7 17906 # Per bank write bursts -system.physmem.perBankRdBursts::8 17946 # Per bank write bursts -system.physmem.perBankRdBursts::9 17953 # Per bank write bursts -system.physmem.perBankRdBursts::10 18007 # Per bank write bursts -system.physmem.perBankRdBursts::11 18104 # Per bank write bursts -system.physmem.perBankRdBursts::12 18147 # Per bank write bursts -system.physmem.perBankRdBursts::13 18252 # Per bank write bursts -system.physmem.perBankRdBursts::14 18085 # Per bank write bursts -system.physmem.perBankRdBursts::15 18250 # Per bank write bursts -system.physmem.perBankWrBursts::0 4173 # Per bank write bursts -system.physmem.perBankWrBursts::1 4100 # Per bank write bursts -system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts -system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4170 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4094 # Per bank write bursts -system.physmem.perBankWrBursts::9 4091 # Per bank write bursts -system.physmem.perBankWrBursts::10 4093 # Per bank write bursts -system.physmem.perBankWrBursts::11 4095 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 63360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6867584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 13490752 # Number of bytes read from this memory +system.physmem.bytes_read::total 20421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4243968 # Number of bytes written to this memory +system.physmem.bytes_written::total 4243968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 107306 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 210793 # Number of read requests responded to by this memory +system.physmem.num_reads::total 319089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66312 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66312 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 155338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16837110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 33074990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50067438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155338 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10404846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10404846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10404846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16837110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 33074990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60472284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 319089 # Number of read requests accepted +system.physmem.writeReqs 66312 # Number of write requests accepted +system.physmem.readBursts 319089 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66312 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20403200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20421696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4243968 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 20089 # Per bank write bursts +system.physmem.perBankRdBursts::1 19545 # Per bank write bursts +system.physmem.perBankRdBursts::2 20086 # Per bank write bursts +system.physmem.perBankRdBursts::3 20646 # Per bank write bursts +system.physmem.perBankRdBursts::4 19933 # Per bank write bursts +system.physmem.perBankRdBursts::5 20704 # Per bank write bursts +system.physmem.perBankRdBursts::6 19571 # Per bank write bursts +system.physmem.perBankRdBursts::7 19471 # Per bank write bursts +system.physmem.perBankRdBursts::8 19556 # Per bank write bursts +system.physmem.perBankRdBursts::9 19505 # Per bank write bursts +system.physmem.perBankRdBursts::10 19502 # Per bank write bursts +system.physmem.perBankRdBursts::11 20173 # Per bank write bursts +system.physmem.perBankRdBursts::12 19634 # Per bank write bursts +system.physmem.perBankRdBursts::13 20280 # Per bank write bursts +system.physmem.perBankRdBursts::14 19577 # Per bank write bursts +system.physmem.perBankRdBursts::15 20528 # Per bank write bursts +system.physmem.perBankWrBursts::0 4247 # Per bank write bursts +system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.perBankWrBursts::2 4143 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4139 # Per bank write bursts +system.physmem.perBankWrBursts::15 4153 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 297198223500 # Total gap between requests +system.physmem.totGap 407883730500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290424 # Read request sizes (log2) +system.physmem.readPktSize::6 319089 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 235690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66312 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 124916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15700 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 644 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -144,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -193,93 +197,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 106390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 214.227653 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.234885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 270.519636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42398 39.85% 39.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42939 40.36% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9834 9.24% 89.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 319 0.30% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 247 0.23% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 237 0.22% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 324 0.30% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1664 1.56% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8428 7.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 106390 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.488651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.041584 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 505.320352 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.479421 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.458127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.855088 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3049 76.05% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 76.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 956 23.85% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads -system.physmem.totQLat 3531270750 # Total ticks spent queuing -system.physmem.totMemAccLat 8970345750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1450420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12173.27 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 138324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.138053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.082938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 199.804046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 55124 39.85% 39.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 58239 42.10% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14671 10.61% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 966 0.70% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1420 1.03% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1368 0.99% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1462 1.06% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1224 0.88% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3850 2.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 138324 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 67.829475 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.454654 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 482.917109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3981 99.10% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 5 0.12% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 3 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 2 0.05% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13824-14335 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.484690 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.435555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.421529 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3367 83.82% 83.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.22% 84.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 437 10.88% 94.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 79 1.97% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 37 0.92% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.45% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.55% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.32% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.07% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.07% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads +system.physmem.totQLat 9958454882 # Total ticks spent queuing +system.physmem.totMemAccLat 15935954882 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1594000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31237.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30923.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 62.47 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 14.23 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 62.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 14.23 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 49987.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 50.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.60 # Data bus utilization in percentage -system.physmem.busUtilRead 0.49 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.11 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 28.82 # Average write queue length when enqueuing -system.physmem.readRowHits 199840 # Number of row buffer hits during reads -system.physmem.writeRowHits 49907 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.50 # Row buffer hit rate for writes -system.physmem.avgGap 833604.16 # Average gap between requests -system.physmem.pageHitRate 70.12 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 84430805250 # Time in different power states -system.physmem.memoryStateTime::REF 9923940000 # Time in different power states +system.physmem.busUtil 0.47 # Data bus utilization in percentage +system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 219908 # Number of row buffer hits during reads +system.physmem.writeRowHits 26785 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.43 # Row buffer hit rate for writes +system.physmem.avgGap 1058335.94 # Average gap between requests +system.physmem.pageHitRate 64.07 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 155274651966 # Time in different power states +system.physmem.memoryStateTime::REF 13620100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 202838904750 # Time in different power states +system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 76774820 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 224345 # Transaction distribution -system.membus.trans_dist::ReadResp 224344 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2334 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2334 # Transaction distribution -system.membus.trans_dist::ReadExReq 66079 # Transaction distribution -system.membus.trans_dist::ReadExResp 66079 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 651613 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 651613 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22817344 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22817344 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22817344 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1003041500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2737822416 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 317731 # Transaction distribution +system.membus.trans_dist::ReadResp 317731 # Transaction distribution +system.membus.trans_dist::Writeback 66312 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19 # Transaction distribution +system.membus.trans_dist::UpgradeResp 19 # Transaction distribution +system.membus.trans_dist::ReadExReq 1358 # Transaction distribution +system.membus.trans_dist::ReadExResp 1358 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 704528 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 704528 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24665664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24665664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 385420 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 385420 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 385420 # Request fanout histogram +system.membus.reqLayer0.occupancy 968060850 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2930140600 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 271863224 # Number of BP lookups -system.cpu.branchPred.condPredicted 178425431 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15415799 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 186524109 # Number of BTB lookups -system.cpu.branchPred.BTBHits 146250524 # Number of BTB hits +system.cpu.branchPred.lookups 233961455 # Number of BP lookups +system.cpu.branchPred.condPredicted 161822903 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15515021 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121571694 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108258179 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 78.408376 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 34625446 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1929978 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.048836 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25034450 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300530 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -365,238 +398,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 594396552 # number of cpu cycles simulated +system.cpu.numCycles 815767570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 217387549 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1367579713 # Number of instructions fetch has processed -system.cpu.fetch.Branches 271863224 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 180875970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 338099313 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 30904558 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 628206 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6076291 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 207850438 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5507154 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 577643745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.955013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.177882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064710 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370072724 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652087 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 815611997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.839157 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 246926096 42.75% 42.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22334065 3.87% 46.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 58641984 10.15% 56.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13805206 2.39% 59.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 49967679 8.65% 67.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26102781 4.52% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32011884 5.54% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19377139 3.35% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 108476911 18.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134572174 16.50% 16.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 222502254 27.28% 43.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98076609 12.02% 55.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360460960 44.20% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 577643745 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457377 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.300787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 170543616 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 112383913 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 256390493 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22882666 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15443057 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 30474424 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9349 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1602087744 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25664 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15443057 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 180102309 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80879107 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 304937 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 269061579 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 31852756 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1553633601 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 27722 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3084329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 23262068 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5400130 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1588085164 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7592228001 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1750427089 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 56767331 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 815611997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286799 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.471100 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119967047 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 156830594 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662032 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38633655 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518669 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25180757 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13832 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248142745 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39968083 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518669 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176978211 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77349013 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209115 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464956606 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80600383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190653187 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25546667 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24946830 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267986 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40254462 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1692453 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225396135 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812466885 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358185264 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876472 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 713306934 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13108 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10964 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 53001201 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 494421032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 283375622 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 38186333 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 81232307 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1474584555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 16256 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1149612413 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2320605 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 685767226 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1987453954 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 577643745 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.990175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.969584 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 350617905 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7272 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 7264 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 108149104 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366119032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236098756 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1753479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5371728 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168565166 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017100859 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18396242 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379746204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032205063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 815611997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.247040 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084974 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197611085 34.21% 34.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85639840 14.83% 49.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 74707514 12.93% 61.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 82105787 14.21% 76.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 66954970 11.59% 87.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 40972938 7.09% 94.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18446421 3.19% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4764432 0.82% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 6440758 1.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 257903097 31.62% 31.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 228438073 28.01% 59.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215325690 26.40% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97769150 11.99% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16175979 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 577643745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 815611997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 853039 1.90% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 10574 0.02% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27015778 60.17% 62.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 17022674 37.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64512923 19.13% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18147 0.01% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155504488 46.10% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116641749 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 506618209 44.07% 44.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5850863 0.51% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 44.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1274977 0.11% 44.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3188014 0.28% 44.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550893 0.22% 45.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 45.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11539273 1.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 402298542 34.99% 81.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 216291642 18.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456383765 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195693 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550151 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478998 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322094029 31.67% 78.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215573019 21.19% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1149612413 # Type of FU issued -system.cpu.iq.rate 1.934083 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44902065 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.039058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2861318586 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2106127825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1031796042 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62772655 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 54292666 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 30270248 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1162493023 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32021455 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 23570591 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017100859 # Type of FU issued +system.cpu.iq.rate 1.246802 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337314196 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331643 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3143647062 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504776491 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934274751 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877091 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565761 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152451 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320604680 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810375 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960281 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 242180094 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1210 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 685580 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 154395126 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113878094 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1252 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107118260 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29018041 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 192 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23979 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15443057 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 78194989 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1280631 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1475233939 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 214769 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 494421032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 283375622 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 10516 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 630754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 23941 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 685580 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 16670086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506202 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17176288 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1116354859 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 386341523 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33257554 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15518669 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35328826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 675397 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168583078 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 366119032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236098756 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 121 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 678981 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437712 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784771 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19222483 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974757504 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303300667 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42343355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 633128 # number of nop insts executed -system.cpu.iew.exec_refs 593821006 # number of memory reference insts executed -system.cpu.iew.exec_branches 162537737 # Number of branches executed -system.cpu.iew.exec_stores 207479483 # Number of stores executed -system.cpu.iew.exec_rate 1.878131 # Inst execution rate -system.cpu.iew.wb_sent 1074811517 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1062066290 # cumulative count of insts written-back -system.cpu.iew.wb_producers 606518919 # num instructions producing a value -system.cpu.iew.wb_consumers 1092664472 # num instructions consuming a value +system.cpu.iew.exec_nop 5552 # number of nop insts executed +system.cpu.iew.exec_refs 497757295 # number of memory reference insts executed +system.cpu.iew.exec_branches 150614518 # Number of branches executed +system.cpu.iew.exec_stores 194456628 # Number of stores executed +system.cpu.iew.exec_rate 1.194896 # Inst execution rate +system.cpu.iew.wb_sent 963726633 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960427202 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536683301 # num instructions producing a value +system.cpu.iew.wb_consumers 893293358 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.786798 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555082 # average fanout of values written-back +system.cpu.iew.wb_rate 1.177329 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600792 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 686508704 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357423726 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15406577 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 485351634 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625069 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.327523 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15501335 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 764789514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.031303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.790973 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 210489753 43.37% 43.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 125850152 25.93% 69.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 47800480 9.85% 79.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 20690881 4.26% 83.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 22810841 4.70% 88.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8150144 1.68% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8105919 1.67% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 7050996 1.45% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 34402468 7.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 428726988 56.06% 56.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 171833427 22.47% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566428 9.62% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31619643 4.13% 92.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7902471 1.03% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14889027 1.95% 95.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7271717 0.95% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618968 0.87% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360845 2.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 485351634 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 764789514 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -642,462 +671,507 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 34402468 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1926179188 # The number of ROB reads -system.cpu.rob.rob_writes 3042778169 # The number of ROB writes -system.cpu.timesIdled 159779 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16752807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1888573713 # The number of ROB reads +system.cpu.rob.rob_writes 2343133825 # The number of ROB writes +system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.927803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.927803 # CPI: Total CPI of All Threads -system.cpu.ipc 1.077815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.077815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1132703521 # number of integer regfile reads -system.cpu.int_regfile_writes 646986163 # number of integer regfile writes -system.cpu.fp_regfile_reads 37276202 # number of floating regfile reads -system.cpu.fp_regfile_writes 27223952 # number of floating regfile writes -system.cpu.cc_regfile_reads 4371075707 # number of cc regfile reads -system.cpu.cc_regfile_writes 413227106 # number of cc regfile writes -system.cpu.misc_regfile_reads 814254354 # number of misc regfile reads +system.cpu.cpi 1.273345 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads +system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995802638 # number of integer regfile reads +system.cpu.int_regfile_writes 567917186 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794452598 # number of cc regfile reads +system.cpu.cc_regfile_writes 384905504 # number of cc regfile writes +system.cpu.misc_regfile_reads 715806131 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.toL2Bus.throughput 191669699 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 729385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 729383 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69311 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 26757 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1664338 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1691095 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 781440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 56032960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56814400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56814400 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 149504 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 537567000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22218748 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1220548813 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 10545 # number of replacements -system.cpu.icache.tags.tagsinuse 1626.781544 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 207828971 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12209 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17022.603899 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1626.781544 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.794327 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.794327 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1664 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1549 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 415715422 # Number of tag accesses -system.cpu.icache.tags.data_accesses 415715422 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 207833630 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 207833630 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 207833630 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 207833630 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 207833630 # number of overall hits -system.cpu.icache.overall_hits::total 207833630 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16808 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16808 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16808 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16808 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16808 # number of overall misses -system.cpu.icache.overall_misses::total 16808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 373718245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 373718245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 373718245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 373718245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 373718245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 373718245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 207850438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 207850438 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 207850438 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 207850438 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 207850438 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 207850438 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000081 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000081 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000081 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000081 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000081 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000081 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22234.545752 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22234.545752 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22234.545752 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22234.545752 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22234.545752 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1690 # number of cycles access was blocked +system.cpu.toL2Bus.trans_dist::ReadReq 7205652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7205652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 9840757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339627 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248397 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16588024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330867456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223467584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554335040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 9840776 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18503299 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.531838 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.498985 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 8662542 46.82% 46.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 9840757 53.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18503299 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5066671498 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7754858551 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4142472532 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 5169293 # number of replacements +system.cpu.icache.tags.tagsinuse 510.870067 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364901080 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.583169 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 199337500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.870067 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997793 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 325 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 745315243 # Number of tag accesses +system.cpu.icache.tags.data_accesses 745315243 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 364901109 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 364901109 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 364901109 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 364901109 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 364901109 # number of overall hits +system.cpu.icache.overall_hits::total 364901109 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5171601 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5171601 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5171601 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5171601 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5171601 # number of overall misses +system.cpu.icache.overall_misses::total 5171601 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41478755019 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41478755019 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41478755019 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41478755019 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41478755019 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41478755019 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370072710 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370072710 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370072710 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370072710 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370072710 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370072710 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8020.486310 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8020.486310 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8020.486310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8020.486310 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17792 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1782 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9.984287 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2261 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2261 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2261 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2261 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2261 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2261 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14547 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 14547 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 14547 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 14547 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 14547 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 14547 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 287782750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 287782750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 287782750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 287782750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 287782750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 287782750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19782.962123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19782.962123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19782.962123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19782.962123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19782.962123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19782.962123 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1778 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1778 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1778 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1778 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1778 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1778 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169823 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5169823 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169823 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169823 # 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Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.528158 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 12938833000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 727.090986 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.045333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8487.644412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 7101.130766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.044378 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002993 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.518045 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.433419 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998835 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 7180 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 9190 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 246 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1499 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 5110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2000 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6801 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13558547000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 23342334 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 23342334 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4297620250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4297620250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 142668750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17713498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17856167250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 142668750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17713498500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17856167250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.310557 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308569 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998716 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.998716 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953370 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953370 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.364689 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192204 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.367375 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.364689 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60787.707712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.428445 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60436.145223 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65037.610285 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65037.610285 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.707712 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61488.763421 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61483.097988 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 66312 # number of writebacks +system.cpu.l2cache.writebacks::total 66312 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 534 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1182 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92793756 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71873499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6496975004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6568848503 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71873499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6496975004 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26000818687 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.052042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.014841 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.950000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.950000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.013663 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1.240312 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72599.493939 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60446.457205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60558.966382 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 1998.554582 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 7553.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 7553.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68331.189985 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68331.189985 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.427781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 2644.695771 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 780052 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.850454 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 456274938 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 784148 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 581.873496 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 340792000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.850454 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 976 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2364 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 451 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 2756164 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.948880 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414248795 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756676 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.271122 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 207459500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.948880 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 918547346 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 918547346 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 328318489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 328318489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127934774 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127934774 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3905 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3905 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5745 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5745 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 839347154 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347154 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286297439 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286297439 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127936631 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127936631 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 456253263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 456253263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 456257168 # number of overall hits -system.cpu.dcache.overall_hits::total 456257168 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1596085 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1596085 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1016703 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1016703 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 156 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 156 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414234070 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414234070 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414237227 # number of overall hits +system.cpu.dcache.overall_hits::total 414237227 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031039 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031039 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1014846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1014846 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 648 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 648 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2612788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2612788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2612944 # number of overall misses -system.cpu.dcache.overall_misses::total 2612944 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65672832321 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65672832321 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69021730126 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69021730126 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 134694562447 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 134694562447 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 134694562447 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 134694562447 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 329914574 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 329914574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4045885 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4045885 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4046533 # number of overall misses +system.cpu.dcache.overall_misses::total 4046533 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33719933619 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33719933619 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9704111685 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9704111685 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 169500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 169500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 43424045304 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43424045304 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43424045304 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43424045304 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328478 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 4061 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 4061 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5748 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3805 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3805 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 458866051 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 458866051 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 458870112 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 458870112 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004838 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004838 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007884 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038414 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038414 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000522 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005694 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005694 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005694 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005694 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41146.199808 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41146.199808 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67887.800199 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67887.800199 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51552.044195 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51552.044195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51548.966395 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51548.966395 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3326 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 660 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.194444 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 418279955 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279955 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283760 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010476 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010476 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007870 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007870 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170302 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.170302 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009673 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009673 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009674 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009674 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11124.876196 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11124.876196 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9562.151977 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9562.151977 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10732.891643 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10732.891643 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10731.172909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10731.172909 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 339239 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5513 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.534373 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91367 # number of writebacks -system.cpu.dcache.writebacks::total 91367 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881385 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 881385 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 945064 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 945064 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735005 # number of writebacks +system.cpu.dcache.writebacks::total 735005 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995853 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 995853 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293979 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 293979 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1826449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1826449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1826449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1826449 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 714700 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 714700 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71639 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71639 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 147 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 147 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 786339 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 786339 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 786486 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 786486 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21837733771 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21837733771 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5293200916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293200916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2189000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2189000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27130934687 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27130934687 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27133123687 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27133123687 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000556 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000556 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.036198 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.036198 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001714 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001714 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001714 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30555.105318 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30555.105318 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73887.141306 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73887.141306 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14891.156463 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14891.156463 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.847610 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34502.847610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34499.182041 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34499.182041 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1289832 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1289832 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1289832 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1289832 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720867 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720867 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 643 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 643 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2756053 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756696 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756696 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20990186992 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20990186992 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5237168826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5237168826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5228000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5228000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26227355818 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26227355818 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26232583818 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26232583818 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168988 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168988 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10313.645530 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10313.645530 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7265.097204 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7265.097204 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8130.637636 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8130.637636 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9516.274113 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9516.274113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9515.950913 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9515.950913 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index a6a0dd3a8..ffaf59dc8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 935276 # Simulator instruction rate (inst/s) -host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 577711928 # Simulator tick rate (ticks/s) -host_mem_usage 250216 # Number of bytes of host memory used -host_seconds 684.99 # Real time elapsed on the host +host_inst_rate 1695212 # Simulator instruction rate (inst/s) +host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1047118075 # Simulator tick rate (ticks/s) +host_mem_usage 304696 # Number of bytes of host memory used +host_seconds 377.92 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 1322421029 # Wr system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10718373779 # Throughput (bytes/s) -system.membus.data_through_bus 4241547521 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 893703777 # Transaction distribution +system.membus.trans_dist::ReadResp 893709516 # Transaction distribution +system.membus.trans_dist::WriteReq 128951477 # Transaction distribution +system.membus.trans_dist::WriteResp 128951477 # Transaction distribution +system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution +system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram +system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 1022670352 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index d4c7242b6..6d64061d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.043695 # Nu sim_ticks 1043695084000 # Number of ticks simulated final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 520727 # Simulator instruction rate (inst/s) -host_op_rate 639745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 850028397 # Simulator tick rate (ticks/s) -host_mem_usage 259968 # Number of bytes of host memory used -host_seconds 1227.84 # Real time elapsed on the host +host_inst_rate 974812 # Simulator instruction rate (inst/s) +host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1591272225 # Simulator tick rate (ticks/s) +host_mem_usage 314196 # Number of bytes of host memory used +host_seconds 655.89 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 4053168 # To system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 21818480 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 223619 # Transaction distribution system.membus.trans_dist::ReadResp 223619 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 66093 # Tr system.membus.trans_dist::ReadExResp 66093 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22771840 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 355811 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 355811 # Request fanout histogram system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) @@ -569,7 +577,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution @@ -578,11 +585,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) |