diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/40.perlbmk | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/40.perlbmk')
6 files changed, 2857 insertions, 2837 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index dc4595f22..1ecb81d4d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.560940 # Number of seconds simulated -sim_ticks 560939659000 # Number of ticks simulated -final_tick 560939659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.560955 # Number of seconds simulated +sim_ticks 560955232000 # Number of ticks simulated +final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 314051 # Simulator instruction rate (inst/s) -host_op_rate 314051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189670339 # Simulator tick rate (ticks/s) -host_mem_usage 308244 # Number of bytes of host memory used -host_seconds 2957.45 # Real time elapsed on the host +host_inst_rate 340981 # Simulator instruction rate (inst/s) +host_op_rate 340981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205940379 # Simulator tick rate (ticks/s) +host_mem_usage 308844 # Number of bytes of host memory used +host_seconds 2723.87 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18514112 # Number of bytes read from this memory -system.physmem.bytes_read::total 18700928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 184896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18519872 # Number of bytes read from this memory +system.physmem.bytes_read::total 18704768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 184896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 184896 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289283 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289373 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292262 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33005532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33338573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7608148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7608148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7608148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33005532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40946722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292202 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 329609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33014884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33344493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 329609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 329609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7607937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7607937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7607937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 329609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33014884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40952430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292262 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292202 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292262 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18682112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18700928 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18684608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18704768 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18035 # Per bank write bursts -system.physmem.perBankRdBursts::1 18362 # Per bank write bursts -system.physmem.perBankRdBursts::2 18392 # Per bank write bursts -system.physmem.perBankRdBursts::3 18337 # Per bank write bursts -system.physmem.perBankRdBursts::4 18250 # Per bank write bursts -system.physmem.perBankRdBursts::5 18249 # Per bank write bursts -system.physmem.perBankRdBursts::6 18316 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18228 # Per bank write bursts -system.physmem.perBankRdBursts::10 18207 # Per bank write bursts -system.physmem.perBankRdBursts::11 18382 # Per bank write bursts -system.physmem.perBankRdBursts::12 18252 # Per bank write bursts -system.physmem.perBankRdBursts::13 18131 # Per bank write bursts -system.physmem.perBankRdBursts::14 18059 # Per bank write bursts -system.physmem.perBankRdBursts::15 18183 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191173 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18033 # Per bank write bursts +system.physmem.perBankRdBursts::1 18359 # Per bank write bursts +system.physmem.perBankRdBursts::2 18394 # Per bank write bursts +system.physmem.perBankRdBursts::3 18332 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18255 # Per bank write bursts +system.physmem.perBankRdBursts::6 18314 # Per bank write bursts +system.physmem.perBankRdBursts::7 18296 # Per bank write bursts +system.physmem.perBankRdBursts::8 18227 # Per bank write bursts +system.physmem.perBankRdBursts::9 18236 # Per bank write bursts +system.physmem.perBankRdBursts::10 18229 # Per bank write bursts +system.physmem.perBankRdBursts::11 18376 # Per bank write bursts +system.physmem.perBankRdBursts::12 18263 # Per bank write bursts +system.physmem.perBankRdBursts::13 18132 # Per bank write bursts +system.physmem.perBankRdBursts::14 18061 # Per bank write bursts +system.physmem.perBankRdBursts::15 18191 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4186 # Per bank write bursts +system.physmem.perBankWrBursts::9 4192 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 560939577000 # Total gap between requests +system.physmem.totGap 560955208000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292202 # Read request sizes (log2) +system.physmem.readPktSize::6 292262 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4051 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,43 +193,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 220.607081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.832345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.107277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 38319 36.84% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43999 42.30% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8903 8.56% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 723 0.70% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 104067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 220.533003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.789866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.043159 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 38344 36.85% 36.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44004 42.28% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8921 8.57% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 721 0.69% 88.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1372 1.32% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1141 1.10% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 666 0.64% 91.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 599 0.58% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8297 7.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104019 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.696468 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.574169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 760.359503 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 3 0.07% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 3 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::640-767 1145 1.10% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 668 0.64% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 598 0.57% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8294 7.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104067 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.768889 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.564435 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 763.185509 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.78% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.463818 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.443063 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.844207 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3110 76.81% 76.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 939 23.19% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 2923147000 # Total ticks spent queuing -system.physmem.totMemAccLat 8396422000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10013.93 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4050 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.461235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.440549 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.842853 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3116 76.94% 76.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 932 23.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4050 # Writes before turning the bus around for reads +system.physmem.totQLat 2934449500 # Total ticks spent queuing +system.physmem.totMemAccLat 8408455750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459735000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10051.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28763.93 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28801.31 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s @@ -239,71 +243,71 @@ system.physmem.busUtil 0.32 # Da system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.30 # Average write queue length when enqueuing -system.physmem.readRowHits 202517 # Number of row buffer hits during reads -system.physmem.writeRowHits 52027 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.02 # Row buffer hit rate for writes -system.physmem.avgGap 1563006.47 # Average gap between requests +system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing +system.physmem.readRowHits 202530 # Number of row buffer hits during reads +system.physmem.writeRowHits 52011 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes +system.physmem.avgGap 1562788.75 # Average gap between requests system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 392311080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 214058625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140422400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140391200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109190821365 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240780947250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388572678720 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.720364 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 399879041250 # Time in different power states -system.physmem_0.memoryStateTime::REF 18730920000 # Time in different power states +system.physmem_0.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 109486358955 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240531047250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388619465820 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.784540 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 399461576500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18731440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142327335000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142759852250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 394019640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 214990875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136187000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215531280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109681250220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240350746500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388630405035 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.823275 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399158044000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18730920000 # Time in different power states +system.physmem_1.actEnergy 394276680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 215131125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136522400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 109506441195 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240513431250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388620069450 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.785616 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399429681750 # Time in different power states +system.physmem_1.memoryStateTime::REF 18731440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 143048821000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 142792236250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125747730 # Number of BP lookups -system.cpu.branchPred.condPredicted 81143399 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12156451 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103980487 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83512673 # Number of BTB hits +system.cpu.branchPred.lookups 125747709 # Number of BP lookups +system.cpu.branchPred.condPredicted 81143389 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12156447 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103980471 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83512685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.315716 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691015 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.315740 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691016 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537770 # DTB read hits +system.cpu.dtb.read_hits 237537764 # DTB read hits system.cpu.dtb.read_misses 198464 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736234 # DTB read accesses -system.cpu.dtb.write_hits 98304947 # DTB write hits +system.cpu.dtb.read_accesses 237736228 # DTB read accesses +system.cpu.dtb.write_hits 98304946 # DTB write hits system.cpu.dtb.write_misses 7177 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312124 # DTB write accesses -system.cpu.dtb.data_hits 335842717 # DTB hits +system.cpu.dtb.write_accesses 98312123 # DTB write accesses +system.cpu.dtb.data_hits 335842710 # DTB hits system.cpu.dtb.data_misses 205641 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048358 # DTB accesses -system.cpu.itb.fetch_hits 316984864 # ITB hits +system.cpu.dtb.data_accesses 336048351 # DTB accesses +system.cpu.itb.fetch_hits 316984906 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316984984 # ITB accesses +system.cpu.itb.fetch_accesses 316985026 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,24 +321,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1121879318 # number of cpu cycles simulated +system.cpu.numCycles 1121910464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30861365 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30861351 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.207895 # CPI: cycles per instruction -system.cpu.ipc 0.827887 # IPC: instructions per cycle -system.cpu.tickCycles 1059707231 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62172087 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.207928 # CPI: cycles per instruction +system.cpu.ipc 0.827864 # IPC: instructions per cycle +system.cpu.tickCycles 1059707465 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62202999 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776530 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.727909 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322866545 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.728000 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322866540 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599528 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 413.599521 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 898816500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.727909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.728000 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999201 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999201 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -344,40 +348,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 951 system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648211884 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648211884 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224702500 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224702500 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164045 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164045 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322866545 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322866545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322866545 # number of overall hits -system.cpu.dcache.overall_hits::total 322866545 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648211872 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648211872 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224702494 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224702494 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164046 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322866540 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322866540 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322866540 # number of overall hits +system.cpu.dcache.overall_hits::total 322866540 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137155 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137155 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849084 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849084 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849084 # number of overall misses -system.cpu.dcache.overall_misses::total 849084 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24888766500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24888766500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9955853000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9955853000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34844619500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34844619500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34844619500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34844619500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225414429 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225414429 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849083 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849083 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849083 # number of overall misses +system.cpu.dcache.overall_misses::total 849083 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24904735500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24904735500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9954481000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9954481000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34859216500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34859216500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34859216500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34859216500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225414423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225414423 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323715629 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323715629 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323715629 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323715629 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 323715623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323715623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323715623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323715623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -386,14 +390,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.618866 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.618866 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72588.334366 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72588.334366 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41037.894366 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41037.894366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41037.894366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41037.894366 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41055.134186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41055.134186 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,16 +406,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88852 # number of writebacks -system.cpu.dcache.writebacks::total 88852 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88497 # number of writebacks +system.cpu.dcache.writebacks::total 88497 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68144 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68144 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68458 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68458 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68458 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68458 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68143 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68457 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68457 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68457 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68457 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -420,14 +424,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780626 system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24170053000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24170053000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993475000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993475000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29163528000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29163528000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29163528000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29163528000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24185998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24185998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4992658500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4992658500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29178656500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29178656500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29178656500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29178656500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -436,69 +440,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33965.069595 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33965.069595 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72357.667618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72357.667618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37359.155345 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37359.155345 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37359.155345 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37359.155345 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10565 # number of replacements -system.cpu.icache.tags.tagsinuse 1685.376392 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316972557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12306 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25757.561921 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10567 # number of replacements +system.cpu.icache.tags.tagsinuse 1685.376446 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316972597 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12308 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25753.379672 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376392 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376446 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.822938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.822938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1571 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633982034 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633982034 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316972557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316972557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316972557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316972557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316972557 # number of overall hits -system.cpu.icache.overall_hits::total 316972557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12307 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12307 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12307 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12307 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12307 # number of overall misses -system.cpu.icache.overall_misses::total 12307 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 350414000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 350414000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 350414000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 350414000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 350414000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 350414000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316984864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316984864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316984864 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316984864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316984864 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316984864 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 633982120 # Number of tag accesses +system.cpu.icache.tags.data_accesses 633982120 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 316972597 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 316972597 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 316972597 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 316972597 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 316972597 # number of overall hits +system.cpu.icache.overall_hits::total 316972597 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12309 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12309 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12309 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12309 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12309 # number of overall misses +system.cpu.icache.overall_misses::total 12309 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 349738000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 349738000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 349738000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 349738000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 349738000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 349738000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 316984906 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 316984906 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 316984906 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28472.739092 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28472.739092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28472.739092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28472.739092 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28413.193598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28413.193598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,129 +511,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12307 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12307 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12307 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12307 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 338108000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 338108000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 338108000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 338108000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 338108000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 338108000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 10567 # number of writebacks +system.cpu.icache.writebacks::total 10567 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12309 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12309 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12309 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12309 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12309 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 337430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 337430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337430000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 337430000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27472.820346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27472.820346 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27472.820346 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27472.820346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27472.820346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27472.820346 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27413.274840 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27413.274840 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259423 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32592.990901 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218275 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292159 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.169904 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259935 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32594.451091 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218218 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292671 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.162414 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2589.705025 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 83.650991 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29919.634886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.079032 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002553 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2659 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29473 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2660 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29372 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13001394 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13001394 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 88852 # 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number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9419 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491253 # number of overall hits +system.cpu.l2cache.overall_hits::total 500672 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2920 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2920 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222638 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222638 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2920 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289283 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292203 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2920 # 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miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.234788 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312989 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312989 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.234788 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370694 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368584 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.234788 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370694 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368584 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.793533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.793533 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76148.269896 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76148.269896 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80749.824899 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80749.824899 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76148.269896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78962.164749 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78934.339961 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76148.269896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78962.164749 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78934.339961 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,120 +650,121 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 452 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 452 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19940615500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20132511000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2890 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2890 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222728 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222728 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2890 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289373 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292263 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2890 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289373 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 191178500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19955788500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20146967000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312863 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312863 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370578 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368509 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370578 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368509 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63000.045015 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63000.045015 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65717.636986 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65717.636986 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70706.606689 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70706.606689 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65717.636986 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.234788 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312989 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312989 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368584 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368584 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1580028 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 1580032 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2077 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2079 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2079 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 723921 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155535 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 890983 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881285 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12309 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35184 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2372960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 787584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55646592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56434176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259423 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1839451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001129 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.033584 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 2372966 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259935 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1052870 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001975 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044393 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1837374 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2077 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050791 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2079 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1839451 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 878866000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052870 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889080000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18459000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18462000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170939000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225557 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191114 # Transaction distribution +system.membus.trans_dist::ReadResp 225617 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191173 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225557 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842201 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842201 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22968640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22968640 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225617 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842380 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22972480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549999 # Request fanout histogram +system.membus.snoop_fanout::samples 550118 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 550118 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549999 # Request fanout histogram -system.membus.reqLayer0.occupancy 918564500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 550118 # Request fanout histogram +system.membus.reqLayer0.occupancy 918693000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556125250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556459000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4dbf3fd00..ba9bff2cb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.276406 # Number of seconds simulated -sim_ticks 276406029500 # Number of ticks simulated -final_tick 276406029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.276414 # Number of seconds simulated +sim_ticks 276414065500 # Number of ticks simulated +final_tick 276414065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172081 # Simulator instruction rate (inst/s) -host_op_rate 172081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56464121 # Simulator tick rate (ticks/s) -host_mem_usage 308248 # Number of bytes of host memory used -host_seconds 4895.25 # Real time elapsed on the host +host_inst_rate 180346 # Simulator instruction rate (inst/s) +host_op_rate 180346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59177560 # Simulator tick rate (ticks/s) +host_mem_usage 308352 # Number of bytes of host memory used +host_seconds 4670.93 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18519360 # Number of bytes read from this memory -system.physmem.bytes_read::total 18693312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 172736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18523584 # Number of bytes read from this memory +system.physmem.bytes_read::total 18696320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 172736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 172736 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289365 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289431 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292130 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 629335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 67000564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67629900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 629335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 629335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15440011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15440011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15440011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 629335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 67000564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 83069910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292083 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 624918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 67013898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67638816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 624918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 624918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15439562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15439562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15439562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 624918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 67013898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 83078377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292130 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292083 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292130 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18672064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18693312 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18675136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18696320 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18010 # Per bank write bursts -system.physmem.perBankRdBursts::1 18319 # Per bank write bursts -system.physmem.perBankRdBursts::2 18376 # Per bank write bursts -system.physmem.perBankRdBursts::3 18330 # Per bank write bursts -system.physmem.perBankRdBursts::4 18231 # Per bank write bursts -system.physmem.perBankRdBursts::5 18221 # Per bank write bursts -system.physmem.perBankRdBursts::6 18322 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18218 # Per bank write bursts -system.physmem.perBankRdBursts::10 18207 # Per bank write bursts -system.physmem.perBankRdBursts::11 18389 # Per bank write bursts -system.physmem.perBankRdBursts::12 18249 # Per bank write bursts -system.physmem.perBankRdBursts::13 18121 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191079 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18006 # Per bank write bursts +system.physmem.perBankRdBursts::1 18321 # Per bank write bursts +system.physmem.perBankRdBursts::2 18379 # Per bank write bursts +system.physmem.perBankRdBursts::3 18333 # Per bank write bursts +system.physmem.perBankRdBursts::4 18240 # Per bank write bursts +system.physmem.perBankRdBursts::5 18219 # Per bank write bursts +system.physmem.perBankRdBursts::6 18314 # Per bank write bursts +system.physmem.perBankRdBursts::7 18303 # Per bank write bursts +system.physmem.perBankRdBursts::8 18232 # Per bank write bursts +system.physmem.perBankRdBursts::9 18223 # Per bank write bursts +system.physmem.perBankRdBursts::10 18219 # Per bank write bursts +system.physmem.perBankRdBursts::11 18380 # Per bank write bursts +system.physmem.perBankRdBursts::12 18258 # Per bank write bursts +system.physmem.perBankRdBursts::13 18122 # Per bank write bursts system.physmem.perBankRdBursts::14 18052 # Per bank write bursts -system.physmem.perBankRdBursts::15 18183 # Per bank write bursts +system.physmem.perBankRdBursts::15 18198 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts +system.physmem.perBankWrBursts::9 4187 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 276405940000 # Total gap between requests +system.physmem.totGap 276414034500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292083 # Read request sizes (log2) +system.physmem.readPktSize::6 292130 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 216501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,121 +193,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 99437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 230.668262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.414135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 279.665008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 34391 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42842 43.08% 77.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10220 10.28% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 417 0.42% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 400 0.40% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 621 0.62% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 466 0.47% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1450 1.46% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8630 8.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 99437 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.663212 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.607328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 761.755251 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4044 99.78% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 99419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.737062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.797862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.058381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 34339 34.54% 34.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42571 42.82% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9880 9.94% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 767 0.77% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1066 1.07% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 606 0.61% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 182 0.18% 89.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1419 1.43% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8589 8.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 99419 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.841638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.476950 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 763.295063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.449050 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.428679 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.836709 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3145 77.60% 77.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 905 22.33% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads -system.physmem.totQLat 3647206250 # Total ticks spent queuing -system.physmem.totMemAccLat 9117537500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1458755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12501.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.443759 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.423618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.831866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3155 77.82% 77.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 77.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 896 22.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads +system.physmem.totQLat 3656274250 # Total ticks spent queuing +system.physmem.totMemAccLat 9127505500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1458995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12530.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31251.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 67.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.44 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.63 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31280.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 67.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 15.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.65 # Data bus utilization in percentage system.physmem.busUtilRead 0.53 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.13 # Average write queue length when enqueuing -system.physmem.readRowHits 206989 # Number of row buffer hits during reads -system.physmem.writeRowHits 51984 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 207034 # Number of row buffer hits during reads +system.physmem.writeRowHits 52000 # Number of row buffer hits during writes system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes -system.physmem.avgGap 770435.16 # Average gap between requests -system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 373947840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204039000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139408400 # Energy for read commands per rank (pJ) +system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes +system.physmem.avgGap 770356.80 # Average gap between requests +system.physmem.pageHitRate 72.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 374197320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204175125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139463000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18053371440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80174383695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 95514202500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 195675791355 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.933114 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158383013500 # Time in different power states -system.physmem_0.memoryStateTime::REF 9229740000 # Time in different power states +system.physmem_0.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80208829935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 95488658250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 195685642110 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.948810 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158328598000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9230000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108791696000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108853550750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 377742960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 206109750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1135890600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18053371440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80329865445 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 95377815000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 195696365355 # Total energy per rank (pJ) -system.physmem_1.averagePower 708.007549 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 158148138750 # Time in different power states -system.physmem_1.memoryStateTime::REF 9229740000 # Time in different power states +system.physmem_1.actEnergy 377342280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 205891125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136187000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80561309670 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 95179465500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 195729613335 # Total energy per rank (pJ) +system.physmem_1.averagePower 708.107889 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 157816922000 # Time in different power states +system.physmem_1.memoryStateTime::REF 9230000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109026483750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109365226750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192576076 # Number of BP lookups -system.cpu.branchPred.condPredicted 126054565 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11561227 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 137875170 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126274438 # Number of BTB hits +system.cpu.branchPred.lookups 192576024 # Number of BP lookups +system.cpu.branchPred.condPredicted 126054494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11561226 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 137875105 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126274367 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.586062 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28678363 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 136 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.586053 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28678385 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 133 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 242441387 # DTB read hits -system.cpu.dtb.read_misses 312131 # DTB read misses +system.cpu.dtb.read_hits 242441427 # DTB read hits +system.cpu.dtb.read_misses 312020 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 242753518 # DTB read accesses -system.cpu.dtb.write_hits 135445935 # DTB write hits +system.cpu.dtb.read_accesses 242753447 # DTB read accesses +system.cpu.dtb.write_hits 135445847 # DTB write hits system.cpu.dtb.write_misses 31631 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135477566 # DTB write accesses -system.cpu.dtb.data_hits 377887322 # DTB hits -system.cpu.dtb.data_misses 343762 # DTB misses +system.cpu.dtb.write_accesses 135477478 # DTB write accesses +system.cpu.dtb.data_hits 377887274 # DTB hits +system.cpu.dtb.data_misses 343651 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 378231084 # DTB accesses -system.cpu.itb.fetch_hits 194828154 # ITB hits -system.cpu.itb.fetch_misses 242 # ITB misses +system.cpu.dtb.data_accesses 378230925 # DTB accesses +system.cpu.itb.fetch_hits 194827904 # ITB hits +system.cpu.itb.fetch_misses 239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 194828396 # ITB accesses +system.cpu.itb.fetch_accesses 194828143 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,98 +320,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 552812060 # number of cpu cycles simulated +system.cpu.numCycles 552828132 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 198850471 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1637321626 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192576076 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 154952801 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341917067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 23591046 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 198849781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1637321417 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192576024 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 154952752 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341932468 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 23591048 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6993 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 6961 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 194828154 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7885913 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 552570202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 194827904 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7885927 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 552584882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963022 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176483 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236054473 42.72% 42.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29638362 5.36% 48.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21702458 3.93% 52.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 35773228 6.47% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67707960 12.25% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21595876 3.91% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19328628 3.50% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3978060 0.72% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 116791157 21.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236070631 42.72% 42.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29638226 5.36% 48.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21699661 3.93% 52.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 35773155 6.47% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67709217 12.25% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21596173 3.91% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19328814 3.50% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3978253 0.72% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 116790752 21.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 552570202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348357 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.961805 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 166802287 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 90542864 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 271199395 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12236841 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11788815 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15468328 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 552584882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.348347 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.961719 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 166809048 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 90546856 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 271205722 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12234440 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11788816 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15468258 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 6932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1567838176 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 24969 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11788815 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 173688859 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 60716441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13717 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276533617 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29828753 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1529250735 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8190 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2401406 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 20516503 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7198838 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1021411513 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1760089033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1720202399 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39886633 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 1567837184 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 24953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11788816 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 173694356 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 60697364 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276538556 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29852032 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1529249378 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8057 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2407484 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20532473 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7206116 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1021410389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1760087391 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1720201095 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39886295 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 382444355 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1364 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9081858 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 369185264 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 173801333 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40211283 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11128775 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1296786218 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 72 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1011356527 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8787388 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 454404260 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 422537101 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 35 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 552570202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.830277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.913640 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 382443231 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9068503 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 369184759 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 173801249 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40216404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11112363 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1296784829 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1011355981 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8787623 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 454402873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 422535596 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 552584882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.830227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.913668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197270443 35.70% 35.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90785192 16.43% 52.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 90547416 16.39% 68.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 58763251 10.63% 79.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 57064914 10.33% 89.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29634790 5.36% 94.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 16885134 3.06% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7510156 1.36% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4108906 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197292642 35.70% 35.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90775823 16.43% 52.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 90545836 16.39% 68.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 58767814 10.64% 79.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57065281 10.33% 89.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29635375 5.36% 94.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 16880319 3.05% 97.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7509205 1.36% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4112587 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 552570202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 552584882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2519726 10.56% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2519786 10.56% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available @@ -441,16 +440,16 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15983640 67.00% 77.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5352814 22.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15987276 67.00% 77.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5353537 22.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 577739239 57.13% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 577738940 57.13% 57.13% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7929 0.00% 57.13% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13232477 1.31% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13232476 1.31% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 3339799 0.33% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued @@ -475,84 +474,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 274563645 27.15% 86.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138645616 13.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 274563490 27.15% 86.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138645524 13.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1011356527 # Type of FU issued -system.cpu.iq.rate 1.829476 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23856180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023588 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2536915249 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1709850818 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 936642710 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 71011575 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41384719 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34526976 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 998747828 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36463603 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 49725855 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1011355981 # Type of FU issued +system.cpu.iq.rate 1.829422 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23860599 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023593 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2536933524 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1709848613 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 936642568 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 71011542 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41384153 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34526963 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 998751721 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36463583 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 49725864 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 131674667 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1209013 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 75500133 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 131674162 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1208593 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45366 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 75500049 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2715 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4018 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4217 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11788815 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59738270 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 197040 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1470367053 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17961 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 369185264 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 173801333 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 72 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15881 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 192528 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11555967 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 14465 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11570432 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 973002630 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 242753693 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 38353897 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11788816 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59730385 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 188341 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1470365584 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 369184759 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 173801249 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15707 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 184002 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45366 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11555966 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 14467 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11570433 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 973002254 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 242753622 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 38353727 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 173580763 # number of nop insts executed -system.cpu.iew.exec_refs 378231547 # number of memory reference insts executed -system.cpu.iew.exec_branches 128483828 # Number of branches executed -system.cpu.iew.exec_stores 135477854 # Number of stores executed -system.cpu.iew.exec_rate 1.760097 # Inst execution rate -system.cpu.iew.wb_sent 971735885 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 971169686 # cumulative count of insts written-back -system.cpu.iew.wb_producers 554962956 # num instructions producing a value -system.cpu.iew.wb_consumers 830927766 # num instructions consuming a value +system.cpu.iew.exec_nop 173580681 # number of nop insts executed +system.cpu.iew.exec_refs 378231388 # number of memory reference insts executed +system.cpu.iew.exec_branches 128483769 # Number of branches executed +system.cpu.iew.exec_stores 135477766 # Number of stores executed +system.cpu.iew.exec_rate 1.760045 # Inst execution rate +system.cpu.iew.wb_sent 971735602 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 971169531 # cumulative count of insts written-back +system.cpu.iew.wb_producers 554965093 # num instructions producing a value +system.cpu.iew.wb_consumers 830941176 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.756781 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667884 # average fanout of values written-back +system.cpu.iew.wb_rate 1.756730 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667875 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 534548617 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 534547076 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11554520 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 481206030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.929709 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.612045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11554519 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 481220935 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.929649 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.612057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 204042568 42.40% 42.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 101511322 21.10% 63.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52351761 10.88% 74.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25424969 5.28% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20905527 4.34% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8991227 1.87% 85.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10032438 2.08% 87.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6244738 1.30% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 51701480 10.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 204061483 42.40% 42.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 101508829 21.09% 63.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52351815 10.88% 74.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25424424 5.28% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20903892 4.34% 84.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8988981 1.87% 85.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10032197 2.08% 87.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6246270 1.30% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 51703044 10.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 481206030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 481220935 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -598,137 +597,137 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 51701480 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1890019657 # The number of ROB reads -system.cpu.rob.rob_writes 2997637733 # The number of ROB writes -system.cpu.timesIdled 3185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 241858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 51703044 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1890031457 # The number of ROB reads +system.cpu.rob.rob_writes 2997634424 # The number of ROB writes +system.cpu.timesIdled 3187 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 243250 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.656249 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.656249 # CPI: Total CPI of All Threads -system.cpu.ipc 1.523813 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.523813 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1234257247 # number of integer regfile reads -system.cpu.int_regfile_writes 703449538 # number of integer regfile writes -system.cpu.fp_regfile_reads 36844878 # number of floating regfile reads -system.cpu.fp_regfile_writes 24462480 # number of floating regfile writes +system.cpu.cpi 0.656268 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.656268 # CPI: Total CPI of All Threads +system.cpu.ipc 1.523768 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.523768 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1234256884 # number of integer regfile reads +system.cpu.int_regfile_writes 703449505 # number of integer regfile writes +system.cpu.fp_regfile_reads 36844868 # number of floating regfile reads +system.cpu.fp_regfile_writes 24462479 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777154 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.899235 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288564425 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781250 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 369.362464 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 369553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.899235 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999243 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999243 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777152 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.896824 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 288563683 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781248 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 369.362460 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 369982500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.896824 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2490 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 256 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 582801760 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 582801760 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 191156368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 191156368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408043 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408043 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 582801420 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 582801420 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 191154367 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 191154367 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97409302 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97409302 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 288564411 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 288564411 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 288564411 # number of overall hits -system.cpu.dcache.overall_hits::total 288564411 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1552672 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1552672 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 893157 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 893157 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 288563669 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 288563669 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 288563669 # number of overall hits +system.cpu.dcache.overall_hits::total 288563669 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554504 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554504 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 891898 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 891898 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2445829 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2445829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2445829 # number of overall misses -system.cpu.dcache.overall_misses::total 2445829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83271101000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83271101000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62352545333 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62352545333 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2446402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2446402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2446402 # number of overall misses +system.cpu.dcache.overall_misses::total 2446402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83607056000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83607056000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61973215333 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61973215333 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 82500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 82500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145623646333 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145623646333 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145623646333 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145623646333 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 192709040 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 192709040 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 145580271333 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145580271333 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145580271333 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145580271333 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 192708871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 192708871 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291010240 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291010240 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 291010240 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 291010240 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008057 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009086 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 291010071 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 291010071 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 291010071 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 291010071 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009073 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009073 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.066667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.066667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008405 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53630.838323 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53630.838323 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69811.405311 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69811.405311 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.008407 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008407 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008407 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008407 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53783.750959 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53783.750959 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69484.644357 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69484.644357 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 82500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 82500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59539.586101 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59539.586101 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59539.586101 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59539.586101 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22515 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 72899 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59507.910529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59507.910529 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23437 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 62248 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 339 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.026393 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 141.003868 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.135693 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 120.402321 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88880 # number of writebacks -system.cpu.dcache.writebacks::total 88880 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840227 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 840227 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824352 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 824352 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 88616 # number of writebacks +system.cpu.dcache.writebacks::total 88616 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842060 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842060 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823094 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 823094 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1664579 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1664579 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1664579 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1664579 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712445 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712445 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68805 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68805 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781250 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781250 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781250 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781250 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24193547500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24193547500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5688085497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5688085497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29881632997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29881632997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29881632997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29881632997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1665154 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1665154 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1665154 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1665154 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712444 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712444 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68804 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68804 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781248 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781248 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781248 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781248 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24228621500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24228621500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5666649497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5666649497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29895270997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29895270997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29895270997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29895270997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003697 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003697 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses @@ -737,69 +736,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002685 system.cpu.dcache.demand_mshr_miss_rate::total 0.002685 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33958.477497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33958.477497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82669.653325 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82669.653325 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38248.490236 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38248.490236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38248.490236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38248.490236 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34007.755697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34007.755697 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82359.303195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82359.303195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4598 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.391736 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 194819915 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6300 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30923.796032 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4602 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.296070 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 194819661 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6304 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30904.134042 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.391736 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801461 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801461 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.296070 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801414 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801414 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1702 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1535 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.831055 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 389662608 # Number of tag accesses -system.cpu.icache.tags.data_accesses 389662608 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 194819915 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 194819915 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 194819915 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 194819915 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 194819915 # number of overall hits -system.cpu.icache.overall_hits::total 194819915 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8239 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8239 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8239 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8239 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8239 # number of overall misses -system.cpu.icache.overall_misses::total 8239 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 351244499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 351244499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 351244499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 351244499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 351244499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 351244499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 194828154 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 194828154 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 194828154 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 194828154 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 194828154 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 194828154 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 389662112 # Number of tag accesses +system.cpu.icache.tags.data_accesses 389662112 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 194819661 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 194819661 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 194819661 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 194819661 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 194819661 # number of overall hits +system.cpu.icache.overall_hits::total 194819661 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8243 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8243 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8243 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8243 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8243 # number of overall misses +system.cpu.icache.overall_misses::total 8243 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 351192999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 351192999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 351192999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 351192999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 351192999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 351192999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 194827904 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 194827904 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 194827904 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 194827904 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 194827904 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 194827904 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42631.933366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42631.933366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42631.933366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42631.933366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42631.933366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42631.933366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42604.998059 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42604.998059 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42604.998059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42604.998059 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 510 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -808,135 +807,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 46.363636 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 4602 # number of writebacks +system.cpu.icache.writebacks::total 4602 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1938 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 1938 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 1938 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 1938 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1938 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1938 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6301 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6301 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6301 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6301 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6301 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261165999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 261165999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261165999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 261165999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261165999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 261165999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6305 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6305 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6305 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6305 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6305 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6305 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261344999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 261344999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261344999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 261344999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261344999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 261344999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41448.341374 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41448.341374 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41448.341374 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41448.341374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41448.341374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41448.341374 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41450.436003 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259749 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32631.179257 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207901 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292487 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.129760 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2512.609153 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 65.430826 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30052.094536 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001997 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5296 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26539 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 532 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26438 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12915272 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12915272 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81376.241660 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81356.477060 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79237.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81376.241660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81356.477060 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,120 +952,121 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20845449000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.968345 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.968345 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.431519 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.431519 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312639 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312639 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.431519 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370387 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370876 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.431519 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370387 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73475.963198 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73475.963198 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68739.058477 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68739.058477 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70711.831838 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70711.831838 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68739.058477 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428232 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312733 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312733 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370935 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370935 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73155.277219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73155.277219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69241.481481 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69241.481481 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70844.251700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70844.251700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1569303 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 1569307 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781754 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1986 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1986 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1989 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1989 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 718745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 885494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712445 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339654 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2356853 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 403200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55688320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56091520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259305 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1828608 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032938 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 718748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712444 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17211 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2356859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 697984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55671296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56369280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259749 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1047302 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001899 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1826622 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1986 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1045313 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1989 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1828608 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 873531500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1047302 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877871500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9450000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9456000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171875499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171872499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225456 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191030 # Transaction distribution -system.membus.trans_dist::ReadExReq 66627 # Transaction distribution -system.membus.trans_dist::ReadExResp 66627 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225456 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 841879 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 841879 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22961024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22961024 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 225504 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191079 # Transaction distribution +system.membus.trans_dist::ReadExReq 66626 # Transaction distribution +system.membus.trans_dist::ReadExResp 66626 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225504 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842022 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22964032 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549796 # Request fanout histogram +system.membus.snoop_fanout::samples 549892 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549796 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549892 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549796 # Request fanout histogram -system.membus.reqLayer0.occupancy 880960000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 549892 # Request fanout histogram +system.membus.reqLayer0.occupancy 880924000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551840500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551641250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f1fff22ed..5e6b1a1be 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.286279 # Number of seconds simulated -sim_ticks 1286278511500 # Number of ticks simulated -final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.288319 # Number of seconds simulated +sim_ticks 1288319411500 # Number of ticks simulated +final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1389844 # Simulator instruction rate (inst/s) -host_op_rate 1389844 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1925210162 # Simulator tick rate (ticks/s) -host_mem_usage 305148 # Number of bytes of host memory used -host_seconds 668.12 # Real time elapsed on the host +host_inst_rate 1465054 # Simulator instruction rate (inst/s) +host_op_rate 1465054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2032611527 # Simulator tick rate (ticks/s) +host_mem_usage 306300 # Number of bytes of host memory used +host_seconds 633.82 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18509184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18646976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory +system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289206 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291359 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14389717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14496842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3317876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3317876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3317876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14389717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17814717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572557023 # number of cpu cycles simulated +system.cpu.numCycles 2576638823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572557023 # Number of busy cycles +system.cpu.num_busy_cycles 2576638823 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261358 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046537500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261358 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses @@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18597166000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18597166000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696410000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696410000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22293576000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22293576000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22293576000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22293576000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) @@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26137.456185 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26137.456185 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.292115 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.292115 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28562.173298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28562.173298 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 89031 # number of writebacks -system.cpu.dcache.writebacks::total 89031 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks +system.cpu.dcache.writebacks::total 88866 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses @@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528 system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17885652000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17885652000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3627396000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3627396000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21513048000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21513048000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21513048000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21513048000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -228,24 +228,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25137.456185 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25137.456185 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52560.292115 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52560.292115 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486224 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486224 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id @@ -266,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170684500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170684500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170684500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170684500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170684500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170684500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -284,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27672.584306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27672.584306 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27672.584306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27672.584306 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,93 +298,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 4618 # number of writebacks +system.cpu.icache.writebacks::total 4618 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164516500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 164516500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164516500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 164516500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164516500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 164516500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26672.584306 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26672.584306 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258580 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.927159 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207050 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291314 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.143467 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258847 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2486.879631 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.811890 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30121.235638 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.075894 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001520 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.919227 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996641 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12902296 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12902296 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 89031 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 89031 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4015 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4015 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488956 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488956 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4015 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491322 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495337 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4015 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491322 # number of overall hits -system.cpu.l2cache.overall_hits::total 495337 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits +system.cpu.l2cache.overall_hits::total 495307 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2153 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2153 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222558 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222558 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289206 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289206 # number of overall misses -system.cpu.l2cache.overall_misses::total 291359 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499032000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3499032000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 113105000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 113105000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11684343000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11684343000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 113105000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15183375000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15296480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 113105000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15183375000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15296480000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 89031 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 89031 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses +system.cpu.l2cache.overall_misses::total 291389 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) @@ -399,28 +405,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 780528 system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.349060 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312795 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312795 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370526 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370526 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.180050 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.180050 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52533.673943 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52533.673943 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.215674 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.215674 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.454765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.454765 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,58 +437,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 238 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 238 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2153 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2153 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222558 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222558 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289206 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291359 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289206 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291359 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2832552000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2832552000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91575000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91575000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9458763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9458763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91575000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12291315000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12382890000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91575000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12291315000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12382890000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.349060 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312795 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312795 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.180050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.180050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42533.673943 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42533.673943 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.215674 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.215674 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -491,8 +497,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution @@ -500,51 +507,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55651776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258580 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000941 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030656 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258847 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1824608 99.91% 99.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1718 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 224711 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190417 # Transaction distribution +system.membus.trans_dist::ReadResp 224741 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 190447 # Transaction distribution system.membus.trans_dist::ReadExReq 66648 # Transaction distribution system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224711 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839818 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839818 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22914688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22914688 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 548514 # Request fanout histogram +system.membus.snoop_fanout::samples 548519 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548514 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548514 # Request fanout histogram -system.membus.reqLayer0.occupancy 815261292 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 548519 # Request fanout histogram +system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456808792 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index ca22b895a..c95abda26 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.542258 # Number of seconds simulated -sim_ticks 542257676500 # Number of ticks simulated -final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.542265 # Number of seconds simulated +sim_ticks 542265386500 # Number of ticks simulated +final_tick 542265386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169610 # Simulator instruction rate (inst/s) -host_op_rate 208813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 143560034 # Simulator tick rate (ticks/s) -host_mem_usage 325880 # Number of bytes of host memory used -host_seconds 3777.22 # Real time elapsed on the host +host_inst_rate 179877 # Simulator instruction rate (inst/s) +host_op_rate 221452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152251725 # Simulator tick rate (ticks/s) +host_mem_usage 325476 # Number of bytes of host memory used +host_seconds 3561.64 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory -system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18474304 # Number of bytes read from this memory +system.physmem.bytes_read::total 18637888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288661 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291217 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291175 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 301668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34068750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34370418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 301668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 301668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7801110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7801110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7801110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 301668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34068750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42171528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291217 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291217 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18637888 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18282 # Per bank write bursts -system.physmem.perBankRdBursts::1 18135 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 190686 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18283 # Per bank write bursts +system.physmem.perBankRdBursts::1 18129 # Per bank write bursts system.physmem.perBankRdBursts::2 18220 # Per bank write bursts -system.physmem.perBankRdBursts::3 18173 # Per bank write bursts -system.physmem.perBankRdBursts::4 18273 # Per bank write bursts -system.physmem.perBankRdBursts::5 18400 # Per bank write bursts -system.physmem.perBankRdBursts::6 18176 # Per bank write bursts -system.physmem.perBankRdBursts::7 17989 # Per bank write bursts +system.physmem.perBankRdBursts::3 18184 # Per bank write bursts +system.physmem.perBankRdBursts::4 18283 # Per bank write bursts +system.physmem.perBankRdBursts::5 18405 # Per bank write bursts +system.physmem.perBankRdBursts::6 18181 # Per bank write bursts +system.physmem.perBankRdBursts::7 17993 # Per bank write bursts system.physmem.perBankRdBursts::8 18030 # Per bank write bursts -system.physmem.perBankRdBursts::9 18057 # Per bank write bursts -system.physmem.perBankRdBursts::10 18104 # Per bank write bursts -system.physmem.perBankRdBursts::11 18195 # Per bank write bursts -system.physmem.perBankRdBursts::12 18214 # Per bank write bursts -system.physmem.perBankRdBursts::13 18267 # Per bank write bursts +system.physmem.perBankRdBursts::9 18058 # Per bank write bursts +system.physmem.perBankRdBursts::10 18107 # Per bank write bursts +system.physmem.perBankRdBursts::11 18199 # Per bank write bursts +system.physmem.perBankRdBursts::12 18220 # Per bank write bursts +system.physmem.perBankRdBursts::13 18271 # Per bank write bursts system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18257 # Per bank write bursts +system.physmem.perBankRdBursts::15 18260 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4098 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4223 # Per bank write bursts system.physmem.perBankWrBursts::5 4222 # Per bank write bursts system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4092 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts -system.physmem.perBankWrBursts::11 4096 # Per bank write bursts -system.physmem.perBankWrBursts::12 4097 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542257582000 # Total gap between requests +system.physmem.totGap 542265360500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291175 # Read request sizes (log2) +system.physmem.readPktSize::6 291217 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,43 +193,42 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 111115 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.591972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.871353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.553383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45879 41.29% 41.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43676 39.31% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9414 8.47% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1626 1.46% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 693 0.62% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 670 0.60% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 551 0.50% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8091 7.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111115 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.511200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.259636 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.474106 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.447598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.427351 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.833980 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3118 77.62% 77.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 2868100000 # Total ticks spent queuing -system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.444749 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.424614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.831636 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3124 77.75% 77.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 77.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 893 22.22% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads +system.physmem.totQLat 2873170250 # Total ticks spent queuing +system.physmem.totMemAccLat 8327545250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9876.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28626.83 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s @@ -239,49 +238,49 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing -system.physmem.readRowHits 194250 # Number of row buffer hits during reads -system.physmem.writeRowHits 51642 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.34 # Average write queue length when enqueuing +system.physmem.readRowHits 194203 # Number of row buffer hits during reads +system.physmem.writeRowHits 51643 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes -system.physmem.avgGap 1517768.15 # Average gap between requests -system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.324021 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states +system.physmem.avgGap 1517611.52 # Average gap between requests +system.physmem.pageHitRate 68.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 420789600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229597500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136101200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215537760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 107646010785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 230928516000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375994196925 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.386081 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 383467912500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18107180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 140682990000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.447269 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states -system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states +system.physmem_1.actEnergy 419141520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228698250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132419600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 107856715275 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230743687500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 376010934465 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.416947 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 383162755000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18107180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 140991278500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 154805770 # Number of BP lookups -system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted +system.cpu.branchPred.lookups 154805774 # Number of BP lookups +system.cpu.branchPred.condPredicted 105138294 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 90693368 # Number of BTB lookups system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.615652 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19277596 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -401,24 +400,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1084515353 # number of cpu cycles simulated +system.cpu.numCycles 1084530773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.692823 # CPI: cycles per instruction -system.cpu.ipc 0.590729 # IPC: instructions per cycle -system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.692847 # CPI: cycles per instruction +system.cpu.ipc 0.590721 # IPC: instructions per cycle +system.cpu.tickCycles 1025899528 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58631245 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778339 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.484104 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484104 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -454,14 +453,14 @@ system.cpu.dcache.demand_misses::cpu.data 851588 # n system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses system.cpu.dcache.overall_misses::total 851729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24770851500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24770851500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105356000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10105356000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34876207500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34876207500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34876207500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34876207500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -486,14 +485,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34699.095501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34699.095501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73380.359010 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73380.359010 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40954.320047 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40954.320047 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40947.540239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40947.540239 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,8 +501,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88920 # number of writebacks -system.cpu.dcache.writebacks::total 88920 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88693 # number of writebacks +system.cpu.dcache.writebacks::total 88693 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 902 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -522,16 +521,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782296 system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24041947500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24041947500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067670500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067670500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29109618000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29109618000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29111406000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29111406000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -542,24 +541,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33720.651104 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33720.651104 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73103.351029 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73103.351029 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37210.490658 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37210.490658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37206.165368 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37206.165368 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23591 # number of replacements -system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1713.095631 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291576507 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11505.662813 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095631 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -567,44 +566,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 58 system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses -system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits -system.cpu.icache.overall_hits::total 291576499 # number of overall hits +system.cpu.icache.tags.tag_accesses 583229042 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583229042 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291576507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291576507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291576507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291576507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291576507 # number of overall hits +system.cpu.icache.overall_hits::total 291576507 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses system.cpu.icache.overall_misses::total 25343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 498728500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 498728500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 498728500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 498728500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 498728500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 498728500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291601850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291601850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291601850 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 291601850 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 291601850 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 291601850 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # 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average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80061.993198 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78785.272103 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78785.272103 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,58 +761,54 @@ system.cpu.l2cache.demand_mshr_hits::total 32 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2573 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2573 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222512 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222512 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2573 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288603 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2573 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288603 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291176 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268970500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268970500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169583000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169583000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15585424500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15585424500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169583000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19854395000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20023978000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169583000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19854395000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20023978000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222570 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222570 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291218 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291218 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268849500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268849500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15594098500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15594098500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169007000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19862948000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20031955000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169007000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19862948000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20031955000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101527 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312029 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312029 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312110 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312110 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360517 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360517 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64590.481306 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64590.481306 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66095.815409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66095.815409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70063.793413 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70063.793413 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -816,8 +817,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154791 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 22257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880344 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution @@ -825,51 +827,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72942 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341192 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2414134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55766720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258395 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3046336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 58798528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258813 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1066591 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005113 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.071523 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1061152 99.49% 99.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5424 0.51% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1066591 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 917138000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225084 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190644 # Transaction distribution +system.membus.trans_dist::ReadResp 225126 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190686 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225084 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839092 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22865472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225126 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839218 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22868160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 547917 # Request fanout histogram +system.membus.snoop_fanout::samples 548001 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 547917 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 548001 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 547917 # Request fanout histogram -system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 548001 # Request fanout histogram +system.membus.reqLayer0.occupancy 918049500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554665000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 8ea31b650..52d6cf15b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410968 # Number of seconds simulated -sim_ticks 410968419000 # Number of ticks simulated -final_tick 410968419000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.452586 # Number of seconds simulated +sim_ticks 452585997000 # Number of ticks simulated +final_tick 452585997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85599 # Simulator instruction rate (inst/s) -host_op_rate 105384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54910730 # Simulator tick rate (ticks/s) -host_mem_usage 322152 # Number of bytes of host memory used -host_seconds 7484.30 # Real time elapsed on the host +host_inst_rate 89374 # Simulator instruction rate (inst/s) +host_op_rate 110031 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63138171 # Simulator tick rate (ticks/s) +host_mem_usage 323296 # Number of bytes of host memory used +host_seconds 7168.18 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 226432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7007424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12927040 # Number of bytes read from this memory -system.physmem.bytes_read::total 20160896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 226432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244672 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 201985 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315014 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66323 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 550972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17051004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31455069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49057044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 550972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 550972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10328463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10328463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10328463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 550972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17051004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31455069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59385507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315014 # Number of read requests accepted -system.physmem.writeReqs 66323 # Number of write requests accepted -system.physmem.readBursts 315014 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66323 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20141440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19456 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 234368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47997568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12828032 # Number of bytes read from this memory +system.physmem.bytes_read::total 61059968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 234368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 234368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4243520 # Number of bytes written to this memory +system.physmem.bytes_written::total 4243520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 749962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 954062 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66305 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66305 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 106051818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 28343855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134913516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9376163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9376163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9376163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 106051818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 28343855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 144289678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 954063 # Number of read requests accepted +system.physmem.writeReqs 66305 # Number of write requests accepted +system.physmem.readBursts 954063 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66305 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61041664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18368 # Total number of bytes read from write queue system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20160896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 304 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 67 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19880 # Per bank write bursts -system.physmem.perBankRdBursts::1 19436 # Per bank write bursts -system.physmem.perBankRdBursts::2 19769 # Per bank write bursts -system.physmem.perBankRdBursts::3 19866 # Per bank write bursts -system.physmem.perBankRdBursts::4 19687 # Per bank write bursts -system.physmem.perBankRdBursts::5 20154 # Per bank write bursts -system.physmem.perBankRdBursts::6 19548 # Per bank write bursts -system.physmem.perBankRdBursts::7 19410 # Per bank write bursts -system.physmem.perBankRdBursts::8 19409 # Per bank write bursts -system.physmem.perBankRdBursts::9 19464 # Per bank write bursts -system.physmem.perBankRdBursts::10 19401 # Per bank write bursts -system.physmem.perBankRdBursts::11 19757 # Per bank write bursts -system.physmem.perBankRdBursts::12 19512 # Per bank write bursts -system.physmem.perBankRdBursts::13 19953 # Per bank write bursts -system.physmem.perBankRdBursts::14 19499 # Per bank write bursts -system.physmem.perBankRdBursts::15 19965 # Per bank write bursts -system.physmem.perBankWrBursts::0 4261 # Per bank write bursts -system.physmem.perBankWrBursts::1 4104 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.bytesReadSys 61060032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4243520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 287 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 227627 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19636 # Per bank write bursts +system.physmem.perBankRdBursts::1 19225 # Per bank write bursts +system.physmem.perBankRdBursts::2 656809 # Per bank write bursts +system.physmem.perBankRdBursts::3 20104 # Per bank write bursts +system.physmem.perBankRdBursts::4 19566 # Per bank write bursts +system.physmem.perBankRdBursts::5 20746 # Per bank write bursts +system.physmem.perBankRdBursts::6 19449 # Per bank write bursts +system.physmem.perBankRdBursts::7 19830 # Per bank write bursts +system.physmem.perBankRdBursts::8 19282 # Per bank write bursts +system.physmem.perBankRdBursts::9 19792 # Per bank write bursts +system.physmem.perBankRdBursts::10 19287 # Per bank write bursts +system.physmem.perBankRdBursts::11 19476 # Per bank write bursts +system.physmem.perBankRdBursts::12 19427 # Per bank write bursts +system.physmem.perBankRdBursts::13 20933 # Per bank write bursts +system.physmem.perBankRdBursts::14 19357 # Per bank write bursts +system.physmem.perBankRdBursts::15 20857 # Per bank write bursts +system.physmem.perBankWrBursts::0 4254 # Per bank write bursts +system.physmem.perBankWrBursts::1 4108 # Per bank write bursts +system.physmem.perBankWrBursts::2 4140 # Per bank write bursts +system.physmem.perBankWrBursts::3 4154 # Per bank write bursts system.physmem.perBankWrBursts::4 4243 # Per bank write bursts -system.physmem.perBankWrBursts::5 4228 # Per bank write bursts +system.physmem.perBankWrBursts::5 4230 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4095 # Per bank write bursts -system.physmem.perBankWrBursts::9 4094 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4153 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410968364500 # Total gap between requests +system.physmem.totGap 452585986500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315014 # Read request sizes (log2) +system.physmem.readPktSize::6 954063 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66323 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 121710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1023 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66305 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 760072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 900 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -197,112 +197,110 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.576479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.708862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.239774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54117 39.64% 39.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57190 41.89% 81.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14847 10.88% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1353 0.99% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1460 1.07% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1428 1.05% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1211 0.89% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1099 0.81% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3810 2.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136515 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.350768 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.698276 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 557.584511 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4013 99.48% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.22% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 4 0.10% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.07% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11264-12287 2 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.416708 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.380496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.197000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3413 84.61% 84.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 10 0.25% 84.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 440 10.91% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 77 1.91% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.89% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.45% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.35% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.25% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 4 0.10% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads -system.physmem.totQLat 8815753021 # Total ticks spent queuing -system.physmem.totMemAccLat 14716565521 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1573550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28012.31 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 205647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.429381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.568290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 286.974442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59802 29.08% 29.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62661 30.47% 59.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15924 7.74% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3207 1.56% 68.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3374 1.64% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48035 23.36% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7705 3.75% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 205647 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 234.045421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.559432 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3989.674296 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4017 99.70% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-16383 7 0.17% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-32767 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::90112-98303 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::212992-221183 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.396271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.276876 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3401 84.41% 84.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.22% 84.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 462 11.47% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 50 1.24% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.40% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 18 0.45% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.25% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.15% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.10% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads +system.physmem.totQLat 15106541272 # Total ticks spent queuing +system.physmem.totMemAccLat 32989841272 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4768880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15838.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46762.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.31 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.06 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34588.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 9.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.91 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.46 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing -system.physmem.readRowHits 218109 # Number of row buffer hits during reads -system.physmem.writeRowHits 26303 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.70 # Row buffer hit rate for writes -system.physmem.avgGap 1077703.88 # Average gap between requests -system.physmem.pageHitRate 64.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 518041440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 282661500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1230403200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96374724480 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 162040566750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 287505134730 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.583184 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 268934392735 # Time in different power states -system.physmem_0.memoryStateTime::REF 13723060000 # Time in different power states +system.physmem.busUtil 1.13 # Data bus utilization in percentage +system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing +system.physmem.readRowHits 788463 # Number of row buffer hits during reads +system.physmem.writeRowHits 25883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes +system.physmem.avgGap 443551.72 # Average gap between requests +system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1032091200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 563145000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6203792400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216412560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305512170480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3557164500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 346645334700 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.925147 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4194914578 # Time in different power states +system.physmem_0.memoryStateTime::REF 15112760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128308892015 # Time in different power states +system.physmem_0.memoryStateTime::ACT 433276166672 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 513943920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280425750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1224030600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96023770920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 162348426750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 287445609300 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.438325 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 269449023468 # Time in different power states -system.physmem_1.memoryStateTime::REF 13723060000 # Time in different power states +system.physmem_1.actEnergy 522539640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 285115875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1235348400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96876011835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 186571355250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 315263655000 # Total energy per rank (pJ) +system.physmem_1.averagePower 696.586172 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 309737229647 # Time in different power states +system.physmem_1.memoryStateTime::REF 15112760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127794271282 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127733879103 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234596987 # Number of BP lookups -system.cpu.branchPred.condPredicted 161823961 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514568 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122849584 # Number of BTB lookups -system.cpu.branchPred.BTBHits 109536151 # Number of BTB hits +system.cpu.branchPred.lookups 234612390 # Number of BP lookups +system.cpu.branchPred.condPredicted 162472835 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514556 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121579993 # Number of BTB lookups +system.cpu.branchPred.BTBHits 107625887 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.162818 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25674290 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300140 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.522696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035644 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300133 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,129 +419,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 821936839 # number of cpu cycles simulated +system.cpu.numCycles 905171995 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85359069 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200718249 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234596987 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135210441 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 720713354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063509 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 86003110 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1202048869 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234612390 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 132661531 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 803279049 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064713 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1868 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3414 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 371348285 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652804 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 821609958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.824964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.165392 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3204 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370083974 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652982 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 904819618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.657214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229926 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 139667844 17.00% 17.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223418217 27.19% 44.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 99581089 12.12% 56.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 358942808 43.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222849160 24.63% 24.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 224059075 24.76% 49.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98313082 10.87% 60.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 359598301 39.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 821609958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285420 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.460840 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121271680 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 161528221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484660379 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38631604 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518074 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181978 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13827 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248136929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39965779 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518074 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178276857 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80769172 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 209944 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464321622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82514289 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190649625 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25545503 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24955076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2266892 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41524383 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1701930 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225389846 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812446196 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358179405 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 904819618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259191 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.327978 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121904104 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 244100755 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484657410 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38638668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518681 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24546049 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13811 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248144086 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39968857 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518681 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178914873 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 163328471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319861 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82530704 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190654266 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 24276153 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24946873 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2269725 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41528835 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1707155 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1226040359 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5813734095 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358184137 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876447 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350611616 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7266 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 351262129 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108773290 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366116518 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236097454 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1660812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5332652 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168559259 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12361 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017121345 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18467813 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379846662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032147150 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 207 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 821609958 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.237961 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084868 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108789591 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 367388897 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236094901 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1672944 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5307285 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1169836169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12331 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017123135 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 19093941 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 381123542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1038508983 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 177 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 904819618 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.124117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093910 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263952395 32.13% 32.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227112360 27.64% 59.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217754382 26.50% 86.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96663071 11.77% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16127742 1.96% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347160042 38.37% 38.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227103662 25.10% 63.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217769500 24.07% 87.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96665190 10.68% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16121217 1.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 821609958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 904819618 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63877670 18.90% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18143 0.01% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 157438093 46.58% 65.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116037067 34.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63881232 18.86% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 158064095 46.67% 65.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116064822 34.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456371832 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195828 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456367780 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -565,90 +563,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322111232 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215588105 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478995 1.13% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322109040 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215596292 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017121345 # Type of FU issued -system.cpu.iq.rate 1.237469 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338007862 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332318 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3150451328 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504870795 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934275536 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61876995 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565857 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1017123135 # Type of FU issued +system.cpu.iq.rate 1.123679 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338665181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3234948583 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1507425320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934275773 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876427 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565693 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321318894 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810313 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960669 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 1321978571 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9959468 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113875580 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1094 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18373 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107116958 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 115147959 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107114405 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 20149 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065764 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19863 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518074 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35327155 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 46316 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168577176 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518681 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35329232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27153 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1169854056 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366116518 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236097454 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6621 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 106 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 49932 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18373 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437332 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784565 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221897 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974752675 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42368670 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 367388897 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236094901 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29598 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437212 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784515 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221727 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974753111 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303296723 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42370024 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497765117 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613949 # Number of branches executed -system.cpu.iew.exec_stores 194467406 # Number of stores executed -system.cpu.iew.exec_rate 1.185922 # Inst execution rate -system.cpu.iew.wb_sent 963726327 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960427986 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536047777 # num instructions producing a value -system.cpu.iew.wb_consumers 893284950 # num instructions consuming a value +system.cpu.iew.exec_refs 497769972 # number of memory reference insts executed +system.cpu.iew.exec_branches 150611064 # Number of branches executed +system.cpu.iew.exec_stores 194473249 # Number of stores executed +system.cpu.iew.exec_rate 1.076871 # Inst execution rate +system.cpu.iew.wb_sent 963726707 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960428223 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536045857 # num instructions producing a value +system.cpu.iew.wb_consumers 893287669 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.168494 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back +system.cpu.iew.wb_rate 1.061045 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357420302 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357425551 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500888 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770788105 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.023277 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.776928 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 853996264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.923576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.715161 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 432159906 56.07% 56.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174391468 22.63% 78.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72936790 9.46% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32897876 4.27% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8538896 1.11% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14258442 1.85% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7269703 0.94% 96.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5974810 0.78% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360214 2.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 515355287 60.35% 60.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174404345 20.42% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72937486 8.54% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32899801 3.85% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8539084 1.00% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14259189 1.67% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7267219 0.85% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5975069 0.70% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22358784 2.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770788105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 853996264 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -694,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360214 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1894569512 # The number of ROB reads -system.cpu.rob.rob_writes 2343126520 # The number of ROB writes -system.cpu.timesIdled 647387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 326881 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22358784 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1977784350 # The number of ROB reads +system.cpu.rob.rob_writes 2343138350 # The number of ROB writes +system.cpu.timesIdled 648611 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 352377 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.282975 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282975 # CPI: Total CPI of All Threads -system.cpu.ipc 0.779439 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.779439 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995803218 # number of integer regfile reads -system.cpu.int_regfile_writes 567908989 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889842 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794442903 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898512 # number of cc regfile writes -system.cpu.misc_regfile_reads 715818410 # number of misc regfile reads +system.cpu.cpi 1.412898 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.412898 # CPI: Total CPI of All Threads +system.cpu.ipc 0.707765 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.707765 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995811618 # number of integer regfile reads +system.cpu.int_regfile_writes 567906414 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794441379 # number of cc regfile reads +system.cpu.cc_regfile_writes 384896518 # number of cc regfile writes +system.cpu.misc_regfile_reads 715823215 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756184 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.933181 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258467 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 257783000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.933181 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756185 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.937157 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216587 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258294 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.937157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839346712 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839346712 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286294274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286294274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907939 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907939 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839347973 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347973 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906811 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906811 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414202213 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414202213 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414205370 # number of overall hits -system.cpu.dcache.overall_hits::total 414205370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3033975 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3033975 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043538 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043538 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414200611 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414200611 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414203768 # number of overall hits +system.cpu.dcache.overall_hits::total 414203768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3035079 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3035079 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044666 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4077513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4077513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4078159 # number of overall misses -system.cpu.dcache.overall_misses::total 4078159 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35335718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35335718000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10020788350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4079745 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4079745 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4080391 # number of overall misses +system.cpu.dcache.overall_misses::total 4080391 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76869214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76869214000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10006334850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10006334850 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45356506350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45356506350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45356506350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45356506350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328249 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 86875548850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86875548850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86875548850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86875548850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -776,309 +774,305 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279726 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279726 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283529 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283529 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418280356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284159 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284159 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008101 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009748 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009748 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009750 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009750 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11646.674083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11646.674083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9602.705747 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9602.705747 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25326.923615 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25326.923615 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9578.501502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9578.501502 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11123.571243 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11123.571243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11121.809216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11121.809216 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21294.357576 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21294.357576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21290.986293 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21290.986293 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 355417 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 352038 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4792 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4878 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 74.168823 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.168512 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735485 # number of writebacks -system.cpu.dcache.writebacks::total 735485 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 998769 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 998769 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322672 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322672 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2756185 # number of writebacks +system.cpu.dcache.writebacks::total 2756185 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999872 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323643 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1321441 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1321441 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1321441 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1321441 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035206 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035206 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720866 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720866 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1323515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1323515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1323515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1323515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035207 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035207 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756072 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756072 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756713 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756713 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24128110500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24128110500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5958496350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5958496350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5922000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5922000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30086606850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30086606850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30092528850 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71526298850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 71526298850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71531875350 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 71531875350 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11855.365255 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11855.365255 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8265.747518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8265.747518 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9238.689548 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9238.689548 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10916.480720 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10916.480720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10916.090594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10916.090594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32217.417933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32217.417933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8262.128046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8262.128046 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8699.687988 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8699.687988 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25950.772922 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25950.772922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25946.761872 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25946.761872 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169351 # number of replacements -system.cpu.icache.tags.tagsinuse 510.555311 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 366173734 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169861 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.828545 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 247765500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.555311 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997178 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997178 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169363 # number of replacements +system.cpu.icache.tags.tagsinuse 510.872217 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364909729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169873 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.583886 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.872217 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997797 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 747866384 # Number of tag accesses -system.cpu.icache.tags.data_accesses 747866384 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 366173762 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 366173762 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 366173762 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 366173762 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 366173762 # number of overall hits -system.cpu.icache.overall_hits::total 366173762 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174491 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174491 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174491 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174491 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174491 # number of overall misses -system.cpu.icache.overall_misses::total 5174491 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41645043922 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41645043922 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41645043922 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41645043922 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41645043922 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41645043922 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 371348253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 371348253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 371348253 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 371348253 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 371348253 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 371348253 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.143078 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8048.143078 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.143078 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8048.143078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.143078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8048.143078 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 82369 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 103 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3794 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 745337941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 745337941 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 364909744 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 364909744 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 364909744 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 364909744 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 364909744 # number of overall hits +system.cpu.icache.overall_hits::total 364909744 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174203 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174203 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174203 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174203 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174203 # number of overall misses +system.cpu.icache.overall_misses::total 5174203 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41972246420 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41972246420 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41972246420 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41972246420 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41972246420 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41972246420 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370083947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370083947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370083947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370083947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370083947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370083947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013981 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013981 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013981 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013981 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013981 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013981 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.828318 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8111.828318 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8111.828318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8111.828318 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 80154 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3667 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.710332 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 20.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.858195 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4612 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4612 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4612 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4612 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4612 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4612 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169879 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169879 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169879 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169879 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169879 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169879 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39015177435 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39015177435 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39015177435 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39015177435 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39015177435 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39015177435 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013922 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013922 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013922 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013922 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013922 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7546.632607 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7546.632607 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7546.632607 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7546.632607 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7546.632607 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7546.632607 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 5169363 # number of writebacks +system.cpu.icache.writebacks::total 5169363 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4154 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4154 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4154 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4154 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4154 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4154 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170049 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5170049 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5170049 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5170049 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5170049 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5170049 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39346514434 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39346514434 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39346514434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39346514434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39346514434 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39346514434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.472248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.472248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1349974 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355118 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 4500 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350388 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355069 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 4095 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6700.053629 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.045675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007756 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.536259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.408939 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998628 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6481 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9883 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1434 # 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number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 108114 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 108114 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3538 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 109491 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 113029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3538 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 109491 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202062 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 315091 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17000279164 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17000279164 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 275000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 275000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 139099000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 139099000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240756500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240756500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7531984000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7531984000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240756500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7671083000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7911839500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240756500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7671083000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17000279164 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24912118664 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.writebacks::writebacks 66305 # number of writebacks +system.cpu.l2cache.writebacks::total 66305 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1019 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1019 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 872 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 872 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1891 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1892 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1891 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1892 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200528 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 200528 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1366 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1366 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3663 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3663 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748596 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748596 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 749962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 753625 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3663 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 749962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200528 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 954153 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16518025996 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16518025996 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2993500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2993500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133767000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133767000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248088000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248088000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49620654000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49620654000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248088000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49754421000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 50002509000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 248088000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49754421000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16518025996 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66520534996 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000684 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053105 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053105 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367707 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367707 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.095076 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039751 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84133.974542 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17187.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17187.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 101015.976761 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 101015.976761 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68048.756360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68048.756360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69667.055145 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69667.055145 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69998.314592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79063.250502 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120374 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82372.666141 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17204.022989 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17204.022989 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97926.061493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97926.061493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67728.091728 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67728.091728 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66284.957440 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66284.957440 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66349.323603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69716.843102 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 15852127 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925581 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644320 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 9549 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 9495 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 54 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7205725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6778141 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 245737 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 15852468 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 760150 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116849 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6546111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 987513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23134399 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330871168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223499584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554370752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 544470 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 16396581 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.079179 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270031 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035848 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508407 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23135037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661654912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311653440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 973308352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1297915 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9224662 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.222014 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.558747 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 15098363 92.08% 92.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1298164 7.92% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 54 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7819958 84.77% 84.77% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 761403 8.25% 93.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 643301 6.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 16396581 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8661548500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754847439 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135063977 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 313637 # Transaction distribution -system.membus.trans_dist::Writeback 66323 # Transaction distribution -system.membus.trans_dist::CleanEvict 231789 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 313637 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 928172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 928172 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24405568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24405568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 9224662 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15851782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7755313513 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4135165933 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadResp 952696 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66305 # Transaction distribution +system.membus.trans_dist::CleanEvict 227453 # Transaction distribution +system.membus.trans_dist::UpgradeReq 174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 1366 # Transaction distribution +system.membus.trans_dist::ReadExResp 1366 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 952697 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2202231 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2202231 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65303488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65303488 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 613142 # Request fanout histogram +system.membus.snoop_fanout::samples 1247995 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 613142 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1247995 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 613142 # Request fanout histogram -system.membus.reqLayer0.occupancy 975944720 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1649749525 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 1247995 # Request fanout histogram +system.membus.reqLayer0.occupancy 1752388071 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 5021031104 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 24851d5c1..dd5f11d63 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.043724 # Number of seconds simulated -sim_ticks 1043723537500 # Number of ticks simulated -final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.045756 # Number of seconds simulated +sim_ticks 1045756396500 # Number of ticks simulated +final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 832063 # Simulator instruction rate (inst/s) -host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1358287943 # Simulator tick rate (ticks/s) -host_mem_usage 323064 # Number of bytes of host memory used -host_seconds 768.41 # Real time elapsed on the host +host_inst_rate 734670 # Simulator instruction rate (inst/s) +host_op_rate 902587 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1201635964 # Simulator tick rate (ticks/s) +host_mem_usage 323928 # Number of bytes of host memory used +host_seconds 870.28 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18469760 # Number of bytes read from this memory -system.physmem.bytes_read::total 18582976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory +system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288590 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290359 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087447075 # number of cpu cycles simulated +system.cpu.numCycles 2091512793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 89072 # number of writebacks -system.cpu.dcache.writebacks::total 89072 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks +system.cpu.dcache.writebacks::total 88995 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,93 +413,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 8769 # number of writebacks +system.cpu.icache.writebacks::total 8769 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257579 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257772 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12984085 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12984085 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 89072 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 89072 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8439 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8439 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490322 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490322 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8439 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493552 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501991 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8439 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493552 # number of overall hits -system.cpu.l2cache.overall_hits::total 501991 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits +system.cpu.l2cache.overall_hits::total 501982 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1769 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1769 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222497 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222497 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1769 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288590 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1769 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288590 # number of overall misses -system.cpu.l2cache.overall_misses::total 290359 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses +system.cpu.l2cache.overall_misses::total 290368 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) @@ -514,28 +520,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 782142 system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.173295 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.173295 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312137 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312137 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173295 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368974 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.366453 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173295 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368974 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.366453 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,58 +552,54 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 184 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 184 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1769 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1769 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222497 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222497 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290359 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288590 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290359 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.173295 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312137 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312137 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366453 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366453 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -606,8 +608,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 8752 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879632 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution @@ -615,51 +618,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55757696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257579 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1213440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56966208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257772 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 224266 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190085 # Transaction distribution +system.membus.trans_dist::ReadResp 224275 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190094 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224266 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836901 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836901 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22813248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 546599 # Request fanout histogram +system.membus.snoop_fanout::samples 546561 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 546599 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 546599 # Request fanout histogram -system.membus.reqLayer0.occupancy 811365948 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 546561 # Request fanout histogram +system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1452169448 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |