diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/40.perlbmk | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/40.perlbmk')
12 files changed, 1375 insertions, 1385 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 1dc93d52f..0ba1f17a2 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index fbf7fa994..b26c5402f 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:12:31 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:41:27 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 639588907000 because target called exit() +Exiting @ tick 646278131000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index f93e57319..042c81ef0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.639589 # Number of seconds simulated -sim_ticks 639588907000 # Number of ticks simulated -final_tick 639588907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.646278 # Number of seconds simulated +sim_ticks 646278131000 # Number of ticks simulated +final_tick 646278131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210347 # Simulator instruction rate (inst/s) -host_op_rate 210347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73797228 # Simulator tick rate (ticks/s) -host_mem_usage 229080 # Number of bytes of host memory used -host_seconds 8666.84 # Real time elapsed on the host +host_inst_rate 212773 # Simulator instruction rate (inst/s) +host_op_rate 212773 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75429257 # Simulator tick rate (ticks/s) +host_mem_usage 229040 # Number of bytes of host memory used +host_seconds 8568.00 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 191360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94464192 # Number of bytes read from this memory -system.physmem.bytes_read::total 94655552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 191360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 191360 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 191680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94465088 # Number of bytes read from this memory +system.physmem.bytes_read::total 94656768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 191680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 191680 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1478993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476017 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479012 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 299192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 147695169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 147994362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 299192 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 299192 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6694100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6694100 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6694100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 299192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 147695169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 154688461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 296591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146167855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146464445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 296591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 296591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6624813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6624813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6624813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 296591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146167855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153089259 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 525683715 # DTB read hits -system.cpu.dtb.read_misses 628896 # DTB read misses +system.cpu.dtb.read_hits 528353322 # DTB read hits +system.cpu.dtb.read_misses 626455 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526312611 # DTB read accesses -system.cpu.dtb.write_hits 287304184 # DTB write hits -system.cpu.dtb.write_misses 53890 # DTB write misses +system.cpu.dtb.read_accesses 528979777 # DTB read accesses +system.cpu.dtb.write_hits 292227311 # DTB write hits +system.cpu.dtb.write_misses 54391 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 287358074 # DTB write accesses -system.cpu.dtb.data_hits 812987899 # DTB hits -system.cpu.dtb.data_misses 682786 # DTB misses +system.cpu.dtb.write_accesses 292281702 # DTB write accesses +system.cpu.dtb.data_hits 820580633 # DTB hits +system.cpu.dtb.data_misses 680846 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 813670685 # DTB accesses -system.cpu.itb.fetch_hits 398461552 # ITB hits -system.cpu.itb.fetch_misses 1212 # ITB misses +system.cpu.dtb.data_accesses 821261479 # DTB accesses +system.cpu.itb.fetch_hits 401438115 # ITB hits +system.cpu.itb.fetch_misses 852 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398462764 # ITB accesses +system.cpu.itb.fetch_accesses 401438967 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1279177815 # number of cpu cycles simulated +system.cpu.numCycles 1292556263 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 391601012 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 255930815 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27097905 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 318432805 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 256621752 # Number of BTB hits +system.cpu.BPredUnit.lookups 394747270 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 256599366 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27590844 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 323468940 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262010178 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59044090 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7305 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 417206849 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3304631660 # Number of instructions fetch has processed -system.cpu.fetch.Branches 391601012 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315665842 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 634205086 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158948618 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 96266839 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 158 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11708 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398461552 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8907646 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1279053519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.583654 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.145594 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57787448 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7273 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421195056 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3322341707 # Number of instructions fetch has processed +system.cpu.fetch.Branches 394747270 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 319797626 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638354680 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162914777 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 98034183 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9273 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 401438115 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8412038 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.570619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.140035 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 644848433 50.42% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60073670 4.70% 55.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44904383 3.51% 58.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71013010 5.55% 64.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 124436565 9.73% 73.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45667903 3.57% 77.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41114141 3.21% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7023739 0.55% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 239971675 18.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 654074173 50.61% 50.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60911661 4.71% 55.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43750931 3.39% 58.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72637907 5.62% 64.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 126293368 9.77% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45669959 3.53% 77.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41606825 3.22% 80.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7021986 0.54% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 240462043 18.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1279053519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.306135 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.583403 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 450209575 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79019815 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 608453320 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10020119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131350690 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33655569 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12307 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3205531959 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46810 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131350690 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 478839352 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 32033074 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25872 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 588505763 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48298768 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3118953725 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 371 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 8014 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42155636 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2071308237 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3619384197 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3501684594 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117699603 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305400 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.570365 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 452871359 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80658875 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 614115226 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9960098 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134823295 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 34649231 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12312 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3231646724 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46688 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134823295 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 482927881 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33597057 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26321 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 592678256 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48376043 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3142025534 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 359 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42577596 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2088048295 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3654580538 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3537192552 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117387986 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 686339167 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4232 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 137 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 140575935 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 734762265 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 354500186 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67932920 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9138793 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2625466002 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2176735177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17945547 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 802302909 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 703322223 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 83 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1279053519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.701833 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.797036 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 703079225 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4247 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 139 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 143016933 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 739120184 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 360450433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67842482 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9359459 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2647443518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 119 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2196739038 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17945817 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 824288888 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 711675230 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1292428853 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.699698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805222 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 464081398 36.28% 36.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 216592353 16.93% 53.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 250622762 19.59% 72.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121884176 9.53% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104836053 8.20% 90.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 77987896 6.10% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21570720 1.69% 98.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17288528 1.35% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4189633 0.33% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470829214 36.43% 36.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 219635474 16.99% 53.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 252835920 19.56% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120249082 9.30% 82.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106312850 8.23% 90.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 78591497 6.08% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21017975 1.63% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17286985 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5669856 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1279053519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1292428853 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1140853 3.19% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24076891 67.30% 70.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10558644 29.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1140834 3.16% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24068551 66.72% 69.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10866173 30.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1247700404 57.32% 57.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16695 0.00% 57.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 28729941 1.32% 58.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254693 0.38% 59.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586556392 26.95% 86.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 298269645 13.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1257954368 57.26% 57.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29223285 1.33% 58.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254700 0.38% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204654 0.33% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 590393009 26.88% 86.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 303689578 13.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2176735177 # Type of FU issued -system.cpu.iq.rate 1.701667 # Inst issue rate -system.cpu.iq.fu_busy_cnt 35776388 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016436 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5534048167 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3341408955 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2010160977 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 152197641 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 86432816 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 74384435 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2134737053 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77771760 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67976479 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2196739038 # Type of FU issued +system.cpu.iq.rate 1.699531 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36075558 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016422 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5585448848 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3387972541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2024033733 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 154479456 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 83833082 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75371142 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2153745376 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 79066468 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69378492 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 223692239 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13198 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 75649 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 143705290 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 228050158 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2255425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75959 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 149655537 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4417 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 29 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4423 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131350690 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3811054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 200562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2981894857 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2707472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 734762265 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 354500186 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131033 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4888 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 75649 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27118847 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31958 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27150805 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2088347607 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526312810 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 88387570 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134823295 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4267154 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 460832 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3006059050 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2702145 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 739120184 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 360450433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 119 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 451591 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5232 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75959 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27593158 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31610 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27624768 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2105923301 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 528979869 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 90815737 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 356428733 # number of nop insts executed -system.cpu.iew.exec_refs 813671363 # number of memory reference insts executed -system.cpu.iew.exec_branches 280895404 # Number of branches executed -system.cpu.iew.exec_stores 287358553 # Number of stores executed -system.cpu.iew.exec_rate 1.632570 # Inst execution rate -system.cpu.iew.wb_sent 2087345359 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2084545412 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1181911333 # num instructions producing a value -system.cpu.iew.wb_consumers 1746825923 # num instructions consuming a value +system.cpu.iew.exec_nop 358615413 # number of nop insts executed +system.cpu.iew.exec_refs 821261997 # number of memory reference insts executed +system.cpu.iew.exec_branches 282350798 # Number of branches executed +system.cpu.iew.exec_stores 292282128 # Number of stores executed +system.cpu.iew.exec_rate 1.629270 # Inst execution rate +system.cpu.iew.wb_sent 2102194150 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2099404875 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1185212781 # num instructions producing a value +system.cpu.iew.wb_consumers 1754721969 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.629598 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.676605 # average fanout of values written-back +system.cpu.iew.wb_rate 1.624227 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675442 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 956239558 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 980398498 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27085717 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1147702829 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.750442 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504523 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27578641 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1157605558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.735468 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.494432 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 533397723 46.48% 46.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 226612269 19.74% 66.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 118218768 10.30% 76.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56744377 4.94% 81.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50032490 4.36% 85.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24020067 2.09% 87.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19167450 1.67% 89.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15607807 1.36% 90.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103901878 9.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 541345046 46.76% 46.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227581474 19.66% 66.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119272187 10.30% 76.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56742029 4.90% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 51019589 4.41% 86.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24162951 2.09% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18255182 1.58% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15605334 1.35% 91.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103621766 8.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1147702829 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1157605558 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103901878 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103621766 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4003391703 # The number of ROB reads -system.cpu.rob.rob_writes 6061807983 # The number of ROB writes -system.cpu.timesIdled 3462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 124296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4037733484 # The number of ROB reads +system.cpu.rob.rob_writes 6113598013 # The number of ROB writes +system.cpu.timesIdled 3574 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 127410 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.701672 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.701672 # CPI: Total CPI of All Threads -system.cpu.ipc 1.425168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.425168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2657999656 # number of integer regfile reads -system.cpu.int_regfile_writes 1510398630 # number of integer regfile writes -system.cpu.fp_regfile_reads 80463471 # number of floating regfile reads -system.cpu.fp_regfile_writes 53540440 # number of floating regfile writes +system.cpu.cpi 0.709010 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.709010 # CPI: Total CPI of All Threads +system.cpu.ipc 1.410417 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.410417 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2681938582 # number of integer regfile reads +system.cpu.int_regfile_writes 1518871452 # number of integer regfile writes +system.cpu.fp_regfile_reads 81943465 # number of floating regfile reads +system.cpu.fp_regfile_writes 54033824 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8417 # number of replacements -system.cpu.icache.tagsinuse 1667.677082 # Cycle average of tags in use -system.cpu.icache.total_refs 398450176 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39306.518299 # Average number of references to valid blocks. +system.cpu.icache.replacements 8410 # number of replacements +system.cpu.icache.tagsinuse 1670.523326 # Cycle average of tags in use +system.cpu.icache.total_refs 401426768 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10133 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39615.786835 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1667.677082 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.814295 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.814295 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 398450176 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398450176 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398450176 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398450176 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398450176 # number of overall hits -system.cpu.icache.overall_hits::total 398450176 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11376 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11376 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11376 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11376 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11376 # number of overall misses -system.cpu.icache.overall_misses::total 11376 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188382000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188382000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188382000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188382000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188382000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188382000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398461552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398461552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398461552 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398461552 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398461552 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398461552 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16559.599156 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16559.599156 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16559.599156 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16559.599156 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16559.599156 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16559.599156 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1670.523326 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.815685 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.815685 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 401426768 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 401426768 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 401426768 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 401426768 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 401426768 # number of overall hits +system.cpu.icache.overall_hits::total 401426768 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11347 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11347 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11347 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11347 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11347 # number of overall misses +system.cpu.icache.overall_misses::total 11347 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 204563500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 204563500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 204563500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 204563500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 204563500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 204563500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 401438115 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 401438115 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 401438115 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 401438115 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 401438115 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 401438115 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.980964 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18027.980964 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18027.980964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18027.980964 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,296 +390,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1238 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1238 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1238 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1238 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1238 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1238 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10138 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10138 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10138 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10138 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10138 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10138 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122862500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 122862500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122862500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 122862500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122862500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122862500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1213 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1213 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1213 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1213 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1213 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10134 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10134 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10134 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10134 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10134 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10134 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139352000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 139352000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139352000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 139352000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139352000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 139352000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12119.007694 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12119.007694 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12119.007694 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12119.007694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12119.007694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12119.007694 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13750.937438 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13750.937438 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13750.937438 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13750.937438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13750.937438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13750.937438 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527982 # number of replacements -system.cpu.dcache.tagsinuse 4095.064488 # Cycle average of tags in use -system.cpu.dcache.total_refs 666017344 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532078 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 434.715037 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 264095000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.064488 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999772 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999772 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 455774339 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 455774339 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210242956 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210242956 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 666017295 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 666017295 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 666017295 # number of overall hits -system.cpu.dcache.overall_hits::total 666017295 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928410 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1928410 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 551940 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 551940 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2480350 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2480350 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2480350 # number of overall misses -system.cpu.dcache.overall_misses::total 2480350 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71225328000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71225328000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20805642991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20805642991 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 20500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92030970991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92030970991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92030970991 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92030970991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 457702749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 457702749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1528066 # number of replacements +system.cpu.dcache.tagsinuse 4095.024861 # Cycle average of tags in use +system.cpu.dcache.total_refs 667221349 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1532162 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 435.477025 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 286461000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.024861 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999762 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999762 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 457042035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 457042035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210179266 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210179266 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 48 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 48 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667221301 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667221301 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667221301 # number of overall hits +system.cpu.dcache.overall_hits::total 667221301 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928301 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928301 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 615630 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 615630 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2543931 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2543931 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2543931 # number of overall misses +system.cpu.dcache.overall_misses::total 2543931 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609230000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76609230000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362374985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30362374985 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106971604985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106971604985 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106971604985 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106971604985 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 458970336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458970336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 50 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 50 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 668497645 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 668497645 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 668497645 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 668497645 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004213 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004213 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002618 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002618 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.020000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.020000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003710 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003710 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003710 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003710 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36934.743130 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36934.743130 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37695.479565 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37695.479565 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37104.026041 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37104.026041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37104.026041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37104.026041 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 98500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 48 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 48 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669765232 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669765232 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669765232 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669765232 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002921 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002921 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003798 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003798 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003798 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003798 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.875316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.875316 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.193322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.193322 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42049.727365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42049.727365 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 174500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6156.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9184.210526 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109405 # number of writebacks -system.cpu.dcache.writebacks::total 109405 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467937 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467937 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480335 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 480335 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 948272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 948272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 948272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 948272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460473 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460473 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71605 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71605 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1532078 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1532078 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1532078 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1532078 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49721165500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49721165500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2483602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2483602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52204767500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52204767500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52204767500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52204767500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003191 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003191 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 109390 # number of writebacks +system.cpu.dcache.writebacks::total 109390 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467746 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467746 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 544023 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 544023 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1011769 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1011769 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1011769 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1011769 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460555 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460555 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71607 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71607 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1532162 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532162 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532162 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532162 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266374000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266374000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176553000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176553000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 53442927000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 53442927000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002292 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002292 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002292 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002292 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34044.563302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34044.563302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34684.756651 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34684.756651 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34074.484132 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34074.484132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34074.484132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34074.484132 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.940516 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.940516 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44360.928401 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44360.928401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480674 # number of replacements -system.cpu.l2cache.tagsinuse 32705.756030 # Cycle average of tags in use -system.cpu.l2cache.total_refs 66279 # Total number of references to valid blocks. +system.cpu.l2cache.replacements 1480672 # number of replacements +system.cpu.l2cache.tagsinuse 32700.801266 # Cycle average of tags in use +system.cpu.l2cache.total_refs 66336 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.043795 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.043832 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3232.284223 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 45.882783 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29427.589024 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.098641 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001400 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.898059 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998100 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7148 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51323 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 58471 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109405 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109405 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7148 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 56075 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 63223 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7148 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 56075 # number of overall hits -system.cpu.l2cache.overall_hits::total 63223 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2990 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1409150 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1412140 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66853 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66853 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2990 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1476003 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1478993 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2990 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1476003 # 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mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963356 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.958968 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32509.181970 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.755946 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.906338 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.071858 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.071858 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index acb7a4c77..77bc7da26 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 85893d278..af38cd121 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:15:06 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:50:30 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2813377164000 because target called exit() +Exiting @ tick 2813572242000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 9b3a7daff..ed560b063 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.813377 # Number of seconds simulated -sim_ticks 2813377164000 # Number of ticks simulated -final_tick 2813377164000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.813572 # Number of seconds simulated +sim_ticks 2813572242000 # Number of ticks simulated +final_tick 2813572242000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2127881 # Simulator instruction rate (inst/s) -host_op_rate 2127880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2979874149 # Simulator tick rate (ticks/s) -host_mem_usage 227924 # Number of bytes of host memory used -host_seconds 944.13 # Real time elapsed on the host +host_inst_rate 1893151 # Simulator instruction rate (inst/s) +host_op_rate 1893151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2651343461 # Simulator tick rate (ticks/s) +host_mem_usage 227888 # Number of bytes of host memory used +host_seconds 1061.19 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475279 # Nu system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33560326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33614400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1521827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1521827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1521827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33560326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35136226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33558000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33612069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54069 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54069 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1521721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1521721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1521721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33558000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35133790 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5626754328 # number of cpu cycles simulated +system.cpu.numCycles 5627144484 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5626754328 # Number of busy cycles +system.cpu.num_busy_cycles 5627144484 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.423352 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.417406 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.423352 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721886 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721886 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1478.417406 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.721883 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.721883 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 248178000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 248178000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 248178000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 248178000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 248178000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 248178000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 248319000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 248319000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 248319000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 248319000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 248319000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 248319000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23421.857305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23421.857305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23421.857305 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23435.164213 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23435.164213 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216531000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216531000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216531000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216531000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216531000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216531000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.204600 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.192384 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.204600 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1063975000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.192384 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999803 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999803 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567740000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79567740000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3815994000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3815994000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83383734000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83383734000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83383734000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83383734000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567803000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79567803000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3816006000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3816006000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83383809000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83383809000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83383809000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83383809000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.024227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.024227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54494.043698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54494.043698 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54494.092713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54494.092713 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193227000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193227000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793377000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78793377000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793377000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78793377000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1479705 # number of replacements -system.cpu.l2cache.tagsinuse 32704.227313 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32703.875584 # Cycle average of tags in use system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3254.893374 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.487953 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29415.845986 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.099331 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3255.326122 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.503711 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29415.045751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.099345 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.897700 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.897676 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998043 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 420e789e0..69901d605 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 95a99c94b..bf499b85a 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:01:11 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:07:10 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 734755023500 because target called exit() +Exiting @ tick 735462942500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index abd280906..7a9f62c0c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.734755 # Number of seconds simulated -sim_ticks 734755023500 # Number of ticks simulated -final_tick 734755023500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.735463 # Number of seconds simulated +sim_ticks 735462942500 # Number of ticks simulated +final_tick 735462942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119232 # Simulator instruction rate (inst/s) -host_op_rate 162378 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63282228 # Simulator tick rate (ticks/s) -host_mem_usage 243808 # Number of bytes of host memory used -host_seconds 11610.76 # Real time elapsed on the host -sim_insts 1384372850 # Number of instructions simulated -sim_ops 1885327602 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94510912 # Number of bytes read from this memory -system.physmem.bytes_read::total 94716672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476733 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479948 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 280039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 128629147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128909186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 280039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 280039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5757478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5757478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5757478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 280039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 128629147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134666664 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 115593 # Simulator instruction rate (inst/s) +host_op_rate 157422 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61409842 # Simulator tick rate (ticks/s) +host_mem_usage 243732 # Number of bytes of host memory used +host_seconds 11976.30 # Real time elapsed on the host +sim_insts 1384378705 # Number of instructions simulated +sim_ops 1885333457 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 209152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94513152 # Number of bytes read from this memory +system.physmem.bytes_read::total 94722304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 209152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 209152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3268 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476768 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1480036 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 284381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128508381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128792762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 284381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 284381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5751849 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5751849 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5751849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 284381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128508381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134544612 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1469510048 # number of cpu cycles simulated +system.cpu.numCycles 1470925886 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 526868038 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 401113446 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 36046358 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 383398262 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 286508671 # Number of BTB hits +system.cpu.BPredUnit.lookups 526944807 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 400998639 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 36103831 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 389912593 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 290078755 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 60655682 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2811201 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 448614021 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2626557864 # Number of instructions fetch has processed -system.cpu.fetch.Branches 526868038 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 347164353 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 716084096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 226374824 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 100079168 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20420 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 419610687 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12785505 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1449541071 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.542405 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156280 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 59371448 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2810327 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 451184041 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2630280787 # Number of instructions fetch has processed +system.cpu.fetch.Branches 526944807 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 349450203 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 714901139 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 225817309 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 101657894 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 20337 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 420935290 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11687737 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1451892883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.541647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.159630 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 733526710 50.60% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 55834579 3.85% 54.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113825896 7.85% 62.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72745123 5.02% 67.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 84690661 5.84% 73.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54721422 3.78% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 33849353 2.34% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 34645380 2.39% 81.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 265701947 18.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 737052267 50.76% 50.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55648987 3.83% 54.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113021811 7.78% 62.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71058557 4.89% 67.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 83474414 5.75% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 55105836 3.80% 76.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35245314 2.43% 79.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 35853884 2.47% 81.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 265431813 18.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1449541071 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.358533 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.787370 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 497288026 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79567524 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 676485575 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11475102 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 184724844 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 81162192 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 16785 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3548614330 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 38542 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 184724844 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 535414239 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 30600962 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 541148 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 648147088 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50112790 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3434293747 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 117 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4398993 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40741019 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1775 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3359442434 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16257634697 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15596931258 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 660703439 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993143706 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1366298728 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50062 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45371 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 137456980 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1058714008 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 577829073 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 31866160 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36849262 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3203795171 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52627 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2727879490 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 26513766 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1318072615 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3048733772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 30791 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1449541071 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.881892 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914534 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1451892883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.358240 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.788180 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 498609504 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80967892 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 677644967 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10558484 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 184112036 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 82169847 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 15539 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3562988403 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 34450 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 184112036 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 537763866 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 32181538 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 530906 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 647549947 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49754590 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3439334544 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4507727 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40704108 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1637 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3357877059 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16273276362 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15612337004 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 660939358 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153074 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1364723985 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 45755 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138448530 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1057693537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 579697033 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 32301976 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40224751 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3204253855 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55204 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2728539607 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 26296633 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1318520975 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3049786617 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 32197 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1451892883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.879298 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.913242 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 528205619 36.44% 36.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 200385301 13.82% 50.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 218048243 15.04% 65.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 179845166 12.41% 77.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 155269867 10.71% 88.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 101678601 7.01% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47766137 3.30% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10944186 0.76% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7397951 0.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 529391229 36.46% 36.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201881649 13.90% 50.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217086646 14.95% 65.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180698536 12.45% 77.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 155303824 10.70% 88.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101627119 7.00% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47687061 3.28% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10818751 0.75% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7398068 0.51% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1449541071 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1451892883 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1786371 1.87% 1.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23899 0.03% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56927453 59.70% 61.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36612005 38.40% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1769730 1.85% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23897 0.03% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 57017691 59.74% 61.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36624161 38.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1265692730 46.40% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11246210 0.41% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876504 0.25% 47.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503517 0.20% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 65 0.00% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23431459 0.86% 48.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 901624360 33.05% 81.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 512129355 18.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1267852875 46.47% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11249841 0.41% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876502 0.25% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5509242 0.20% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 10 0.00% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23422716 0.86% 48.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 900241539 32.99% 81.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 512011592 18.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2727879490 # Type of FU issued -system.cpu.iq.rate 1.856319 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95349728 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034954 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6892702222 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4416661768 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2501406306 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 134461323 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 105324073 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59997583 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2754068673 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 69160545 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71273395 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2728539607 # Type of FU issued +system.cpu.iq.rate 1.854981 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95435479 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034977 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6896111029 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4417455828 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2500265065 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 134593180 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 105438972 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 60061785 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2754719800 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 69255286 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 70868561 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 427326375 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 261567 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1134338 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 300833324 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 426304733 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264948 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1116073 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 302700113 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 184724844 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16014821 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1979639 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3203920541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4008843 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1058714008 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 577829073 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42582 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1976809 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 591 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1134338 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 37198169 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9007131 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 46205300 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2628771663 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 847609803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 99107827 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 184112036 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17217570 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2222077 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3204383976 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3801477 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1057693537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 579697033 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 44065 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2220604 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1116073 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 37419443 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9018722 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46438165 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2627591050 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 846492275 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 100948557 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 72743 # number of nop insts executed -system.cpu.iew.exec_refs 1330077082 # number of memory reference insts executed -system.cpu.iew.exec_branches 361648549 # Number of branches executed -system.cpu.iew.exec_stores 482467279 # Number of stores executed -system.cpu.iew.exec_rate 1.788876 # Inst execution rate -system.cpu.iew.wb_sent 2589616129 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2561403889 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1477403496 # num instructions producing a value -system.cpu.iew.wb_consumers 2764851406 # num instructions consuming a value +system.cpu.iew.exec_nop 74917 # number of nop insts executed +system.cpu.iew.exec_refs 1329282286 # number of memory reference insts executed +system.cpu.iew.exec_branches 361424797 # Number of branches executed +system.cpu.iew.exec_stores 482790011 # Number of stores executed +system.cpu.iew.exec_rate 1.786352 # Inst execution rate +system.cpu.iew.wb_sent 2588656133 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2560326850 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1477151291 # num instructions producing a value +system.cpu.iew.wb_consumers 2761912490 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.743033 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534352 # average fanout of values written-back +system.cpu.iew.wb_rate 1.740623 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534829 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1384383866 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1885338618 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1318582287 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 21836 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41567877 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1264816229 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.490603 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.207767 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1384389721 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885344473 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1319039983 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 23007 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41626374 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1267780849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.487122 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.205349 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 584481462 46.21% 46.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 317753060 25.12% 71.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 101743247 8.04% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79200545 6.26% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52876697 4.18% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23864362 1.89% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17162643 1.36% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9180731 0.73% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78553482 6.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 586908423 46.29% 46.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 318188211 25.10% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 101915381 8.04% 79.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79184752 6.25% 85.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 52930899 4.18% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24002778 1.89% 91.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17056118 1.35% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9057246 0.71% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78537041 6.19% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1264816229 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384383866 # Number of instructions committed -system.cpu.commit.committedOps 1885338618 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1267780849 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384389721 # Number of instructions committed +system.cpu.commit.committedOps 1885344473 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908383382 # Number of memory references committed -system.cpu.commit.loads 631387633 # Number of loads committed +system.cpu.commit.refs 908385724 # Number of memory references committed +system.cpu.commit.loads 631388804 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291348996 # Number of branches committed +system.cpu.commit.branches 291350167 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653700675 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705359 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78553482 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78537041 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4390165307 # The number of ROB reads -system.cpu.rob.rob_writes 6592584661 # The number of ROB writes -system.cpu.timesIdled 1305443 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19968977 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384372850 # Number of Instructions Simulated -system.cpu.committedOps 1885327602 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384372850 # Number of Instructions Simulated -system.cpu.cpi 1.061499 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.061499 # CPI: Total CPI of All Threads -system.cpu.ipc 0.942064 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.942064 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12961850201 # number of integer regfile reads -system.cpu.int_regfile_writes 2434855102 # number of integer regfile writes -system.cpu.fp_regfile_reads 71417921 # number of floating regfile reads -system.cpu.fp_regfile_writes 51448336 # number of floating regfile writes -system.cpu.misc_regfile_reads 4106986212 # number of misc regfile reads -system.cpu.misc_regfile_writes 13773806 # number of misc regfile writes -system.cpu.icache.replacements 25589 # number of replacements -system.cpu.icache.tagsinuse 1654.450414 # Cycle average of tags in use -system.cpu.icache.total_refs 419572856 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 27281 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15379.672886 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4393609919 # The number of ROB reads +system.cpu.rob.rob_writes 6592898385 # The number of ROB writes +system.cpu.timesIdled 1319009 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19033003 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384378705 # Number of Instructions Simulated +system.cpu.committedOps 1885333457 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384378705 # Number of Instructions Simulated +system.cpu.cpi 1.062517 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.062517 # CPI: Total CPI of All Threads +system.cpu.ipc 0.941161 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.941161 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12954963873 # number of integer regfile reads +system.cpu.int_regfile_writes 2433899431 # number of integer regfile writes +system.cpu.fp_regfile_reads 71453474 # number of floating regfile reads +system.cpu.fp_regfile_writes 51512029 # number of floating regfile writes +system.cpu.misc_regfile_reads 4110345957 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776148 # number of misc regfile writes +system.cpu.icache.replacements 27727 # number of replacements +system.cpu.icache.tagsinuse 1657.357291 # Cycle average of tags in use +system.cpu.icache.total_refs 420895339 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 29422 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14305.463225 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1654.450414 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.807837 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.807837 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 419577538 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 419577538 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 419577538 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 419577538 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 419577538 # number of overall hits -system.cpu.icache.overall_hits::total 419577538 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33149 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33149 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33149 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33149 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33149 # number of overall misses -system.cpu.icache.overall_misses::total 33149 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 298308500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 298308500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 298308500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 298308500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 298308500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 298308500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 419610687 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 419610687 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 419610687 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 419610687 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 419610687 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 419610687 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000079 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000079 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000079 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000079 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000079 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000079 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8999.019578 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8999.019578 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8999.019578 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8999.019578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8999.019578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8999.019578 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1657.357291 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.809256 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.809256 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 420900012 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 420900012 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 420900012 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 420900012 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 420900012 # number of overall hits +system.cpu.icache.overall_hits::total 420900012 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35278 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35278 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35278 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35278 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35278 # number of overall misses +system.cpu.icache.overall_misses::total 35278 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 347510000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 347510000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 347510000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 347510000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 347510000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 347510000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 420935290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 420935290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 420935290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 420935290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 420935290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 420935290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9850.615114 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 9850.615114 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 9850.615114 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 9850.615114 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,254 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 781 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 781 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 781 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 781 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 781 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32368 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32368 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32368 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32368 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32368 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32368 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 180567000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 180567000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 180567000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 180567000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 180567000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 180567000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000077 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000077 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5578.565250 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5578.565250 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5578.565250 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5578.565250 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5578.565250 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5578.565250 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 933 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 933 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 933 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 933 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 933 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 933 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34345 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 34345 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 34345 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 34345 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 34345 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 34345 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 217293500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 217293500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 217293500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 217293500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 217293500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 217293500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6326.787014 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6326.787014 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532821 # number of replacements -system.cpu.dcache.tagsinuse 4094.970368 # Cycle average of tags in use -system.cpu.dcache.total_refs 1034449788 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536917 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 673.068089 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 277219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.970368 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999749 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999749 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 758296274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 758296274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276114755 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276114755 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10674 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10674 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10437 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10437 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1034411029 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1034411029 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1034411029 # number of overall hits -system.cpu.dcache.overall_hits::total 1034411029 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2832781 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2832781 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 820923 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 820923 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3653704 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3653704 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3653704 # number of overall misses -system.cpu.dcache.overall_misses::total 3653704 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 761129055 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1532802 # number of replacements +system.cpu.dcache.tagsinuse 4094.906416 # Cycle average of tags in use +system.cpu.dcache.total_refs 1033702432 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1536898 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 672.590134 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.906416 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 757546654 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 757546654 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276115180 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276115180 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11970 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11970 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11608 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11608 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1033661834 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1033661834 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1033661834 # number of overall hits +system.cpu.dcache.overall_hits::total 1033661834 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2867388 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2867388 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 820498 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 820498 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3687886 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3687886 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3687886 # number of overall misses +system.cpu.dcache.overall_misses::total 3687886 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 99520769500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 99520769500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963338500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33963338500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 216500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133484108000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133484108000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133484108000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133484108000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 760414042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 760414042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10677 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10677 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10437 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10437 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1038064733 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1038064733 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1038064733 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1038064733 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003722 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003722 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002964 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002964 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000281 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000281 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003520 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003520 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003520 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003520 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32305.167960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32305.167960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34811.427503 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34811.427503 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32868.280381 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32868.280381 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32868.280381 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32868.280381 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11976 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11976 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11608 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11608 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1037349720 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1037349720 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1037349720 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1037349720 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003771 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003771 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000501 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000501 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003555 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003555 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003555 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003555 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34707.814045 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34707.814045 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41393.566468 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41393.566468 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36083.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 36083.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36195.291286 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36195.291286 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108625 # number of writebacks -system.cpu.dcache.writebacks::total 108625 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1368436 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1368436 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743264 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743264 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2111700 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2111700 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2111700 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2111700 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464345 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464345 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77659 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77659 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1542004 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1542004 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1542004 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1542004 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49970798500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49970798500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2507122500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2507122500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52477921000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52477921000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52477921000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52477921000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 108638 # number of writebacks +system.cpu.dcache.writebacks::total 108638 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1403027 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1403027 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743038 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947870 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999410 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999410 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910531 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910531 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960841 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.946138 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960841 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.946138 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31076.360809 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.985782 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.002552 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks +system.cpu.l2cache.writebacks::total 66098 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3268 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410687 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1413955 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4920 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4920 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66081 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476768 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1480036 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3268 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1476768 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1480036 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105473000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44226810500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44332283500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152520000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152520000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105473000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46276018500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46381491500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105473000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46276018500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46381491500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111070 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963347 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946560 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999391 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999391 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910985 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910985 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111070 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960876 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.944912 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111070 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960876 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.944912 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32274.479804 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.256870 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.390667 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.809625 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.809625 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31076.360809 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.935074 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.957723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31076.360809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.935074 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.957723 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.547661 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.547661 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index a14c026cf..350b3e880 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index e82eb191d..2b2490099 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:12:18 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 16:24:15 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2369826854000 because target called exit() +Exiting @ tick 2369931974000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index a105f9616..8787dc4d5 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.369827 # Number of seconds simulated -sim_ticks 2369826854000 # Number of ticks simulated -final_tick 2369826854000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.369932 # Number of seconds simulated +sim_ticks 2369931974000 # Number of ticks simulated +final_tick 2369931974000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1185646 # Simulator instruction rate (inst/s) -host_op_rate 1608413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2033704433 # Simulator tick rate (ticks/s) -host_mem_usage 241756 # Number of bytes of host memory used -host_seconds 1165.28 # Real time elapsed on the host +host_inst_rate 1141587 # Simulator instruction rate (inst/s) +host_op_rate 1548644 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1958218374 # Simulator tick rate (ticks/s) +host_mem_usage 241676 # Number of bytes of host memory used +host_seconds 1210.25 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 1475585 # Nu system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39849932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39910885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785082 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785082 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39849932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41695968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 60950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39848165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39909115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60950 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60950 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1785003 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1785003 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1785003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39848165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41694118 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4739653708 # number of cpu cycles simulated +system.cpu.numCycles 4739863948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1381604339 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 908382479 # nu system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4739653708 # Number of busy cycles +system.cpu.num_busy_cycles 4739863948 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.324421 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1392.322496 # Cycle average of tags in use system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.324421 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1392.322496 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.679845 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.679845 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 19803 # n system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 372036000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 372036000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 372036000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 372133000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 372133000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 372133000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 372133000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 372133000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 372133000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18786.850477 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18786.850477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18786.850477 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18791.748725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18791.748725 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18791.748725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18791.748725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18791.748725 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 19803 system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312627000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312627000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312627000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312627000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312724000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312724000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312724000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312724000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312724000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312724000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15786.850477 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15791.748725 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15791.748725 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15791.748725 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15791.748725 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.960317 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.950469 # Cycle average of tags in use system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 997872000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.960317 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 1004561000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.950469 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999744 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999744 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650886000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79650886000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794826000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3794826000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83445712000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83445712000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83445712000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83445712000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650958000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79650958000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794840000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3794840000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83445798000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83445798000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83445798000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83445798000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.799723 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.799723 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54409.773267 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54409.773267 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.849009 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.849009 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.247595 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.247595 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54409.829342 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.829342 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54409.829342 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268339000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268339000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576500000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576500000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844839000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78844839000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844839000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78844839000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.849009 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.849009 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.247595 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.247595 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.829342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.829342 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1478696 # number of replacements -system.cpu.l2cache.tagsinuse 32689.777876 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32689.689328 # Cycle average of tags in use system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3194.588699 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.929350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29462.259827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 3194.581985 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 32.931287 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29462.176056 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.097491 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.899117 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997613 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.899114 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997610 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits |